| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| op0 | |||||||||||||||||||||||||||||||
| Decode fields | Instruction details |
|---|---|
| op0 | |
| 0000x | Reserved |
| 00010 | Morello encodings |
| 00011 | UNALLOCATED |
| 001xx | UNALLOCATED |
| 100xx | Data Processing -- Immediate |
| 101xx | Branches, Exception Generating and System instructions |
| x1x0x | Loads and Stores |
| x101x | Data Processing -- Register |
| x111x | Data Processing -- Scalar Floating-Point and Advanced SIMD |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| op0 | 0000 | op1 | |||||||||||||||||||||||||||||
| Decode fields | Instruction details | |
|---|---|---|
| op0 | op1 | |
| 000 | 000000000 | UDF |
| 000 | 0001xxxxx | UNALLOCATED |
| != 000 | UNALLOCATED | |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| op0 | 00010 | op1 | op2 | op3 | |||||||||||||||||||||||||||
| Decode fields | Instruction details | |||
|---|---|---|---|---|
| op0 | op1 | op2 | op3 | |
| 000 | Morello add/subtract capability | |||
| 001 | morello_load_store_misc_1 | |||
| 010 | morello_load_store_misc_2 | |||
| 011 | morello_load_store_misc_3 | |||
| 100 | 00x | LDR (literal) | ||
| 100 | 01x | Morello load/store unsigned offset via alternate base | ||
| 100 | 1xx | Morello load/store register via alternate base | ||
| 101 | morello_load_store_misc_4 | |||
| 110 | 0xx | Morello load/store unsigned offset | ||
| 110 | 100 | Morello get/set system register | ||
| 110 | 101 | ADD (extended register) | ||
| 110 | 11x | morello_misc | ||
| 111 | Morello load/store unscaled immediate via alternate base | |||
These instructions are under Morello encodings.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | A | sh | imm12 | Cn | Cd | |||||||||||||||||||
| Decode fields | Instruction Details |
|---|---|
| A | |
| 0 | ADD (immediate) |
| 1 | SUB |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 00100010 | op0 | ||||||||||||||||||||||||||||||
| Decode fields | Instruction details |
|---|---|
| op0 | |
| 0 | Morello load/ exclusive |
| 1 | Morello load/store pair postindex |
These instructions are under morello_load_store_misc_1.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | L | op | Rs | o2 | Ct2 | Rn | Ct | ||||||||||||||||
These instructions are under morello_load_store_misc_1.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | L | imm7 | Ct2 | Rn | Ct | ||||||||||||||||||
| Decode fields | Instruction Details |
|---|---|
| L | |
| 0 | STP (post-indexed) |
| 1 | LDP (post-indexed) |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 01000010 | op0 | op1 | op2 | ||||||||||||||||||||||||||||
| Decode fields | Instruction details | ||
|---|---|---|---|
| op0 | op1 | op2 | |
| 0 | 0 | 0 | Morello load/store acquire/release capability via alternate base |
| 0 | 0 | 1 | Morello load/store acquire/release |
| 0 | 1 | Morello load/store acquire/release via alternate base | |
| 1 | Morello load/store pair | ||
These instructions are under morello_load_store_misc_2.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | L | 0 | Rs | 0 | Ct2 | Rn | Ct | ||||||||||||||||
| Decode fields | Instruction Details | ||
|---|---|---|---|
| L | Rs | Ct2 | |
| 0 | 11111 | 11111 | STLR (capability, alternate base) |
| 1 | 11111 | 11111 | LDAR (capability, alternate base) |
These instructions are under morello_load_store_misc_2.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | L | 0 | Rs | 1 | Ct2 | Rn | Ct | ||||||||||||||||
| Decode fields | Instruction Details | ||
|---|---|---|---|
| L | Rs | Ct2 | |
| 0 | 11111 | 11111 | STLR (capability, normal base) |
| 1 | 11111 | 11111 | LDAR (capability, normal base) |
These instructions are under morello_load_store_misc_2.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | L | 1 | Rs | op | Rt2 | Rn | Rt | ||||||||||||||||
| Decode fields | Instruction Details | |||
|---|---|---|---|---|
| L | Rs | op | Rt2 | |
| 0 | 11111 | 0 | 11111 | STLRB |
| 0 | 11111 | 1 | 11111 | STLR (integer) |
| 1 | 11111 | 0 | 11111 | LDARB |
| 1 | 11111 | 1 | 11111 | LDAR (integer) |
These instructions are under morello_load_store_misc_2.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | L | imm7 | Ct2 | Rn | Ct | ||||||||||||||||||
| Decode fields | Instruction Details |
|---|---|
| L | |
| 0 | STP (signed offset) |
| 1 | LDP (signed offset) |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 01100010 | op0 | ||||||||||||||||||||||||||||||
| Decode fields | Instruction details |
|---|---|
| op0 | |
| 0 | Morello load/store pair non-temporal |
| 1 | Morello load/store pair preindex |
These instructions are under morello_load_store_misc_3.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | L | imm7 | Ct2 | Rn | Ct | ||||||||||||||||||
These instructions are under morello_load_store_misc_3.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | L | imm7 | Ct2 | Rn | Ct | ||||||||||||||||||
| Decode fields | Instruction Details |
|---|---|
| L | |
| 0 | STP (pre-indexed) |
| 1 | LDP (pre-indexed) |
These instructions are under Morello encodings.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | L | imm9 | op | Rn | Rt | |||||||||||||||||
| Decode fields | Instruction Details | |
|---|---|---|
| L | op | |
| 0 | 00 | STR (unsigned offset, capability, alternate base) |
| 0 | 01 | STRB (unsigned offset) |
| 0 | 10 | STR (unsigned offset, integer) — word |
| 0 | 11 | STR (unsigned offset, integer) — doubleword |
| 1 | 00 | LDR (unsigned offset, capability, alternate base) |
| 1 | 01 | LDRB (unsigned offset) |
| 1 | 10 | LDR (unsigned offset, integer) — word |
| 1 | 11 | LDR (unsigned offset, integer) — doubleword |
These instructions are under Morello encodings.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | L | op | Rm | A | 1 | B | S | opc | Rn | Rt | |||||||||||||
| Decode fields | Instruction Details | ||
|---|---|---|---|
| L | op | opc | |
| 0 | 0 | 00 | STRB (register offset) |
| 0 | 0 | 01 | LDRSB — doubleword |
| 0 | 0 | 10 | LDRSH — doubleword |
| 0 | 0 | 11 | STRH |
| 0 | 1 | 00 | STR (register offset, integer) — word |
| 0 | 1 | 01 | STR (register offset, integer) — doubleword |
| 0 | 1 | 10 | STR (register offset, SIMD&FP) — 64-bit |
| 0 | 1 | 11 | STR (register offset, SIMD&FP) — 32-bit |
| 1 | 0 | 00 | LDRB (register offset) |
| 1 | 0 | 01 | LDRSB — word |
| 1 | 0 | 10 | LDRSH — word |
| 1 | 0 | 11 | LDRH |
| 1 | 1 | 00 | LDR (register offset, integer) — word |
| 1 | 1 | 01 | LDR (register offset, integer) — doubleword |
| 1 | 1 | 10 | LDR (register offset, SIMD&FP) — 64-bit |
| 1 | 1 | 11 | LDR (register offset, SIMD&FP) — 32-bit |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 10100010 | op0 | op1 | |||||||||||||||||||||||||||||
| Decode fields | Instruction details | |
|---|---|---|
| op0 | op1 | |
| 0 | xxxx00 | Morello load/store unscaled immediate |
| 0 | xxxx01 | Morello load/store immediate postindex |
| 0 | xxxx10 | Morello load/store immediate translated |
| 0 | xxxx11 | Morello load/store immediate preindex |
| 1 | 100000 | Morello swap |
| 1 | 110000 | LDAPR |
| 1 | x11111 | Morello compare and swap |
| 1 | x1xx10 | Morello load/store register |
These instructions are under morello_load_store_misc_4.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | opc | 0 | imm9 | 0 | 0 | Rn | Ct | |||||||||||||||||
| Decode fields | Instruction Details |
|---|---|
| opc | |
| 00 | STUR (capability, normal base) |
| 01 | LDUR (capability, normal base) |
These instructions are under morello_load_store_misc_4.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | opc | 0 | imm9 | 0 | 1 | Rn | Ct | |||||||||||||||||
| Decode fields | Instruction Details |
|---|---|
| opc | |
| 00 | STR (post-indexed) |
| 01 | LDR (post-indexed) |
These instructions are under morello_load_store_misc_4.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | opc | 0 | imm9 | 1 | 0 | Rn | Ct | |||||||||||||||||
These instructions are under morello_load_store_misc_4.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | opc | 0 | imm9 | 1 | 1 | Rn | Ct | |||||||||||||||||
| Decode fields | Instruction Details |
|---|---|
| opc | |
| 00 | STR (pre-indexed) |
| 01 | LDR (pre-indexed) |
These instructions are under morello_load_store_misc_4.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | opc | 1 | Cs | 1 | 0 | 0 | 0 | 0 | 0 | opc2 | ||||||||||||||
These instructions are under morello_load_store_misc_4.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | opc | 1 | opc2 | 1 | 1 | 1 | 1 | 1 | opc3 | |||||||||||||||
These instructions are under morello_load_store_misc_4.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | opc | 1 | Rm | A | 1 | B | S | 1 | 0 | Rn | Ct | |||||||||||||
| Decode fields | Instruction Details |
|---|---|
| opc | |
| 00 | STR (register offset, capability, normal base) |
| 01 | LDR (register offset, capability, normal base) |
These instructions are under Morello encodings.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | L | imm12 | Rn | Ct | |||||||||||||||||||
| Decode fields | Instruction Details |
|---|---|
| L | |
| 0 | STR (unsigned offset, capability, normal base) |
| 1 | LDR (unsigned offset, capability, normal base) |
These instructions are under Morello encodings.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | L | o0 | op1 | CRn | CRm | op2 | Ct | ||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1100001011 | op0 | op1 | op2 | op3 | |||||||||||||||||||||||||||
These instructions are under morello_misc.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | opc | 1 | 0 | 0 | Cn | Rd | ||||||||||
These instructions are under morello_misc.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | opc | 1 | 0 | 0 | Cn | Rd | |||||||||
These instructions are under morello_misc.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | opc | 1 | 0 | 0 | Cn | Cd | |||||||||
These instructions are under morello_misc.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | opc | 1 | 0 | 0 | Cn | 0 | 0 | 0 | 0 | 0 | |||||
| Decode fields | Instruction Details | |
|---|---|---|
| opc | Cn | |
| 00 | BR (indirect) | |
| 01 | BLR (indirect) | |
| 10 | RET | |
| 11 | 11111 | BX |
These instructions are under morello_misc.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | opc | 1 | 0 | 0 | Cn | 0 | 0 | 0 | 0 | 1 | |||||
These instructions are under morello_misc.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | opc | 1 | 0 | 0 | Cn | 0 | 0 | 0 | 1 | 0 | |||||
| Decode fields | Instruction Details |
|---|---|
| opc | |
| 00 | BRS (capability) |
| 01 | BLRS (capability) |
| 10 | RETS (capability) |
These instructions are under morello_misc.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | opc | 1 | 0 | 0 | Cn | 0 | 0 | 0 | 1 | 1 | |||||
These instructions are under morello_misc.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | opc | 1 | 0 | 0 | Cn | Ct | |||||||||
These instructions are under morello_misc.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | opc | 1 | 0 | 0 | Cn | Ct | |||||||||
These instructions are under morello_misc.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | opc | 1 | 0 | 0 | Cn | Rd | |||||||||
| Decode fields | Instruction Details |
|---|---|
| opc | |
| 00 | CVTD (to pointer) |
| 01 | CVTP (to pointer) |
These instructions are under morello_misc.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | opc | 1 | 0 | 0 | Rn | Cd | |||||||||
| Decode fields | Instruction Details |
|---|---|
| opc | |
| 00 | CVTD (to capability) |
| 01 | CVTP (to capability) |
| 10 | CVTDZ |
| 11 | CVTPZ |
These instructions are under morello_misc.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | opc | 1 | 0 | 0 | Rn | Rd | |||||||||
These instructions are under morello_misc.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | imm7 | 1 | 0 | 0 | Cn | 0 | 0 | 0 | 0 | op | ||||||||||
| Decode fields | Instruction Details |
|---|---|
| op | |
| 0 | BR (memory indirect) |
| 1 | BLR (memory indirect) |
These instructions are under morello_misc.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | Rm | 0 | opc | 0 | 0 | 0 | Cn | Cd | |||||||||||||
| Decode fields | Instruction Details |
|---|---|
| opc | |
| 00 | SCBNDS (register) |
| 01 | SCBNDSE |
| 10 | SCVALUE |
| 11 | SCOFF |
These instructions are under morello_misc.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | Cm | 0 | opc | 0 | 0 | 1 | Cn | Cd | |||||||||||||
These instructions are under morello_misc.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | Rm | 1 | 0 | op | 0 | 0 | 0 | Cn | Cd | ||||||||||||
| Decode fields | Instruction Details |
|---|---|
| op | |
| 0 | SCTAG |
| 1 | CLRPERM (register) |
These instructions are under morello_misc.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | Cm | 1 | opc | 0 | 0 | 1 | Cn | 0 | 0 | 0 | 0 | 0 | |||||||||
| Decode fields | Instruction Details |
|---|---|
| opc | |
| 00 | BRS (pair of capabilities) |
| 01 | BLRS (pair of capabilities) |
| 10 | RETS (pair of capabilities) |
These instructions are under morello_misc.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | Cm | 1 | opc | 0 | 0 | 1 | Cn | 0 | 0 | 0 | 0 | 1 | |||||||||
These instructions are under morello_misc.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | Cm | opc | 0 | 0 | 1 | 0 | Cn | Cd | |||||||||||||
| Decode fields | Instruction Details |
|---|---|
| opc | |
| 00 | SEAL (capability) |
| 01 | UNSEAL |
| 10 | CHKSSU |
These instructions are under morello_misc.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | imm6 | U | 0 | 1 | 1 | 0 | Cn | Cd | |||||||||||||
These instructions are under morello_misc.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | Rm | opc | 1 | 0 | 1 | 0 | Cn | Cd | |||||||||||||
| Decode fields | Instruction Details |
|---|---|
| opc | |
| 00 | BICFLGS (register) |
| 01 | ORRFLGS (register) |
| 10 | EORFLGS (register) |
| 11 | CTHI |
These instructions are under morello_misc.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | imm6 | S | 1 | 1 | 1 | 0 | Cn | Cd | |||||||||||||
| Decode fields | Instruction Details |
|---|---|
| S | |
| 0 | SCBNDS (immediate) — Unscaled |
| 1 | SCBNDS (immediate) — Scaled |
These instructions are under morello_misc.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | Rm | 0 | op | 0 | 1 | 1 | 0 | Cn | Cd | ||||||||||||
| Decode fields | Instruction Details |
|---|---|
| op | |
| 0 | CVT (to capability) |
| 1 | CVTZ |
These instructions are under morello_misc.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | Rm | A | 1 | B | S | L | 1 | Rn | Ct | ||||||||||||
| Decode fields | Instruction Details |
|---|---|
| L | |
| 0 | STR (register offset, capability, alternate base) |
| 1 | LDR (register offset, capability, alternate base) |
These instructions are under morello_misc.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | imm8 | != 11 | 0 | Cn | Cd | ||||||||||||||||
| opc | |||||||||||||||||||||||||||||||
The following constraints also apply to this encoding: opc != 11 && opc != 11
| Decode fields | Instruction Details |
|---|---|
| opc | |
| 00 | BICFLGS (immediate) |
| 01 | ORRFLGS (immediate) |
| 10 | EORFLGS (immediate) |
These instructions are under Morello encodings.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | op1 | V | imm9 | op2 | Rn | Rd | ||||||||||||||||||
| Decode fields | Instruction Details | ||
|---|---|---|---|
| op1 | V | op2 | |
| 00 | 0 | 00 | STURB |
| 00 | 0 | 01 | LDURB |
| 00 | 0 | 10 | LDURSB — doubleword |
| 00 | 0 | 11 | LDURSB — word |
| 00 | 1 | 00 | STUR (SIMD&FP) — 8-bit |
| 00 | 1 | 01 | LDUR (SIMD&FP) — 8-bit |
| 00 | 1 | 10 | STUR (SIMD&FP) — 128-bit |
| 00 | 1 | 11 | LDUR (SIMD&FP) — 128-bit |
| 01 | 0 | 00 | STURH |
| 01 | 0 | 01 | LDURH |
| 01 | 0 | 10 | LDURSH — doubleword |
| 01 | 0 | 11 | LDURSH — word |
| 01 | 1 | 00 | STUR (SIMD&FP) — 16-bit |
| 01 | 1 | 01 | LDUR (SIMD&FP) — 16-bit |
| 10 | 0 | 00 | STUR (integer) — word |
| 10 | 0 | 01 | LDUR (integer) — word |
| 10 | 0 | 10 | LDURSW |
| 10 | 0 | 11 | STUR (capability, alternate base) |
| 10 | 1 | 00 | STUR (SIMD&FP) — 32-bit |
| 10 | 1 | 01 | LDUR (SIMD&FP) — 32-bit |
| 11 | 0 | 00 | STUR (integer) — doubleword |
| 11 | 0 | 01 | LDUR (integer) — doubleword |
| 11 | 0 | 11 | LDUR (capability, alternate base) |
| 11 | 1 | 00 | STUR (SIMD&FP) — 64-bit |
| 11 | 1 | 01 | LDUR (SIMD&FP) — 64-bit |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 100 | op0 | ||||||||||||||||||||||||||||||
| Decode fields | Instruction details |
|---|---|
| op0 | |
| 00x | aarch64_adr |
| 010 | Add/subtract (immediate) |
| 011 | Add/subtract (immediate, with tags) |
| 100 | Logical (immediate) |
| 101 | Move wide (immediate) |
| 110 | Bitfield |
| 111 | Extract |
These instructions are under Data Processing -- Immediate.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| op | immlo | 1 | 0 | 0 | 0 | 0 | P | immhi | Rd | ||||||||||||||||||||||
These instructions are under Data Processing -- Immediate.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | op | S | 1 | 0 | 0 | 0 | 1 | 0 | sh | imm12 | Rn | Rd | |||||||||||||||||||
| Decode fields | Instruction Details | ||
|---|---|---|---|
| sf | op | S | |
| 0 | 0 | 0 | ADD (immediate) — 32-bit |
| 0 | 0 | 1 | ADDS (immediate) — 32-bit |
| 0 | 1 | 0 | SUB (immediate) — 32-bit |
| 0 | 1 | 1 | SUBS (immediate) — 32-bit |
| 1 | 0 | 0 | ADD (immediate) — 64-bit |
| 1 | 0 | 1 | ADDS (immediate) — 64-bit |
| 1 | 1 | 0 | SUB (immediate) — 64-bit |
| 1 | 1 | 1 | SUBS (immediate) — 64-bit |
These instructions are under Data Processing -- Immediate.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | op | S | 1 | 0 | 0 | 0 | 1 | 1 | o2 | uimm6 | op3 | uimm4 | Rn | Rd | |||||||||||||||||
| Decode fields | Instruction Details | ||
|---|---|---|---|
| sf | S | o2 | |
| 1 | UNALLOCATED | ||
| 0 | 0 | UNALLOCATED | |
| 1 | 1 | 0 | UNALLOCATED |
These instructions are under Data Processing -- Immediate.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | opc | 1 | 0 | 0 | 1 | 0 | 0 | N | immr | imms | Rn | Rd | |||||||||||||||||||
| Decode fields | Instruction Details | ||
|---|---|---|---|
| sf | opc | N | |
| 0 | 1 | UNALLOCATED | |
| 0 | 00 | 0 | AND (immediate) — 32-bit |
| 0 | 01 | 0 | ORR (immediate) — 32-bit |
| 0 | 10 | 0 | EOR (immediate) — 32-bit |
| 0 | 11 | 0 | ANDS (immediate) — 32-bit |
| 1 | 00 | AND (immediate) — 64-bit | |
| 1 | 01 | ORR (immediate) — 64-bit | |
| 1 | 10 | EOR (immediate) — 64-bit | |
| 1 | 11 | ANDS (immediate) — 64-bit | |
These instructions are under Data Processing -- Immediate.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | opc | 1 | 0 | 0 | 1 | 0 | 1 | hw | imm16 | Rd | |||||||||||||||||||||
These instructions are under Data Processing -- Immediate.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | opc | 1 | 0 | 0 | 1 | 1 | 0 | N | immr | imms | Rn | Rd | |||||||||||||||||||
These instructions are under Data Processing -- Immediate.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | op21 | 1 | 0 | 0 | 1 | 1 | 1 | N | o0 | Rm | imms | Rn | Rd | ||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| op0 | 101 | op1 | op2 | ||||||||||||||||||||||||||||
| Decode fields | Instruction details | ||
|---|---|---|---|
| op0 | op1 | op2 | |
| 010 | 0xxxxxxxxxxxxx | Conditional branch (immediate) | |
| 010 | 1xxxxxxxxxxxxx | UNALLOCATED | |
| 110 | 00xxxxxxxxxxxx | Exception generation | |
| 110 | 010000000x000x | UNALLOCATED | |
| 110 | 010000000x001x | UNALLOCATED | |
| 110 | 0100000010000x | UNALLOCATED | |
| 110 | 0100000010001x | UNALLOCATED | |
| 110 | 01000000110000 | UNALLOCATED | |
| 110 | 01000000110010 | 11111 | Hints |
| 110 | 01000000110010 | != 11111 | UNALLOCATED |
| 110 | 01000000110011 | Barriers | |
| 110 | 01000001xx000x | UNALLOCATED | |
| 110 | 01000001xx001x | UNALLOCATED | |
| 110 | 0100000xxx0100 | PSTATE | |
| 110 | 0100000xxx0101 | UNALLOCATED | |
| 110 | 0100000xxx011x | UNALLOCATED | |
| 110 | 0100000xxx1xxx | UNALLOCATED | |
| 110 | 0100x01xxxxxxx | System instructions | |
| 110 | 0100x1xxxxxxxx | System register move | |
| 110 | 0101xxxxxxxxxx | UNALLOCATED | |
| 110 | 011xxxxxxxxxxx | UNALLOCATED | |
| 110 | 1xxxxxxxxxxxxx | Unconditional branch (register) | |
| x00 | Unconditional branch (immediate) | ||
| x01 | 0xxxxxxxxxxxxx | Compare and branch (immediate) | |
| x01 | 1xxxxxxxxxxxxx | Test and branch (immediate) | |
| x11 | UNALLOCATED | ||
These instructions are under Branches, Exception Generating and System instructions.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 | 1 | 0 | o1 | imm19 | o0 | cond | |||||||||||||||||||||
| Decode fields | Instruction Details | |
|---|---|---|
| o1 | o0 | |
| 0 | 0 | B.cond |
| 0 | 1 | UNALLOCATED |
| 1 | UNALLOCATED | |
These instructions are under Branches, Exception Generating and System instructions.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | opc | imm16 | op2 | LL | ||||||||||||||||||||
| Decode fields | Instruction Details | ||
|---|---|---|---|
| opc | op2 | LL | |
| 001 | UNALLOCATED | ||
| 01x | UNALLOCATED | ||
| 1xx | UNALLOCATED | ||
| 000 | 000 | 00 | UNALLOCATED |
| 000 | 000 | 01 | SVC |
| 000 | 000 | 10 | HVC |
| 000 | 000 | 11 | SMC |
| 001 | 000 | x1 | UNALLOCATED |
| 001 | 000 | 00 | BRK |
| 001 | 000 | 1x | UNALLOCATED |
| 010 | 000 | x1 | UNALLOCATED |
| 010 | 000 | 00 | HLT |
| 010 | 000 | 1x | UNALLOCATED |
| 011 | 000 | 01 | UNALLOCATED |
| 011 | 000 | 1x | UNALLOCATED |
| 100 | 000 | UNALLOCATED | |
| 101 | 000 | 00 | UNALLOCATED |
| 101 | 000 | 01 | DCPS1 |
| 101 | 000 | 10 | DCPS2 |
| 101 | 000 | 11 | DCPS3 |
| 110 | 000 | UNALLOCATED | |
| 111 | 000 | UNALLOCATED | |
These instructions are under Branches, Exception Generating and System instructions.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | CRm | op2 | 1 | 1 | 1 | 1 | 1 | |||||
These instructions are under Branches, Exception Generating and System instructions.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | CRm | op2 | Rt | |||||||||
| Decode fields | Instruction Details | ||
|---|---|---|---|
| CRm | op2 | Rt | |
| 000 | UNALLOCATED | ||
| 001 | != 11111 | UNALLOCATED | |
| 010 | 11111 | CLREX | |
| 101 | 11111 | DMB | |
| 110 | 11111 | ISB | |
| 111 | != 11111 | UNALLOCATED | |
| 111 | 11111 | SB | |
| != 0x00 | 100 | 11111 | DSB |
| 0000 | 100 | 11111 | SSBB |
| 0001 | 011 | UNALLOCATED | |
| 001x | 011 | UNALLOCATED | |
| 01xx | 011 | UNALLOCATED | |
| 0100 | 100 | 11111 | PSSBB |
| 1xxx | 011 | UNALLOCATED | |
These instructions are under Branches, Exception Generating and System instructions.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | op1 | 0 | 1 | 0 | 0 | CRm | op2 | Rt | |||||||||||
| Decode fields | Instruction Details |
|---|---|
| Rt | |
| != 11111 | UNALLOCATED |
| 11111 | MSR (immediate) |
These instructions are under Branches, Exception Generating and System instructions.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | L | 0 | 1 | op1 | CRn | CRm | op2 | Rt | ||||||||||||||
These instructions are under Branches, Exception Generating and System instructions.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | L | 1 | o0 | op1 | CRn | CRm | op2 | Rt | ||||||||||||||
| Decode fields | Instruction Details |
|---|---|
| L | |
| 0 | MSR (register) |
| 1 | MRS |
These instructions are under Branches, Exception Generating and System instructions.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 1 | 0 | 1 | 1 | opc | op2 | op3 | Rn | op4 | ||||||||||||||||||||
| Decode fields | Instruction Details | ||||
|---|---|---|---|---|---|
| opc | op2 | op3 | Rn | op4 | |
| != 11111 | UNALLOCATED | ||||
| 0000 | 11111 | 000000 | != 00000 | UNALLOCATED | |
| 0000 | 11111 | 000000 | 00000 | BR | |
| 0000 | 11111 | 000001 | UNALLOCATED | ||
| 0000 | 11111 | 000010 | != 11111 | UNALLOCATED | |
| 0000 | 11111 | 000011 | != 11111 | UNALLOCATED | |
| 0000 | 11111 | 0001xx | UNALLOCATED | ||
| 0000 | 11111 | 001xxx | UNALLOCATED | ||
| 0000 | 11111 | 01xxxx | UNALLOCATED | ||
| 0000 | 11111 | 1xxxxx | UNALLOCATED | ||
| 0001 | 11111 | 000000 | != 00000 | UNALLOCATED | |
| 0001 | 11111 | 000000 | 00000 | BLR | |
| 0001 | 11111 | 000001 | UNALLOCATED | ||
| 0001 | 11111 | 000010 | != 11111 | UNALLOCATED | |
| 0001 | 11111 | 000011 | != 11111 | UNALLOCATED | |
| 0001 | 11111 | 0001xx | UNALLOCATED | ||
| 0001 | 11111 | 001xxx | UNALLOCATED | ||
| 0001 | 11111 | 01xxxx | UNALLOCATED | ||
| 0001 | 11111 | 1xxxxx | UNALLOCATED | ||
| 0010 | 11111 | 000000 | != 00000 | UNALLOCATED | |
| 0010 | 11111 | 000000 | 00000 | RET | |
| 0010 | 11111 | 000001 | UNALLOCATED | ||
| 0010 | 11111 | 000010 | != 11111 | != 11111 | UNALLOCATED |
| 0010 | 11111 | 000011 | != 11111 | != 11111 | UNALLOCATED |
| 0010 | 11111 | 0001xx | UNALLOCATED | ||
| 0010 | 11111 | 001xxx | UNALLOCATED | ||
| 0010 | 11111 | 01xxxx | UNALLOCATED | ||
| 0010 | 11111 | 1xxxxx | UNALLOCATED | ||
| 0011 | 11111 | UNALLOCATED | |||
| 0100 | 11111 | 000000 | != 11111 | != 00000 | UNALLOCATED |
| 0100 | 11111 | 000000 | != 11111 | 00000 | UNALLOCATED |
| 0100 | 11111 | 000000 | 11111 | != 00000 | UNALLOCATED |
| 0100 | 11111 | 000000 | 11111 | 00000 | ERET |
| 0100 | 11111 | 000001 | UNALLOCATED | ||
| 0100 | 11111 | 000010 | != 11111 | != 11111 | UNALLOCATED |
| 0100 | 11111 | 000010 | != 11111 | 11111 | UNALLOCATED |
| 0100 | 11111 | 000010 | 11111 | != 11111 | UNALLOCATED |
| 0100 | 11111 | 000011 | != 11111 | != 11111 | UNALLOCATED |
| 0100 | 11111 | 000011 | != 11111 | 11111 | UNALLOCATED |
| 0100 | 11111 | 000011 | 11111 | != 11111 | UNALLOCATED |
| 0100 | 11111 | 0001xx | UNALLOCATED | ||
| 0100 | 11111 | 001xxx | UNALLOCATED | ||
| 0100 | 11111 | 01xxxx | UNALLOCATED | ||
| 0100 | 11111 | 1xxxxx | UNALLOCATED | ||
| 0101 | 11111 | != 000000 | UNALLOCATED | ||
| 0101 | 11111 | 000000 | != 11111 | != 00000 | UNALLOCATED |
| 0101 | 11111 | 000000 | != 11111 | 00000 | UNALLOCATED |
| 0101 | 11111 | 000000 | 11111 | != 00000 | UNALLOCATED |
| 0101 | 11111 | 000000 | 11111 | 00000 | DRPS |
| 011x | 11111 | UNALLOCATED | |||
| 1000 | 11111 | 00000x | UNALLOCATED | ||
| 1000 | 11111 | 0001xx | UNALLOCATED | ||
| 1000 | 11111 | 001xxx | UNALLOCATED | ||
| 1000 | 11111 | 01xxxx | UNALLOCATED | ||
| 1000 | 11111 | 1xxxxx | UNALLOCATED | ||
| 1001 | 11111 | 00000x | UNALLOCATED | ||
| 1001 | 11111 | 0001xx | UNALLOCATED | ||
| 1001 | 11111 | 001xxx | UNALLOCATED | ||
| 1001 | 11111 | 01xxxx | UNALLOCATED | ||
| 1001 | 11111 | 1xxxxx | UNALLOCATED | ||
| 101x | 11111 | UNALLOCATED | |||
| 11xx | 11111 | UNALLOCATED | |||
These instructions are under Branches, Exception Generating and System instructions.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| op | 0 | 0 | 1 | 0 | 1 | imm26 | |||||||||||||||||||||||||
These instructions are under Branches, Exception Generating and System instructions.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | 0 | 1 | 1 | 0 | 1 | 0 | op | imm19 | Rt | ||||||||||||||||||||||
These instructions are under Branches, Exception Generating and System instructions.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| b5 | 0 | 1 | 1 | 0 | 1 | 1 | op | b40 | imm14 | Rt | |||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| op0 | 1 | op1 | 0 | op2 | op3 | op4 | |||||||||||||||||||||||||
These instructions are under Loads and Stores.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 0 | 0 | 1 | 1 | 0 | 0 | 0 | L | 0 | 0 | 0 | 0 | 0 | 0 | opcode | size | Rn | Rt | ||||||||||||
| Decode fields | Instruction Details | |
|---|---|---|
| L | opcode | |
| 0 | 0000 | ST4 (multiple structures) |
| 0 | 0001 | UNALLOCATED |
| 0 | 0010 | ST1 (multiple structures) — four registers |
| 0 | 0011 | UNALLOCATED |
| 0 | 0100 | ST3 (multiple structures) |
| 0 | 0101 | UNALLOCATED |
| 0 | 0110 | ST1 (multiple structures) — three registers |
| 0 | 0111 | ST1 (multiple structures) — one register |
| 0 | 1000 | ST2 (multiple structures) |
| 0 | 1001 | UNALLOCATED |
| 0 | 1010 | ST1 (multiple structures) — two registers |
| 0 | 1011 | UNALLOCATED |
| 0 | 11xx | UNALLOCATED |
| 1 | 0000 | LD4 (multiple structures) |
| 1 | 0001 | UNALLOCATED |
| 1 | 0010 | LD1 (multiple structures) — four registers |
| 1 | 0011 | UNALLOCATED |
| 1 | 0100 | LD3 (multiple structures) |
| 1 | 0101 | UNALLOCATED |
| 1 | 0110 | LD1 (multiple structures) — three registers |
| 1 | 0111 | LD1 (multiple structures) — one register |
| 1 | 1000 | LD2 (multiple structures) |
| 1 | 1001 | UNALLOCATED |
| 1 | 1010 | LD1 (multiple structures) — two registers |
| 1 | 1011 | UNALLOCATED |
| 1 | 11xx | UNALLOCATED |
These instructions are under Loads and Stores.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 0 | 0 | 1 | 1 | 0 | 0 | 1 | L | 0 | Rm | opcode | size | Rn | Rt | ||||||||||||||||
These instructions are under Loads and Stores.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 0 | 0 | 1 | 1 | 0 | 1 | 0 | L | R | 0 | 0 | 0 | 0 | 0 | opcode | S | size | Rn | Rt | |||||||||||
| Decode fields | Instruction Details | ||||
|---|---|---|---|---|---|
| L | R | opcode | S | size | |
| 0 | 11x | UNALLOCATED | |||
| 0 | 0 | 000 | ST1 (single structure) — 8-bit | ||
| 0 | 0 | 001 | ST3 (single structure) — 8-bit | ||
| 0 | 0 | 010 | x0 | ST1 (single structure) — 16-bit | |
| 0 | 0 | 010 | x1 | UNALLOCATED | |
| 0 | 0 | 011 | x0 | ST3 (single structure) — 16-bit | |
| 0 | 0 | 011 | x1 | UNALLOCATED | |
| 0 | 0 | 100 | 00 | ST1 (single structure) — 32-bit | |
| 0 | 0 | 100 | 1x | UNALLOCATED | |
| 0 | 0 | 100 | 0 | 01 | ST1 (single structure) — 64-bit |
| 0 | 0 | 100 | 1 | 01 | UNALLOCATED |
| 0 | 0 | 101 | 00 | ST3 (single structure) — 32-bit | |
| 0 | 0 | 101 | 10 | UNALLOCATED | |
| 0 | 0 | 101 | 0 | 01 | ST3 (single structure) — 64-bit |
| 0 | 0 | 101 | 0 | 11 | UNALLOCATED |
| 0 | 0 | 101 | 1 | x1 | UNALLOCATED |
| 0 | 1 | 000 | ST2 (single structure) — 8-bit | ||
| 0 | 1 | 001 | ST4 (single structure) — 8-bit | ||
| 0 | 1 | 010 | x0 | ST2 (single structure) — 16-bit | |
| 0 | 1 | 010 | x1 | UNALLOCATED | |
| 0 | 1 | 011 | x0 | ST4 (single structure) — 16-bit | |
| 0 | 1 | 011 | x1 | UNALLOCATED | |
| 0 | 1 | 100 | 00 | ST2 (single structure) — 32-bit | |
| 0 | 1 | 100 | 10 | UNALLOCATED | |
| 0 | 1 | 100 | 0 | 01 | ST2 (single structure) — 64-bit |
| 0 | 1 | 100 | 0 | 11 | UNALLOCATED |
| 0 | 1 | 100 | 1 | x1 | UNALLOCATED |
| 0 | 1 | 101 | 00 | ST4 (single structure) — 32-bit | |
| 0 | 1 | 101 | 10 | UNALLOCATED | |
| 0 | 1 | 101 | 0 | 01 | ST4 (single structure) — 64-bit |
| 0 | 1 | 101 | 0 | 11 | UNALLOCATED |
| 0 | 1 | 101 | 1 | x1 | UNALLOCATED |
| 1 | 0 | 000 | LD1 (single structure) — 8-bit | ||
| 1 | 0 | 001 | LD3 (single structure) — 8-bit | ||
| 1 | 0 | 010 | x0 | LD1 (single structure) — 16-bit | |
| 1 | 0 | 010 | x1 | UNALLOCATED | |
| 1 | 0 | 011 | x0 | LD3 (single structure) — 16-bit | |
| 1 | 0 | 011 | x1 | UNALLOCATED | |
| 1 | 0 | 100 | 00 | LD1 (single structure) — 32-bit | |
| 1 | 0 | 100 | 1x | UNALLOCATED | |
| 1 | 0 | 100 | 0 | 01 | LD1 (single structure) — 64-bit |
| 1 | 0 | 100 | 1 | 01 | UNALLOCATED |
| 1 | 0 | 101 | 00 | LD3 (single structure) — 32-bit | |
| 1 | 0 | 101 | 10 | UNALLOCATED | |
| 1 | 0 | 101 | 0 | 01 | LD3 (single structure) — 64-bit |
| 1 | 0 | 101 | 0 | 11 | UNALLOCATED |
| 1 | 0 | 101 | 1 | x1 | UNALLOCATED |
| 1 | 0 | 110 | 0 | LD1R | |
| 1 | 0 | 110 | 1 | UNALLOCATED | |
| 1 | 0 | 111 | 0 | LD3R | |
| 1 | 0 | 111 | 1 | UNALLOCATED | |
| 1 | 1 | 000 | LD2 (single structure) — 8-bit | ||
| 1 | 1 | 001 | LD4 (single structure) — 8-bit | ||
| 1 | 1 | 010 | x0 | LD2 (single structure) — 16-bit | |
| 1 | 1 | 010 | x1 | UNALLOCATED | |
| 1 | 1 | 011 | x0 | LD4 (single structure) — 16-bit | |
| 1 | 1 | 011 | x1 | UNALLOCATED | |
| 1 | 1 | 100 | 00 | LD2 (single structure) — 32-bit | |
| 1 | 1 | 100 | 10 | UNALLOCATED | |
| 1 | 1 | 100 | 0 | 01 | LD2 (single structure) — 64-bit |
| 1 | 1 | 100 | 0 | 11 | UNALLOCATED |
| 1 | 1 | 100 | 1 | x1 | UNALLOCATED |
| 1 | 1 | 101 | 00 | LD4 (single structure) — 32-bit | |
| 1 | 1 | 101 | 10 | UNALLOCATED | |
| 1 | 1 | 101 | 0 | 01 | LD4 (single structure) — 64-bit |
| 1 | 1 | 101 | 0 | 11 | UNALLOCATED |
| 1 | 1 | 101 | 1 | x1 | UNALLOCATED |
| 1 | 1 | 110 | 0 | LD2R | |
| 1 | 1 | 110 | 1 | UNALLOCATED | |
| 1 | 1 | 111 | 0 | LD4R | |
| 1 | 1 | 111 | 1 | UNALLOCATED | |
These instructions are under Loads and Stores.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 0 | 0 | 1 | 1 | 0 | 1 | 1 | L | R | Rm | opcode | S | size | Rn | Rt | |||||||||||||||
These instructions are under Loads and Stores.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| size | 0 | 0 | 1 | 0 | 0 | 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt | |||||||||||||||||
| Decode fields | Instruction Details | Feature | |||||
|---|---|---|---|---|---|---|---|
| size | o2 | L | o1 | o0 | Rt2 | ||
| 1 | 1 | != 11111 | UNALLOCATED | - | |||
| 0x | 0 | 1 | != 11111 | UNALLOCATED | - | ||
| 00 | 0 | 0 | 0 | 0 | STXRB | - | |
| 00 | 0 | 0 | 0 | 1 | STLXRB | - | |
| 00 | 0 | 0 | 1 | 0 | 11111 | CASP, CASPA, CASPAL, CASPL — 32-bit CASP | FEAT_LSE |
| 00 | 0 | 0 | 1 | 1 | 11111 | CASP, CASPA, CASPAL, CASPL — 32-bit CASPL | FEAT_LSE |
| 00 | 0 | 1 | 0 | 0 | LDXRB | - | |
| 00 | 0 | 1 | 0 | 1 | LDAXRB | - | |
| 00 | 0 | 1 | 1 | 0 | 11111 | CASP, CASPA, CASPAL, CASPL — 32-bit CASPA | FEAT_LSE |
| 00 | 0 | 1 | 1 | 1 | 11111 | CASP, CASPA, CASPAL, CASPL — 32-bit CASPAL | FEAT_LSE |
| 00 | 1 | 0 | 0 | 0 | STLLRB | FEAT_LOR | |
| 00 | 1 | 0 | 0 | 1 | STLRB | - | |
| 00 | 1 | 0 | 1 | 0 | 11111 | CASB, CASAB, CASALB, CASLB — CASB | FEAT_LSE |
| 00 | 1 | 0 | 1 | 1 | 11111 | CASB, CASAB, CASALB, CASLB — CASLB | FEAT_LSE |
| 00 | 1 | 1 | 0 | 0 | LDLARB | FEAT_LOR | |
| 00 | 1 | 1 | 0 | 1 | LDARB | - | |
| 00 | 1 | 1 | 1 | 0 | 11111 | CASB, CASAB, CASALB, CASLB — CASAB | FEAT_LSE |
| 00 | 1 | 1 | 1 | 1 | 11111 | CASB, CASAB, CASALB, CASLB — CASALB | FEAT_LSE |
| 01 | 0 | 0 | 0 | 0 | STXRH | - | |
| 01 | 0 | 0 | 0 | 1 | STLXRH | - | |
| 01 | 0 | 0 | 1 | 0 | 11111 | CASP, CASPA, CASPAL, CASPL — 64-bit CASP | FEAT_LSE |
| 01 | 0 | 0 | 1 | 1 | 11111 | CASP, CASPA, CASPAL, CASPL — 64-bit CASPL | FEAT_LSE |
| 01 | 0 | 1 | 0 | 0 | LDXRH | - | |
| 01 | 0 | 1 | 0 | 1 | LDAXRH | - | |
| 01 | 0 | 1 | 1 | 0 | 11111 | CASP, CASPA, CASPAL, CASPL — 64-bit CASPA | FEAT_LSE |
| 01 | 0 | 1 | 1 | 1 | 11111 | CASP, CASPA, CASPAL, CASPL — 64-bit CASPAL | FEAT_LSE |
| 01 | 1 | 0 | 0 | 0 | STLLRH | FEAT_LOR | |
| 01 | 1 | 0 | 0 | 1 | STLRH | - | |
| 01 | 1 | 0 | 1 | 0 | 11111 | CASH, CASAH, CASALH, CASLH — CASH | FEAT_LSE |
| 01 | 1 | 0 | 1 | 1 | 11111 | CASH, CASAH, CASALH, CASLH — CASLH | FEAT_LSE |
| 01 | 1 | 1 | 0 | 0 | LDLARH | FEAT_LOR | |
| 01 | 1 | 1 | 0 | 1 | LDARH | - | |
| 01 | 1 | 1 | 1 | 0 | 11111 | CASH, CASAH, CASALH, CASLH — CASAH | FEAT_LSE |
| 01 | 1 | 1 | 1 | 1 | 11111 | CASH, CASAH, CASALH, CASLH — CASALH | FEAT_LSE |
| 10 | 0 | 0 | 0 | 0 | STXR — 32-bit | - | |
| 10 | 0 | 0 | 0 | 1 | STLXR — 32-bit | - | |
| 10 | 0 | 0 | 1 | 0 | STXP — 32-bit | - | |
| 10 | 0 | 0 | 1 | 1 | STLXP — 32-bit | - | |
| 10 | 0 | 1 | 0 | 0 | LDXR — 32-bit | - | |
| 10 | 0 | 1 | 0 | 1 | LDAXR — 32-bit | - | |
| 10 | 0 | 1 | 1 | 0 | LDXP — 32-bit | - | |
| 10 | 0 | 1 | 1 | 1 | LDAXP — 32-bit | - | |
| 10 | 1 | 0 | 0 | 0 | STLLR — 32-bit | FEAT_LOR | |
| 10 | 1 | 0 | 0 | 1 | STLR — 32-bit | - | |
| 10 | 1 | 0 | 1 | 0 | 11111 | CAS, CASA, CASAL, CASL — 32-bit CAS | FEAT_LSE |
| 10 | 1 | 0 | 1 | 1 | 11111 | CAS, CASA, CASAL, CASL — 32-bit CASL | FEAT_LSE |
| 10 | 1 | 1 | 0 | 0 | LDLAR — 32-bit | FEAT_LOR | |
| 10 | 1 | 1 | 0 | 1 | LDAR — 32-bit | - | |
| 10 | 1 | 1 | 1 | 0 | 11111 | CAS, CASA, CASAL, CASL — 32-bit CASA | FEAT_LSE |
| 10 | 1 | 1 | 1 | 1 | 11111 | CAS, CASA, CASAL, CASL — 32-bit CASAL | FEAT_LSE |
| 11 | 0 | 0 | 0 | 0 | STXR — 64-bit | - | |
| 11 | 0 | 0 | 0 | 1 | STLXR — 64-bit | - | |
| 11 | 0 | 0 | 1 | 0 | STXP — 64-bit | - | |
| 11 | 0 | 0 | 1 | 1 | STLXP — 64-bit | - | |
| 11 | 0 | 1 | 0 | 0 | LDXR — 64-bit | - | |
| 11 | 0 | 1 | 0 | 1 | LDAXR — 64-bit | - | |
| 11 | 0 | 1 | 1 | 0 | LDXP — 64-bit | - | |
| 11 | 0 | 1 | 1 | 1 | LDAXP — 64-bit | - | |
| 11 | 1 | 0 | 0 | 0 | STLLR — 64-bit | FEAT_LOR | |
| 11 | 1 | 0 | 0 | 1 | STLR — 64-bit | - | |
| 11 | 1 | 0 | 1 | 0 | 11111 | CAS, CASA, CASAL, CASL — 64-bit CAS | FEAT_LSE |
| 11 | 1 | 0 | 1 | 1 | 11111 | CAS, CASA, CASAL, CASL — 64-bit CASL | FEAT_LSE |
| 11 | 1 | 1 | 0 | 0 | LDLAR — 64-bit | FEAT_LOR | |
| 11 | 1 | 1 | 0 | 1 | LDAR — 64-bit | - | |
| 11 | 1 | 1 | 1 | 0 | 11111 | CAS, CASA, CASAL, CASL — 64-bit CASA | FEAT_LSE |
| 11 | 1 | 1 | 1 | 1 | 11111 | CAS, CASA, CASAL, CASL — 64-bit CASAL | FEAT_LSE |
These instructions are under Loads and Stores.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| opc | 0 | 1 | 1 | V | 0 | 0 | imm19 | Rt | |||||||||||||||||||||||
| Decode fields | Instruction Details | |
|---|---|---|
| opc | V | |
| 00 | 0 | LDR (literal) — 32-bit |
| 00 | 1 | LDR (literal, SIMD&FP) — 32-bit |
| 01 | 0 | LDR (literal) — 64-bit |
| 01 | 1 | LDR (literal, SIMD&FP) — 64-bit |
| 10 | 0 | LDRSW (literal) |
| 10 | 1 | LDR (literal, SIMD&FP) — 128-bit |
| 11 | 0 | PRFM (literal) |
| 11 | 1 | UNALLOCATED |
These instructions are under Loads and Stores.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| opc | 1 | 0 | 1 | V | 0 | 0 | 0 | L | imm7 | Rt2 | Rn | Rt | |||||||||||||||||||
| Decode fields | Instruction Details | ||
|---|---|---|---|
| opc | V | L | |
| 00 | 0 | 0 | STNP — 32-bit |
| 00 | 0 | 1 | LDNP — 32-bit |
| 00 | 1 | 0 | STNP (SIMD&FP) — 32-bit |
| 00 | 1 | 1 | LDNP (SIMD&FP) — 32-bit |
| 01 | 0 | UNALLOCATED | |
| 01 | 1 | 0 | STNP (SIMD&FP) — 64-bit |
| 01 | 1 | 1 | LDNP (SIMD&FP) — 64-bit |
| 10 | 0 | 0 | STNP — 64-bit |
| 10 | 0 | 1 | LDNP — 64-bit |
| 10 | 1 | 0 | STNP (SIMD&FP) — 128-bit |
| 10 | 1 | 1 | LDNP (SIMD&FP) — 128-bit |
| 11 | UNALLOCATED | ||
These instructions are under Loads and Stores.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| opc | 1 | 0 | 1 | V | 0 | 0 | 1 | L | imm7 | Rt2 | Rn | Rt | |||||||||||||||||||
| Decode fields | Instruction Details | ||
|---|---|---|---|
| opc | V | L | |
| 00 | 0 | 0 | STP — 32-bit |
| 00 | 0 | 1 | LDP — 32-bit |
| 00 | 1 | 0 | STP (SIMD&FP) — 32-bit |
| 00 | 1 | 1 | LDP (SIMD&FP) — 32-bit |
| 01 | 0 | 1 | LDPSW |
| 01 | 1 | 0 | STP (SIMD&FP) — 64-bit |
| 01 | 1 | 1 | LDP (SIMD&FP) — 64-bit |
| 10 | 0 | 0 | STP — 64-bit |
| 10 | 0 | 1 | LDP — 64-bit |
| 10 | 1 | 0 | STP (SIMD&FP) — 128-bit |
| 10 | 1 | 1 | LDP (SIMD&FP) — 128-bit |
| 11 | UNALLOCATED | ||
These instructions are under Loads and Stores.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| opc | 1 | 0 | 1 | V | 0 | 1 | 0 | L | imm7 | Rt2 | Rn | Rt | |||||||||||||||||||
| Decode fields | Instruction Details | ||
|---|---|---|---|
| opc | V | L | |
| 00 | 0 | 0 | STP — 32-bit |
| 00 | 0 | 1 | LDP — 32-bit |
| 00 | 1 | 0 | STP (SIMD&FP) — 32-bit |
| 00 | 1 | 1 | LDP (SIMD&FP) — 32-bit |
| 01 | 0 | 1 | LDPSW |
| 01 | 1 | 0 | STP (SIMD&FP) — 64-bit |
| 01 | 1 | 1 | LDP (SIMD&FP) — 64-bit |
| 10 | 0 | 0 | STP — 64-bit |
| 10 | 0 | 1 | LDP — 64-bit |
| 10 | 1 | 0 | STP (SIMD&FP) — 128-bit |
| 10 | 1 | 1 | LDP (SIMD&FP) — 128-bit |
| 11 | UNALLOCATED | ||
These instructions are under Loads and Stores.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| opc | 1 | 0 | 1 | V | 0 | 1 | 1 | L | imm7 | Rt2 | Rn | Rt | |||||||||||||||||||
| Decode fields | Instruction Details | ||
|---|---|---|---|
| opc | V | L | |
| 00 | 0 | 0 | STP — 32-bit |
| 00 | 0 | 1 | LDP — 32-bit |
| 00 | 1 | 0 | STP (SIMD&FP) — 32-bit |
| 00 | 1 | 1 | LDP (SIMD&FP) — 32-bit |
| 01 | 0 | 1 | LDPSW |
| 01 | 1 | 0 | STP (SIMD&FP) — 64-bit |
| 01 | 1 | 1 | LDP (SIMD&FP) — 64-bit |
| 10 | 0 | 0 | STP — 64-bit |
| 10 | 0 | 1 | LDP — 64-bit |
| 10 | 1 | 0 | STP (SIMD&FP) — 128-bit |
| 10 | 1 | 1 | LDP (SIMD&FP) — 128-bit |
| 11 | UNALLOCATED | ||
These instructions are under Loads and Stores.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| size | 1 | 1 | 1 | V | 0 | 0 | opc | 0 | imm9 | 0 | 0 | Rn | Rt | ||||||||||||||||||
| Decode fields | Instruction Details | ||
|---|---|---|---|
| size | V | opc | |
| x1 | 1 | 1x | UNALLOCATED |
| 00 | 0 | 00 | STURB |
| 00 | 0 | 01 | LDURB |
| 00 | 0 | 10 | LDURSB — 64-bit |
| 00 | 0 | 11 | LDURSB — 32-bit |
| 00 | 1 | 00 | STUR (SIMD&FP) — 8-bit |
| 00 | 1 | 01 | LDUR (SIMD&FP) — 8-bit |
| 00 | 1 | 10 | STUR (SIMD&FP) — 128-bit |
| 00 | 1 | 11 | LDUR (SIMD&FP) — 128-bit |
| 01 | 0 | 00 | STURH |
| 01 | 0 | 01 | LDURH |
| 01 | 0 | 10 | LDURSH — 64-bit |
| 01 | 0 | 11 | LDURSH — 32-bit |
| 01 | 1 | 00 | STUR (SIMD&FP) — 16-bit |
| 01 | 1 | 01 | LDUR (SIMD&FP) — 16-bit |
| 1x | 0 | 11 | UNALLOCATED |
| 1x | 1 | 1x | UNALLOCATED |
| 10 | 0 | 00 | STUR — 32-bit |
| 10 | 0 | 01 | LDUR — 32-bit |
| 10 | 0 | 10 | LDURSW |
| 10 | 1 | 00 | STUR (SIMD&FP) — 32-bit |
| 10 | 1 | 01 | LDUR (SIMD&FP) — 32-bit |
| 11 | 0 | 00 | STUR — 64-bit |
| 11 | 0 | 01 | LDUR — 64-bit |
| 11 | 0 | 10 | PRFUM |
| 11 | 1 | 00 | STUR (SIMD&FP) — 64-bit |
| 11 | 1 | 01 | LDUR (SIMD&FP) — 64-bit |
These instructions are under Loads and Stores.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| size | 1 | 1 | 1 | V | 0 | 0 | opc | 0 | imm9 | 0 | 1 | Rn | Rt | ||||||||||||||||||
| Decode fields | Instruction Details | ||
|---|---|---|---|
| size | V | opc | |
| x1 | 1 | 1x | UNALLOCATED |
| 00 | 0 | 00 | STRB (immediate) |
| 00 | 0 | 01 | LDRB (immediate) |
| 00 | 0 | 10 | LDRSB (immediate) — 64-bit |
| 00 | 0 | 11 | LDRSB (immediate) — 32-bit |
| 00 | 1 | 00 | STR (immediate, SIMD&FP) — 8-bit |
| 00 | 1 | 01 | LDR (immediate, SIMD&FP) — 8-bit |
| 00 | 1 | 10 | STR (immediate, SIMD&FP) — 128-bit |
| 00 | 1 | 11 | LDR (immediate, SIMD&FP) — 128-bit |
| 01 | 0 | 00 | STRH (immediate) |
| 01 | 0 | 01 | LDRH (immediate) |
| 01 | 0 | 10 | LDRSH (immediate) — 64-bit |
| 01 | 0 | 11 | LDRSH (immediate) — 32-bit |
| 01 | 1 | 00 | STR (immediate, SIMD&FP) — 16-bit |
| 01 | 1 | 01 | LDR (immediate, SIMD&FP) — 16-bit |
| 1x | 0 | 11 | UNALLOCATED |
| 1x | 1 | 1x | UNALLOCATED |
| 10 | 0 | 00 | STR (immediate) — 32-bit |
| 10 | 0 | 01 | LDR (immediate) — 32-bit |
| 10 | 0 | 10 | LDRSW (immediate) |
| 10 | 1 | 00 | STR (immediate, SIMD&FP) — 32-bit |
| 10 | 1 | 01 | LDR (immediate, SIMD&FP) — 32-bit |
| 11 | 0 | 00 | STR (immediate) — 64-bit |
| 11 | 0 | 01 | LDR (immediate) — 64-bit |
| 11 | 0 | 10 | UNALLOCATED |
| 11 | 1 | 00 | STR (immediate, SIMD&FP) — 64-bit |
| 11 | 1 | 01 | LDR (immediate, SIMD&FP) — 64-bit |
These instructions are under Loads and Stores.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| size | 1 | 1 | 1 | V | 0 | 0 | opc | 0 | imm9 | 1 | 0 | Rn | Rt | ||||||||||||||||||
| Decode fields | Instruction Details | ||
|---|---|---|---|
| size | V | opc | |
| 1 | UNALLOCATED | ||
| 00 | 0 | 00 | STTRB |
| 00 | 0 | 01 | LDTRB |
| 00 | 0 | 10 | LDTRSB — 64-bit |
| 00 | 0 | 11 | LDTRSB — 32-bit |
| 01 | 0 | 00 | STTRH |
| 01 | 0 | 01 | LDTRH |
| 01 | 0 | 10 | LDTRSH — 64-bit |
| 01 | 0 | 11 | LDTRSH — 32-bit |
| 1x | 0 | 11 | UNALLOCATED |
| 10 | 0 | 00 | STTR — 32-bit |
| 10 | 0 | 01 | LDTR — 32-bit |
| 10 | 0 | 10 | LDTRSW |
| 11 | 0 | 00 | STTR — 64-bit |
| 11 | 0 | 01 | LDTR — 64-bit |
| 11 | 0 | 10 | UNALLOCATED |
These instructions are under Loads and Stores.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| size | 1 | 1 | 1 | V | 0 | 0 | opc | 0 | imm9 | 1 | 1 | Rn | Rt | ||||||||||||||||||
| Decode fields | Instruction Details | ||
|---|---|---|---|
| size | V | opc | |
| x1 | 1 | 1x | UNALLOCATED |
| 00 | 0 | 00 | STRB (immediate) |
| 00 | 0 | 01 | LDRB (immediate) |
| 00 | 0 | 10 | LDRSB (immediate) — 64-bit |
| 00 | 0 | 11 | LDRSB (immediate) — 32-bit |
| 00 | 1 | 00 | STR (immediate, SIMD&FP) — 8-bit |
| 00 | 1 | 01 | LDR (immediate, SIMD&FP) — 8-bit |
| 00 | 1 | 10 | STR (immediate, SIMD&FP) — 128-bit |
| 00 | 1 | 11 | LDR (immediate, SIMD&FP) — 128-bit |
| 01 | 0 | 00 | STRH (immediate) |
| 01 | 0 | 01 | LDRH (immediate) |
| 01 | 0 | 10 | LDRSH (immediate) — 64-bit |
| 01 | 0 | 11 | LDRSH (immediate) — 32-bit |
| 01 | 1 | 00 | STR (immediate, SIMD&FP) — 16-bit |
| 01 | 1 | 01 | LDR (immediate, SIMD&FP) — 16-bit |
| 1x | 0 | 11 | UNALLOCATED |
| 1x | 1 | 1x | UNALLOCATED |
| 10 | 0 | 00 | STR (immediate) — 32-bit |
| 10 | 0 | 01 | LDR (immediate) — 32-bit |
| 10 | 0 | 10 | LDRSW (immediate) |
| 10 | 1 | 00 | STR (immediate, SIMD&FP) — 32-bit |
| 10 | 1 | 01 | LDR (immediate, SIMD&FP) — 32-bit |
| 11 | 0 | 00 | STR (immediate) — 64-bit |
| 11 | 0 | 01 | LDR (immediate) — 64-bit |
| 11 | 0 | 10 | UNALLOCATED |
| 11 | 1 | 00 | STR (immediate, SIMD&FP) — 64-bit |
| 11 | 1 | 01 | LDR (immediate, SIMD&FP) — 64-bit |
These instructions are under Loads and Stores.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| size | 1 | 1 | 1 | V | 0 | 0 | A | R | 1 | Rs | o3 | opc | 0 | 0 | Rn | Rt | |||||||||||||||
These instructions are under Loads and Stores.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| size | 1 | 1 | 1 | V | 0 | 0 | opc | 1 | Rm | option | S | 1 | 0 | Rn | Rt | ||||||||||||||||
These instructions are under Loads and Stores.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| size | 1 | 1 | 1 | V | 0 | 0 | M | S | 1 | imm9 | W | 1 | Rn | Rt | |||||||||||||||||
| Decode fields | Instruction Details | |
|---|---|---|
| size | V | |
| != 11 | UNALLOCATED | |
| 11 | 1 | UNALLOCATED |
These instructions are under Loads and Stores.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| size | 1 | 1 | 1 | V | 0 | 1 | opc | imm12 | Rn | Rt | |||||||||||||||||||||
| Decode fields | Instruction Details | ||
|---|---|---|---|
| size | V | opc | |
| x1 | 1 | 1x | UNALLOCATED |
| 00 | 0 | 00 | STRB (immediate) |
| 00 | 0 | 01 | LDRB (immediate) |
| 00 | 0 | 10 | LDRSB (immediate) — 64-bit |
| 00 | 0 | 11 | LDRSB (immediate) — 32-bit |
| 00 | 1 | 00 | STR (immediate, SIMD&FP) — 8-bit |
| 00 | 1 | 01 | LDR (immediate, SIMD&FP) — 8-bit |
| 00 | 1 | 10 | STR (immediate, SIMD&FP) — 128-bit |
| 00 | 1 | 11 | LDR (immediate, SIMD&FP) — 128-bit |
| 01 | 0 | 00 | STRH (immediate) |
| 01 | 0 | 01 | LDRH (immediate) |
| 01 | 0 | 10 | LDRSH (immediate) — 64-bit |
| 01 | 0 | 11 | LDRSH (immediate) — 32-bit |
| 01 | 1 | 00 | STR (immediate, SIMD&FP) — 16-bit |
| 01 | 1 | 01 | LDR (immediate, SIMD&FP) — 16-bit |
| 1x | 0 | 11 | UNALLOCATED |
| 1x | 1 | 1x | UNALLOCATED |
| 10 | 0 | 00 | STR (immediate) — 32-bit |
| 10 | 0 | 01 | LDR (immediate) — 32-bit |
| 10 | 0 | 10 | LDRSW (immediate) |
| 10 | 1 | 00 | STR (immediate, SIMD&FP) — 32-bit |
| 10 | 1 | 01 | LDR (immediate, SIMD&FP) — 32-bit |
| 11 | 0 | 00 | STR (immediate) — 64-bit |
| 11 | 0 | 01 | LDR (immediate) — 64-bit |
| 11 | 0 | 10 | PRFM (immediate) |
| 11 | 1 | 00 | STR (immediate, SIMD&FP) — 64-bit |
| 11 | 1 | 01 | LDR (immediate, SIMD&FP) — 64-bit |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| op0 | op1 | 101 | op2 | op3 | |||||||||||||||||||||||||||
| Decode fields | Instruction details | |||
|---|---|---|---|---|
| op0 | op1 | op2 | op3 | |
| 0 | 1 | 0110 | Data-processing (2 source) | |
| 1 | 1 | 0110 | Data-processing (1 source) | |
| 0 | 0xxx | Logical (shifted register) | ||
| 0 | 1xx0 | Add/subtract (shifted register) | ||
| 0 | 1xx1 | Add/subtract (extended register) | ||
| 1 | 0000 | 000000 | Add/subtract (with carry) | |
| 1 | 0000 | 000011 | UNALLOCATED | |
| 1 | 0000 | 0001xx | UNALLOCATED | |
| 1 | 0000 | 001xxx | UNALLOCATED | |
| 1 | 0000 | x00001 | Rotate right into flags | |
| 1 | 0000 | xx0010 | Evaluate into flags | |
| 1 | 0010 | xxxx0x | Conditional compare (register) | |
| 1 | 0010 | xxxx1x | Conditional compare (immediate) | |
| 1 | 0100 | Conditional select | ||
| 1 | 0xx1 | UNALLOCATED | ||
| 1 | 1xxx | Data-processing (3 source) | ||
These instructions are under Data Processing -- Register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | 0 | S | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | Rm | opcode | Rn | Rd | |||||||||||||||||
| Decode fields | Instruction Details | ||
|---|---|---|---|
| sf | S | opcode | |
| 000001 | UNALLOCATED | ||
| 011xxx | UNALLOCATED | ||
| 1xxxxx | UNALLOCATED | ||
| 0 | 00011x | UNALLOCATED | |
| 0 | 001101 | UNALLOCATED | |
| 0 | 00111x | UNALLOCATED | |
| 1 | 00001x | UNALLOCATED | |
| 1 | 0001xx | UNALLOCATED | |
| 1 | 001xxx | UNALLOCATED | |
| 1 | 01xxxx | UNALLOCATED | |
| 0 | 000000 | UNALLOCATED | |
| 0 | 0 | 000010 | UDIV — 32-bit |
| 0 | 0 | 000011 | SDIV — 32-bit |
| 0 | 0 | 00010x | UNALLOCATED |
| 0 | 0 | 001000 | LSLV — 32-bit |
| 0 | 0 | 001001 | LSRV — 32-bit |
| 0 | 0 | 001010 | ASRV — 32-bit |
| 0 | 0 | 001011 | RORV — 32-bit |
| 0 | 0 | 001100 | UNALLOCATED |
| 0 | 0 | 010x11 | UNALLOCATED |
| 0 | 0 | 010000 | CRC32B, CRC32H, CRC32W, CRC32X — CRC32B |
| 0 | 0 | 010001 | CRC32B, CRC32H, CRC32W, CRC32X — CRC32H |
| 0 | 0 | 010010 | CRC32B, CRC32H, CRC32W, CRC32X — CRC32W |
| 0 | 0 | 010100 | CRC32CB, CRC32CH, CRC32CW, CRC32CX — CRC32CB |
| 0 | 0 | 010101 | CRC32CB, CRC32CH, CRC32CW, CRC32CX — CRC32CH |
| 0 | 0 | 010110 | CRC32CB, CRC32CH, CRC32CW, CRC32CX — CRC32CW |
| 1 | 0 | 000010 | UDIV — 64-bit |
| 1 | 0 | 000011 | SDIV — 64-bit |
| 1 | 0 | 001000 | LSLV — 64-bit |
| 1 | 0 | 001001 | LSRV — 64-bit |
| 1 | 0 | 001010 | ASRV — 64-bit |
| 1 | 0 | 001011 | RORV — 64-bit |
| 1 | 0 | 010xx0 | UNALLOCATED |
| 1 | 0 | 010x0x | UNALLOCATED |
| 1 | 0 | 010011 | CRC32B, CRC32H, CRC32W, CRC32X — CRC32X |
| 1 | 0 | 010111 | CRC32CB, CRC32CH, CRC32CW, CRC32CX — CRC32CX |
These instructions are under Data Processing -- Register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | 1 | S | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | opcode2 | opcode | Rn | Rd | |||||||||||||||||
| Decode fields | Instruction Details | |||
|---|---|---|---|---|
| sf | S | opcode2 | opcode | |
| 1xxxxx | UNALLOCATED | |||
| xxx1x | UNALLOCATED | |||
| xx1xx | UNALLOCATED | |||
| x1xxx | UNALLOCATED | |||
| 1xxxx | UNALLOCATED | |||
| 0 | 00000 | 00011x | UNALLOCATED | |
| 0 | 00000 | 001xxx | UNALLOCATED | |
| 0 | 00000 | 01xxxx | UNALLOCATED | |
| 1 | UNALLOCATED | |||
| 0 | 00001 | UNALLOCATED | ||
| 0 | 0 | 00000 | 000000 | RBIT — 32-bit |
| 0 | 0 | 00000 | 000001 | REV16 — 32-bit |
| 0 | 0 | 00000 | 000010 | REV — 32-bit |
| 0 | 0 | 00000 | 000011 | UNALLOCATED |
| 0 | 0 | 00000 | 000100 | CLZ — 32-bit |
| 0 | 0 | 00000 | 000101 | CLS — 32-bit |
| 1 | 0 | 00000 | 000000 | RBIT — 64-bit |
| 1 | 0 | 00000 | 000001 | REV16 — 64-bit |
| 1 | 0 | 00000 | 000010 | REV32 |
| 1 | 0 | 00000 | 000011 | REV — 64-bit |
| 1 | 0 | 00000 | 000100 | CLZ — 64-bit |
| 1 | 0 | 00000 | 000101 | CLS — 64-bit |
| 1 | 0 | 00001 | 01001x | UNALLOCATED |
| 1 | 0 | 00001 | 0101xx | UNALLOCATED |
| 1 | 0 | 00001 | 011xxx | UNALLOCATED |
These instructions are under Data Processing -- Register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | opc | 0 | 1 | 0 | 1 | 0 | shift | N | Rm | imm6 | Rn | Rd | |||||||||||||||||||
| Decode fields | Instruction Details | |||
|---|---|---|---|---|
| sf | opc | N | imm6 | |
| 0 | 1xxxxx | UNALLOCATED | ||
| 0 | 00 | 0 | AND (shifted register) — 32-bit | |
| 0 | 00 | 1 | BIC (shifted register) — 32-bit | |
| 0 | 01 | 0 | ORR (shifted register) — 32-bit | |
| 0 | 01 | 1 | ORN (shifted register) — 32-bit | |
| 0 | 10 | 0 | EOR (shifted register) — 32-bit | |
| 0 | 10 | 1 | EON (shifted register) — 32-bit | |
| 0 | 11 | 0 | ANDS (shifted register) — 32-bit | |
| 0 | 11 | 1 | BICS (shifted register) — 32-bit | |
| 1 | 00 | 0 | AND (shifted register) — 64-bit | |
| 1 | 00 | 1 | BIC (shifted register) — 64-bit | |
| 1 | 01 | 0 | ORR (shifted register) — 64-bit | |
| 1 | 01 | 1 | ORN (shifted register) — 64-bit | |
| 1 | 10 | 0 | EOR (shifted register) — 64-bit | |
| 1 | 10 | 1 | EON (shifted register) — 64-bit | |
| 1 | 11 | 0 | ANDS (shifted register) — 64-bit | |
| 1 | 11 | 1 | BICS (shifted register) — 64-bit | |
These instructions are under Data Processing -- Register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | op | S | 0 | 1 | 0 | 1 | 1 | shift | 0 | Rm | imm6 | Rn | Rd | ||||||||||||||||||
| Decode fields | Instruction Details | ||||
|---|---|---|---|---|---|
| sf | op | S | shift | imm6 | |
| 11 | UNALLOCATED | ||||
| 0 | 1xxxxx | UNALLOCATED | |||
| 0 | 0 | 0 | ADD (shifted register) — 32-bit | ||
| 0 | 0 | 1 | ADDS (shifted register) — 32-bit | ||
| 0 | 1 | 0 | SUB (shifted register) — 32-bit | ||
| 0 | 1 | 1 | SUBS (shifted register) — 32-bit | ||
| 1 | 0 | 0 | ADD (shifted register) — 64-bit | ||
| 1 | 0 | 1 | ADDS (shifted register) — 64-bit | ||
| 1 | 1 | 0 | SUB (shifted register) — 64-bit | ||
| 1 | 1 | 1 | SUBS (shifted register) — 64-bit | ||
These instructions are under Data Processing -- Register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | op | S | 0 | 1 | 0 | 1 | 1 | opt | 1 | Rm | option | imm3 | Rn | Rd | |||||||||||||||||
| Decode fields | Instruction Details | ||||
|---|---|---|---|---|---|
| sf | op | S | opt | imm3 | |
| 1x1 | UNALLOCATED | ||||
| 11x | UNALLOCATED | ||||
| x1 | UNALLOCATED | ||||
| 1x | UNALLOCATED | ||||
| 0 | 0 | 0 | 00 | ADD (extended register) — 32-bit | |
| 0 | 0 | 1 | 00 | ADDS (extended register) — 32-bit | |
| 0 | 1 | 0 | 00 | SUB (extended register) — 32-bit | |
| 0 | 1 | 1 | 00 | SUBS (extended register) — 32-bit | |
| 1 | 0 | 0 | 00 | ADD (extended register) — 64-bit | |
| 1 | 0 | 1 | 00 | ADDS (extended register) — 64-bit | |
| 1 | 1 | 0 | 00 | SUB (extended register) — 64-bit | |
| 1 | 1 | 1 | 00 | SUBS (extended register) — 64-bit | |
These instructions are under Data Processing -- Register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | op | S | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | Rm | 0 | 0 | 0 | 0 | 0 | 0 | Rn | Rd | ||||||||||||
These instructions are under Data Processing -- Register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | op | S | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | imm6 | 0 | 0 | 0 | 0 | 1 | Rn | o2 | mask | ||||||||||||
| Decode fields | Instruction Details | |||
|---|---|---|---|---|
| sf | op | S | o2 | |
| 0 | UNALLOCATED | |||
| 1 | 0 | 0 | UNALLOCATED | |
| 1 | 0 | 1 | 1 | UNALLOCATED |
| 1 | 1 | UNALLOCATED | ||
These instructions are under Data Processing -- Register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | op | S | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | opcode2 | sz | 0 | 0 | 1 | 0 | Rn | o3 | mask | ||||||||||||
| Decode fields | Instruction Details | |||||
|---|---|---|---|---|---|---|
| sf | op | S | opcode2 | o3 | mask | |
| 0 | 0 | 0 | UNALLOCATED | |||
| 0 | 0 | 1 | != 000000 | UNALLOCATED | ||
| 0 | 0 | 1 | 000000 | 0 | != 1101 | UNALLOCATED |
| 0 | 0 | 1 | 000000 | 1 | UNALLOCATED | |
| 0 | 1 | UNALLOCATED | ||||
| 1 | UNALLOCATED | |||||
These instructions are under Data Processing -- Register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | op | S | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | Rm | cond | 0 | o2 | Rn | o3 | nzcv | ||||||||||||||
| Decode fields | Instruction Details | ||||
|---|---|---|---|---|---|
| sf | op | S | o2 | o3 | |
| 1 | UNALLOCATED | ||||
| 1 | UNALLOCATED | ||||
| 0 | UNALLOCATED | ||||
| 0 | 0 | 1 | 0 | 0 | CCMN (register) — 32-bit |
| 0 | 1 | 1 | 0 | 0 | CCMP (register) — 32-bit |
| 1 | 0 | 1 | 0 | 0 | CCMN (register) — 64-bit |
| 1 | 1 | 1 | 0 | 0 | CCMP (register) — 64-bit |
These instructions are under Data Processing -- Register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | op | S | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | imm5 | cond | 1 | o2 | Rn | o3 | nzcv | ||||||||||||||
| Decode fields | Instruction Details | ||||
|---|---|---|---|---|---|
| sf | op | S | o2 | o3 | |
| 1 | UNALLOCATED | ||||
| 1 | UNALLOCATED | ||||
| 0 | UNALLOCATED | ||||
| 0 | 0 | 1 | 0 | 0 | CCMN (immediate) — 32-bit |
| 0 | 1 | 1 | 0 | 0 | CCMP (immediate) — 32-bit |
| 1 | 0 | 1 | 0 | 0 | CCMN (immediate) — 64-bit |
| 1 | 1 | 1 | 0 | 0 | CCMP (immediate) — 64-bit |
These instructions are under Data Processing -- Register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | op | S | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | Rm | cond | op2 | Rn | Rd | ||||||||||||||||
These instructions are under Data Processing -- Register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | op54 | 1 | 1 | 0 | 1 | 1 | op31 | Rm | o0 | Ra | Rn | Rd | |||||||||||||||||||
| Decode fields | Instruction Details | |||
|---|---|---|---|---|
| sf | op54 | op31 | o0 | |
| 00 | 010 | 1 | UNALLOCATED | |
| 00 | 011 | UNALLOCATED | ||
| 00 | 100 | UNALLOCATED | ||
| 00 | 110 | 1 | UNALLOCATED | |
| 00 | 111 | UNALLOCATED | ||
| 01 | UNALLOCATED | |||
| 1x | UNALLOCATED | |||
| 0 | 00 | 000 | 0 | MADD — 32-bit |
| 0 | 00 | 000 | 1 | MSUB — 32-bit |
| 0 | 00 | 001 | 0 | UNALLOCATED |
| 0 | 00 | 001 | 1 | UNALLOCATED |
| 0 | 00 | 010 | 0 | UNALLOCATED |
| 0 | 00 | 101 | 0 | UNALLOCATED |
| 0 | 00 | 101 | 1 | UNALLOCATED |
| 0 | 00 | 110 | 0 | UNALLOCATED |
| 1 | 00 | 000 | 0 | MADD — 64-bit |
| 1 | 00 | 000 | 1 | MSUB — 64-bit |
| 1 | 00 | 001 | 0 | SMADDL |
| 1 | 00 | 001 | 1 | SMSUBL |
| 1 | 00 | 010 | 0 | SMULH |
| 1 | 00 | 101 | 0 | UMADDL |
| 1 | 00 | 101 | 1 | UMSUBL |
| 1 | 00 | 110 | 0 | UMULH |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| op0 | 111 | op1 | op2 | op3 | |||||||||||||||||||||||||||
| Decode fields | Instruction details | Architecture version | |||
|---|---|---|---|---|---|
| op0 | op1 | op2 | op3 | ||
| 0000 | 0x | x101 | 00xxxxx10 | UNALLOCATED | - |
| 0010 | 0x | x101 | 00xxxxx10 | UNALLOCATED | - |
| 0100 | 0x | x101 | 00xxxxx10 | Cryptographic AES | - |
| 0101 | 0x | x0xx | xxx0xxx00 | Cryptographic three-register SHA | - |
| 0101 | 0x | x0xx | xxx0xxx10 | UNALLOCATED | - |
| 0101 | 0x | x101 | 00xxxxx10 | Cryptographic two-register SHA | - |
| 0110 | 0x | x101 | 00xxxxx10 | UNALLOCATED | - |
| 0111 | 0x | x0xx | xxx0xxxx0 | UNALLOCATED | - |
| 0111 | 0x | x101 | 00xxxxx10 | UNALLOCATED | - |
| 01x1 | 00 | 00xx | xxx0xxxx1 | Advanced SIMD scalar copy | - |
| 01x1 | 01 | 00xx | xxx0xxxx1 | UNALLOCATED | - |
| 01x1 | 0x | 0111 | 00xxxxx10 | UNALLOCATED | - |
| 01x1 | 0x | 10xx | xxx00xxx1 | Advanced SIMD scalar three same FP16 | - |
| 01x1 | 0x | 10xx | xxx01xxx1 | UNALLOCATED | - |
| 01x1 | 0x | 1111 | 00xxxxx10 | Advanced SIMD scalar two-register miscellaneous FP16 | - |
| 01x1 | 0x | x0xx | xxx1xxxx0 | UNALLOCATED | - |
| 01x1 | 0x | x0xx | xxx1xxxx1 | Advanced SIMD scalar three same extra | - |
| 01x1 | 0x | x100 | 00xxxxx10 | Advanced SIMD scalar two-register miscellaneous | - |
| 01x1 | 0x | x110 | 00xxxxx10 | Advanced SIMD scalar pairwise | - |
| 01x1 | 0x | x1xx | 1xxxxxx10 | UNALLOCATED | - |
| 01x1 | 0x | x1xx | x1xxxxx10 | UNALLOCATED | - |
| 01x1 | 0x | x1xx | xxxxxxx00 | Advanced SIMD scalar three different | - |
| 01x1 | 0x | x1xx | xxxxxxxx1 | Advanced SIMD scalar three same | - |
| 01x1 | 10 | xxxxxxxx1 | Advanced SIMD scalar shift by immediate | - | |
| 01x1 | 11 | xxxxxxxx1 | UNALLOCATED | - | |
| 01x1 | 1x | xxxxxxxx0 | Advanced SIMD scalar x indexed element | - | |
| 0x00 | 0x | x0xx | xxx0xxx00 | Advanced SIMD table lookup | - |
| 0x00 | 0x | x0xx | xxx0xxx10 | Advanced SIMD permute | - |
| 0x10 | 0x | x0xx | xxx0xxxx0 | Advanced SIMD extract | - |
| 0xx0 | 00 | 00xx | xxx0xxxx1 | Advanced SIMD copy | - |
| 0xx0 | 01 | 00xx | xxx0xxxx1 | UNALLOCATED | - |
| 0xx0 | 0x | 0111 | 00xxxxx10 | UNALLOCATED | - |
| 0xx0 | 0x | 10xx | xxx00xxx1 | Advanced SIMD three same (FP16) | - |
| 0xx0 | 0x | 10xx | xxx01xxx1 | UNALLOCATED | - |
| 0xx0 | 0x | 1111 | 00xxxxx10 | Advanced SIMD two-register miscellaneous (FP16) | - |
| 0xx0 | 0x | x0xx | xxx1xxxx0 | UNALLOCATED | - |
| 0xx0 | 0x | x0xx | xxx1xxxx1 | Advanced SIMD three-register extension | - |
| 0xx0 | 0x | x100 | 00xxxxx10 | Advanced SIMD two-register miscellaneous | - |
| 0xx0 | 0x | x110 | 00xxxxx10 | Advanced SIMD across lanes | - |
| 0xx0 | 0x | x1xx | 1xxxxxx10 | UNALLOCATED | - |
| 0xx0 | 0x | x1xx | x1xxxxx10 | UNALLOCATED | - |
| 0xx0 | 0x | x1xx | xxxxxxx00 | Advanced SIMD three different | - |
| 0xx0 | 0x | x1xx | xxxxxxxx1 | Advanced SIMD three same | - |
| 0xx0 | 10 | 0000 | xxxxxxxx1 | Advanced SIMD modified immediate | - |
| 0xx0 | 10 | != 0000 | xxxxxxxx1 | Advanced SIMD shift by immediate | - |
| 0xx0 | 11 | xxxxxxxx1 | UNALLOCATED | - | |
| 0xx0 | 1x | xxxxxxxx0 | Advanced SIMD vector x indexed element | - | |
| 1100 | 00 | 10xx | xxx10xxxx | Cryptographic three-register, imm2 | - |
| 1100 | 00 | 11xx | xxx1x00xx | Cryptographic three-register SHA 512 | - |
| 1100 | 00 | xxx0xxxxx | Cryptographic four-register | - | |
| 1100 | 01 | 00xx | XAR | FEAT_SHA3 | |
| 1100 | 01 | 1000 | 0001000xx | Cryptographic two-register SHA 512 | - |
| 11x1 | UNALLOCATED | - | |||
| 1xx0 | 1x | UNALLOCATED | - | ||
| x0x1 | 0x | x0xx | Conversion between floating-point and fixed-point | - | |
| x0x1 | 0x | x1xx | xxx000000 | Conversion between floating-point and integer | - |
| x0x1 | 0x | x1xx | xxx100000 | UNALLOCATED | - |
| x0x1 | 0x | x1xx | xxxx10000 | Floating-point data-processing (1 source) | - |
| x0x1 | 0x | x1xx | xxxxx1000 | Floating-point compare | - |
| x0x1 | 0x | x1xx | xxxxxx100 | Floating-point immediate | - |
| x0x1 | 0x | x1xx | xxxxxxx01 | Floating-point conditional compare | - |
| x0x1 | 0x | x1xx | xxxxxxx10 | Floating-point data-processing (2 source) | - |
| x0x1 | 0x | x1xx | xxxxxxx11 | Floating-point conditional select | - |
| x0x1 | 1x | Floating-point data-processing (3 source) | - | ||
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | size | 1 | 0 | 1 | 0 | 0 | opcode | 1 | 0 | Rn | Rd | |||||||||||||
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | size | 0 | Rm | 0 | opcode | 0 | 0 | Rn | Rd | |||||||||||||||
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | size | 1 | 0 | 1 | 0 | 0 | opcode | 1 | 0 | Rn | Rd | |||||||||||||
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | op | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | |||||||||||||||
| Decode fields | Instruction Details | |
|---|---|---|
| op | imm4 | |
| 0 | xxx1 | UNALLOCATED |
| 0 | xx1x | UNALLOCATED |
| 0 | x1xx | UNALLOCATED |
| 0 | 0000 | DUP (element) |
| 0 | 1xxx | UNALLOCATED |
| 1 | UNALLOCATED | |
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | U | 1 | 1 | 1 | 1 | 0 | a | 1 | 0 | Rm | 0 | 0 | opcode | 1 | Rn | Rd | ||||||||||||||
| Decode fields | Instruction Details | Feature | ||
|---|---|---|---|---|
| U | a | opcode | ||
| 110 | UNALLOCATED | - | ||
| 1 | 011 | UNALLOCATED | - | |
| 0 | 0 | 011 | FMULX | FEAT_FP16 |
| 0 | 0 | 100 | FCMEQ (register) | FEAT_FP16 |
| 0 | 0 | 101 | UNALLOCATED | - |
| 0 | 0 | 111 | FRECPS | FEAT_FP16 |
| 0 | 1 | 100 | UNALLOCATED | - |
| 0 | 1 | 101 | UNALLOCATED | - |
| 0 | 1 | 111 | FRSQRTS | FEAT_FP16 |
| 1 | 0 | 011 | UNALLOCATED | - |
| 1 | 0 | 100 | FCMGE (register) | FEAT_FP16 |
| 1 | 0 | 101 | FACGE | FEAT_FP16 |
| 1 | 0 | 111 | UNALLOCATED | - |
| 1 | 1 | 010 | FABD | FEAT_FP16 |
| 1 | 1 | 100 | FCMGT (register) | FEAT_FP16 |
| 1 | 1 | 101 | FACGT | FEAT_FP16 |
| 1 | 1 | 111 | UNALLOCATED | - |
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | U | 1 | 1 | 1 | 1 | 0 | a | 1 | 1 | 1 | 1 | 0 | 0 | opcode | 1 | 0 | Rn | Rd | ||||||||||||
| Decode fields | Instruction Details | Feature | ||
|---|---|---|---|---|
| U | a | opcode | ||
| 00xxx | UNALLOCATED | - | ||
| 010xx | UNALLOCATED | - | ||
| 10xxx | UNALLOCATED | - | ||
| 1100x | UNALLOCATED | - | ||
| 11110 | UNALLOCATED | - | ||
| 0 | 011xx | UNALLOCATED | - | |
| 0 | 11111 | UNALLOCATED | - | |
| 1 | 01111 | UNALLOCATED | - | |
| 1 | 11100 | UNALLOCATED | - | |
| 0 | 0 | 11010 | FCVTNS (vector) | FEAT_FP16 |
| 0 | 0 | 11011 | FCVTMS (vector) | FEAT_FP16 |
| 0 | 0 | 11100 | FCVTAS (vector) | FEAT_FP16 |
| 0 | 0 | 11101 | SCVTF (vector, integer) | FEAT_FP16 |
| 0 | 1 | 01100 | FCMGT (zero) | FEAT_FP16 |
| 0 | 1 | 01101 | FCMEQ (zero) | FEAT_FP16 |
| 0 | 1 | 01110 | FCMLT (zero) | FEAT_FP16 |
| 0 | 1 | 11010 | FCVTPS (vector) | FEAT_FP16 |
| 0 | 1 | 11011 | FCVTZS (vector, integer) | FEAT_FP16 |
| 0 | 1 | 11101 | FRECPE | FEAT_FP16 |
| 0 | 1 | 11111 | FRECPX | FEAT_FP16 |
| 1 | 0 | 11010 | FCVTNU (vector) | FEAT_FP16 |
| 1 | 0 | 11011 | FCVTMU (vector) | FEAT_FP16 |
| 1 | 0 | 11100 | FCVTAU (vector) | FEAT_FP16 |
| 1 | 0 | 11101 | UCVTF (vector, integer) | FEAT_FP16 |
| 1 | 1 | 01100 | FCMGE (zero) | FEAT_FP16 |
| 1 | 1 | 01101 | FCMLE (zero) | FEAT_FP16 |
| 1 | 1 | 01110 | UNALLOCATED | - |
| 1 | 1 | 11010 | FCVTPU (vector) | FEAT_FP16 |
| 1 | 1 | 11011 | FCVTZU (vector, integer) | FEAT_FP16 |
| 1 | 1 | 11101 | FRSQRTE | FEAT_FP16 |
| 1 | 1 | 11111 | UNALLOCATED | - |
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | U | 1 | 1 | 1 | 1 | 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | ||||||||||||||||
| Decode fields | Instruction Details | Feature | |
|---|---|---|---|
| U | opcode | ||
| 001x | UNALLOCATED | - | |
| 01xx | UNALLOCATED | - | |
| 1xxx | UNALLOCATED | - | |
| 0 | 0000 | UNALLOCATED | - |
| 0 | 0001 | UNALLOCATED | - |
| 1 | 0000 | SQRDMLAH (vector) | FEAT_RDM |
| 1 | 0001 | SQRDMLSH (vector) | FEAT_RDM |
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | U | 1 | 1 | 1 | 1 | 0 | size | 1 | 0 | 0 | 0 | 0 | opcode | 1 | 0 | Rn | Rd | |||||||||||||
| Decode fields | Instruction Details | ||
|---|---|---|---|
| U | size | opcode | |
| 0000x | UNALLOCATED | ||
| 00010 | UNALLOCATED | ||
| 0010x | UNALLOCATED | ||
| 00110 | UNALLOCATED | ||
| 01111 | UNALLOCATED | ||
| 1000x | UNALLOCATED | ||
| 10011 | UNALLOCATED | ||
| 10101 | UNALLOCATED | ||
| 10111 | UNALLOCATED | ||
| 1100x | UNALLOCATED | ||
| 11110 | UNALLOCATED | ||
| 0x | 011xx | UNALLOCATED | |
| 0x | 11111 | UNALLOCATED | |
| 1x | 10110 | UNALLOCATED | |
| 1x | 11100 | UNALLOCATED | |
| 0 | 00011 | SUQADD | |
| 0 | 00111 | SQABS | |
| 0 | 01000 | CMGT (zero) | |
| 0 | 01001 | CMEQ (zero) | |
| 0 | 01010 | CMLT (zero) | |
| 0 | 01011 | ABS | |
| 0 | 10010 | UNALLOCATED | |
| 0 | 10100 | SQXTN, SQXTN2 | |
| 0 | 0x | 10110 | UNALLOCATED |
| 0 | 0x | 11010 | FCVTNS (vector) |
| 0 | 0x | 11011 | FCVTMS (vector) |
| 0 | 0x | 11100 | FCVTAS (vector) |
| 0 | 0x | 11101 | SCVTF (vector, integer) |
| 0 | 1x | 01100 | FCMGT (zero) |
| 0 | 1x | 01101 | FCMEQ (zero) |
| 0 | 1x | 01110 | FCMLT (zero) |
| 0 | 1x | 11010 | FCVTPS (vector) |
| 0 | 1x | 11011 | FCVTZS (vector, integer) |
| 0 | 1x | 11101 | FRECPE |
| 0 | 1x | 11111 | FRECPX |
| 1 | 00011 | USQADD | |
| 1 | 00111 | SQNEG | |
| 1 | 01000 | CMGE (zero) | |
| 1 | 01001 | CMLE (zero) | |
| 1 | 01010 | UNALLOCATED | |
| 1 | 01011 | NEG (vector) | |
| 1 | 10010 | SQXTUN, SQXTUN2 | |
| 1 | 10100 | UQXTN, UQXTN2 | |
| 1 | 0x | 10110 | FCVTXN, FCVTXN2 |
| 1 | 0x | 11010 | FCVTNU (vector) |
| 1 | 0x | 11011 | FCVTMU (vector) |
| 1 | 0x | 11100 | FCVTAU (vector) |
| 1 | 0x | 11101 | UCVTF (vector, integer) |
| 1 | 1x | 01100 | FCMGE (zero) |
| 1 | 1x | 01101 | FCMLE (zero) |
| 1 | 1x | 01110 | UNALLOCATED |
| 1 | 1x | 11010 | FCVTPU (vector) |
| 1 | 1x | 11011 | FCVTZU (vector, integer) |
| 1 | 1x | 11101 | FRSQRTE |
| 1 | 1x | 11111 | UNALLOCATED |
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | U | 1 | 1 | 1 | 1 | 0 | size | 1 | 1 | 0 | 0 | 0 | opcode | 1 | 0 | Rn | Rd | |||||||||||||
| Decode fields | Instruction Details | Feature | ||
|---|---|---|---|---|
| U | size | opcode | ||
| 00xxx | UNALLOCATED | - | ||
| 010xx | UNALLOCATED | - | ||
| 01110 | UNALLOCATED | - | ||
| 10xxx | UNALLOCATED | - | ||
| 1100x | UNALLOCATED | - | ||
| 11010 | UNALLOCATED | - | ||
| 111xx | UNALLOCATED | - | ||
| 1x | 01101 | UNALLOCATED | - | |
| 0 | 11011 | ADDP (scalar) | - | |
| 0 | 00 | 01100 | FMAXNMP (scalar) — half-precision | FEAT_FP16 |
| 0 | 00 | 01101 | FADDP (scalar) — half-precision | FEAT_FP16 |
| 0 | 00 | 01111 | FMAXP (scalar) — half-precision | FEAT_FP16 |
| 0 | 01 | 01100 | UNALLOCATED | - |
| 0 | 01 | 01101 | UNALLOCATED | - |
| 0 | 01 | 01111 | UNALLOCATED | - |
| 0 | 10 | 01100 | FMINNMP (scalar) — half-precision | FEAT_FP16 |
| 0 | 10 | 01111 | FMINP (scalar) — half-precision | FEAT_FP16 |
| 0 | 11 | 01100 | UNALLOCATED | - |
| 0 | 11 | 01111 | UNALLOCATED | - |
| 1 | 11011 | UNALLOCATED | - | |
| 1 | 0x | 01100 | FMAXNMP (scalar) — single-precision and double-precision | - |
| 1 | 0x | 01101 | FADDP (scalar) — single-precision and double-precision | - |
| 1 | 0x | 01111 | FMAXP (scalar) — single-precision and double-precision | - |
| 1 | 1x | 01100 | FMINNMP (scalar) — single-precision and double-precision | - |
| 1 | 1x | 01111 | FMINP (scalar) — single-precision and double-precision | - |
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | U | 1 | 1 | 1 | 1 | 0 | size | 1 | Rm | opcode | 0 | 0 | Rn | Rd | ||||||||||||||||
| Decode fields | Instruction Details | |
|---|---|---|
| U | opcode | |
| 00xx | UNALLOCATED | |
| 01xx | UNALLOCATED | |
| 1000 | UNALLOCATED | |
| 1010 | UNALLOCATED | |
| 1100 | UNALLOCATED | |
| 111x | UNALLOCATED | |
| 0 | 1001 | SQDMLAL, SQDMLAL2 (vector) |
| 0 | 1011 | SQDMLSL, SQDMLSL2 (vector) |
| 0 | 1101 | SQDMULL, SQDMULL2 (vector) |
| 1 | 1001 | UNALLOCATED |
| 1 | 1011 | UNALLOCATED |
| 1 | 1101 | UNALLOCATED |
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | U | 1 | 1 | 1 | 1 | 0 | size | 1 | Rm | opcode | 1 | Rn | Rd | |||||||||||||||||
| Decode fields | Instruction Details | ||
|---|---|---|---|
| U | size | opcode | |
| 00000 | UNALLOCATED | ||
| 0001x | UNALLOCATED | ||
| 00100 | UNALLOCATED | ||
| 011xx | UNALLOCATED | ||
| 1001x | UNALLOCATED | ||
| 1x | 11011 | UNALLOCATED | |
| 0 | 00001 | SQADD | |
| 0 | 00101 | SQSUB | |
| 0 | 00110 | CMGT (register) | |
| 0 | 00111 | CMGE (register) | |
| 0 | 01000 | SSHL | |
| 0 | 01001 | SQSHL (register) | |
| 0 | 01010 | SRSHL | |
| 0 | 01011 | SQRSHL | |
| 0 | 10000 | ADD (vector) | |
| 0 | 10001 | CMTST | |
| 0 | 10100 | UNALLOCATED | |
| 0 | 10101 | UNALLOCATED | |
| 0 | 10110 | SQDMULH (vector) | |
| 0 | 10111 | UNALLOCATED | |
| 0 | 0x | 11000 | UNALLOCATED |
| 0 | 0x | 11001 | UNALLOCATED |
| 0 | 0x | 11010 | UNALLOCATED |
| 0 | 0x | 11011 | FMULX |
| 0 | 0x | 11100 | FCMEQ (register) |
| 0 | 0x | 11101 | UNALLOCATED |
| 0 | 0x | 11110 | UNALLOCATED |
| 0 | 0x | 11111 | FRECPS |
| 0 | 1x | 11000 | UNALLOCATED |
| 0 | 1x | 11001 | UNALLOCATED |
| 0 | 1x | 11010 | UNALLOCATED |
| 0 | 1x | 11100 | UNALLOCATED |
| 0 | 1x | 11101 | UNALLOCATED |
| 0 | 1x | 11110 | UNALLOCATED |
| 0 | 1x | 11111 | FRSQRTS |
| 1 | 00001 | UQADD | |
| 1 | 00101 | UQSUB | |
| 1 | 00110 | CMHI (register) | |
| 1 | 00111 | CMHS (register) | |
| 1 | 01000 | USHL | |
| 1 | 01001 | UQSHL (register) | |
| 1 | 01010 | URSHL | |
| 1 | 01011 | UQRSHL | |
| 1 | 10000 | SUB (vector) | |
| 1 | 10001 | CMEQ (register) | |
| 1 | 10100 | UNALLOCATED | |
| 1 | 10101 | UNALLOCATED | |
| 1 | 10110 | SQRDMULH (vector) | |
| 1 | 10111 | UNALLOCATED | |
| 1 | 0x | 11000 | UNALLOCATED |
| 1 | 0x | 11001 | UNALLOCATED |
| 1 | 0x | 11010 | UNALLOCATED |
| 1 | 0x | 11011 | UNALLOCATED |
| 1 | 0x | 11100 | FCMGE (register) |
| 1 | 0x | 11101 | FACGE |
| 1 | 0x | 11110 | UNALLOCATED |
| 1 | 0x | 11111 | UNALLOCATED |
| 1 | 1x | 11000 | UNALLOCATED |
| 1 | 1x | 11001 | UNALLOCATED |
| 1 | 1x | 11010 | FABD |
| 1 | 1x | 11100 | FCMGT (register) |
| 1 | 1x | 11101 | FACGT |
| 1 | 1x | 11110 | UNALLOCATED |
| 1 | 1x | 11111 | UNALLOCATED |
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | U | 1 | 1 | 1 | 1 | 1 | 0 | immh | immb | opcode | 1 | Rn | Rd | |||||||||||||||||
| Decode fields | Instruction Details | ||
|---|---|---|---|
| U | immh | opcode | |
| != 0000 | 00001 | UNALLOCATED | |
| != 0000 | 00011 | UNALLOCATED | |
| != 0000 | 00101 | UNALLOCATED | |
| != 0000 | 00111 | UNALLOCATED | |
| != 0000 | 01001 | UNALLOCATED | |
| != 0000 | 01011 | UNALLOCATED | |
| != 0000 | 01101 | UNALLOCATED | |
| != 0000 | 01111 | UNALLOCATED | |
| != 0000 | 101xx | UNALLOCATED | |
| != 0000 | 110xx | UNALLOCATED | |
| != 0000 | 11101 | UNALLOCATED | |
| != 0000 | 11110 | UNALLOCATED | |
| 0000 | UNALLOCATED | ||
| 0 | != 0000 | 00000 | SSHR |
| 0 | != 0000 | 00010 | SSRA |
| 0 | != 0000 | 00100 | SRSHR |
| 0 | != 0000 | 00110 | SRSRA |
| 0 | != 0000 | 01000 | UNALLOCATED |
| 0 | != 0000 | 01010 | SHL |
| 0 | != 0000 | 01100 | UNALLOCATED |
| 0 | != 0000 | 01110 | SQSHL (immediate) |
| 0 | != 0000 | 10000 | UNALLOCATED |
| 0 | != 0000 | 10001 | UNALLOCATED |
| 0 | != 0000 | 10010 | SQSHRN, SQSHRN2 |
| 0 | != 0000 | 10011 | SQRSHRN, SQRSHRN2 |
| 0 | != 0000 | 11100 | SCVTF (vector, fixed-point) |
| 0 | != 0000 | 11111 | FCVTZS (vector, fixed-point) |
| 1 | != 0000 | 00000 | USHR |
| 1 | != 0000 | 00010 | USRA |
| 1 | != 0000 | 00100 | URSHR |
| 1 | != 0000 | 00110 | URSRA |
| 1 | != 0000 | 01000 | SRI |
| 1 | != 0000 | 01010 | SLI |
| 1 | != 0000 | 01100 | SQSHLU |
| 1 | != 0000 | 01110 | UQSHL (immediate) |
| 1 | != 0000 | 10000 | SQSHRUN, SQSHRUN2 |
| 1 | != 0000 | 10001 | SQRSHRUN, SQRSHRUN2 |
| 1 | != 0000 | 10010 | UQSHRN, UQSHRN2 |
| 1 | != 0000 | 10011 | UQRSHRN, UQRSHRN2 |
| 1 | != 0000 | 11100 | UCVTF (vector, fixed-point) |
| 1 | != 0000 | 11111 | FCVTZU (vector, fixed-point) |
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | U | 1 | 1 | 1 | 1 | 1 | size | L | M | Rm | opcode | H | 0 | Rn | Rd | |||||||||||||||
| Decode fields | Instruction Details | Feature | ||
|---|---|---|---|---|
| U | size | opcode | ||
| 0000 | UNALLOCATED | - | ||
| 0010 | UNALLOCATED | - | ||
| 0100 | UNALLOCATED | - | ||
| 0110 | UNALLOCATED | - | ||
| 1000 | UNALLOCATED | - | ||
| 1010 | UNALLOCATED | - | ||
| 1110 | UNALLOCATED | - | ||
| 01 | 0001 | UNALLOCATED | - | |
| 01 | 0101 | UNALLOCATED | - | |
| 01 | 1001 | UNALLOCATED | - | |
| 0 | 0011 | SQDMLAL, SQDMLAL2 (by element) | - | |
| 0 | 0111 | SQDMLSL, SQDMLSL2 (by element) | - | |
| 0 | 1011 | SQDMULL, SQDMULL2 (by element) | - | |
| 0 | 1100 | SQDMULH (by element) | - | |
| 0 | 1101 | SQRDMULH (by element) | - | |
| 0 | 1111 | UNALLOCATED | - | |
| 0 | 00 | 0001 | FMLA (by element) — half-precision | FEAT_FP16 |
| 0 | 00 | 0101 | FMLS (by element) — half-precision | FEAT_FP16 |
| 0 | 00 | 1001 | FMUL (by element) — half-precision | FEAT_FP16 |
| 0 | 1x | 0001 | FMLA (by element) — single-precision and double-precision | - |
| 0 | 1x | 0101 | FMLS (by element) — single-precision and double-precision | - |
| 0 | 1x | 1001 | FMUL (by element) — single-precision and double-precision | - |
| 1 | 0011 | UNALLOCATED | - | |
| 1 | 0111 | UNALLOCATED | - | |
| 1 | 1011 | UNALLOCATED | - | |
| 1 | 1100 | UNALLOCATED | - | |
| 1 | 1101 | SQRDMLAH (by element) | FEAT_RDM | |
| 1 | 1111 | SQRDMLSH (by element) | FEAT_RDM | |
| 1 | 00 | 0001 | UNALLOCATED | - |
| 1 | 00 | 0101 | UNALLOCATED | - |
| 1 | 00 | 1001 | FMULX (by element) — half-precision | FEAT_FP16 |
| 1 | 1x | 0001 | UNALLOCATED | - |
| 1 | 1x | 0101 | UNALLOCATED | - |
| 1 | 1x | 1001 | FMULX (by element) — single-precision and double-precision | - |
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | op2 | 0 | Rm | 0 | len | op | 0 | 0 | Rn | Rd | ||||||||||||||
| Decode fields | Instruction Details | ||
|---|---|---|---|
| op2 | len | op | |
| x1 | UNALLOCATED | ||
| 00 | 00 | 0 | TBL — single register table |
| 00 | 00 | 1 | TBX — single register table |
| 00 | 01 | 0 | TBL — two register table |
| 00 | 01 | 1 | TBX — two register table |
| 00 | 10 | 0 | TBL — three register table |
| 00 | 10 | 1 | TBX — three register table |
| 00 | 11 | 0 | TBL — four register table |
| 00 | 11 | 1 | TBX — four register table |
| 1x | UNALLOCATED | ||
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | size | 0 | Rm | 0 | opcode | 1 | 0 | Rn | Rd | |||||||||||||||
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 1 | 0 | 1 | 1 | 1 | 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd | ||||||||||||||||
| Decode fields | Instruction Details |
|---|---|
| op2 | |
| x1 | UNALLOCATED |
| 00 | EXT |
| 1x | UNALLOCATED |
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | op | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | |||||||||||||||
| Decode fields | Instruction Details | |||
|---|---|---|---|---|
| Q | op | imm5 | imm4 | |
| x0000 | UNALLOCATED | |||
| 0 | 0000 | DUP (element) | ||
| 0 | 0001 | DUP (general) | ||
| 0 | 0010 | UNALLOCATED | ||
| 0 | 0100 | UNALLOCATED | ||
| 0 | 0110 | UNALLOCATED | ||
| 0 | 1xxx | UNALLOCATED | ||
| 0 | 0 | 0011 | UNALLOCATED | |
| 0 | 0 | 0101 | SMOV | |
| 0 | 0 | 0111 | UMOV | |
| 0 | 1 | UNALLOCATED | ||
| 1 | 0 | 0011 | INS (general) | |
| 1 | 0 | 0101 | SMOV | |
| 1 | 0 | x1000 | 0111 | UMOV |
| 1 | 1 | INS (element) | ||
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | U | 0 | 1 | 1 | 1 | 0 | a | 1 | 0 | Rm | 0 | 0 | opcode | 1 | Rn | Rd | ||||||||||||||
| Decode fields | Instruction Details | Feature | ||
|---|---|---|---|---|
| U | a | opcode | ||
| 0 | 0 | 000 | FMAXNM (vector) | FEAT_FP16 |
| 0 | 0 | 001 | FMLA (vector) | FEAT_FP16 |
| 0 | 0 | 010 | FADD (vector) | FEAT_FP16 |
| 0 | 0 | 011 | FMULX | FEAT_FP16 |
| 0 | 0 | 100 | FCMEQ (register) | FEAT_FP16 |
| 0 | 0 | 101 | UNALLOCATED | - |
| 0 | 0 | 110 | FMAX (vector) | FEAT_FP16 |
| 0 | 0 | 111 | FRECPS | FEAT_FP16 |
| 0 | 1 | 000 | FMINNM (vector) | FEAT_FP16 |
| 0 | 1 | 001 | FMLS (vector) | FEAT_FP16 |
| 0 | 1 | 010 | FSUB (vector) | FEAT_FP16 |
| 0 | 1 | 011 | UNALLOCATED | - |
| 0 | 1 | 100 | UNALLOCATED | - |
| 0 | 1 | 101 | UNALLOCATED | - |
| 0 | 1 | 110 | FMIN (vector) | FEAT_FP16 |
| 0 | 1 | 111 | FRSQRTS | FEAT_FP16 |
| 1 | 0 | 000 | FMAXNMP (vector) | FEAT_FP16 |
| 1 | 0 | 001 | UNALLOCATED | - |
| 1 | 0 | 010 | FADDP (vector) | FEAT_FP16 |
| 1 | 0 | 011 | FMUL (vector) | FEAT_FP16 |
| 1 | 0 | 100 | FCMGE (register) | FEAT_FP16 |
| 1 | 0 | 101 | FACGE | FEAT_FP16 |
| 1 | 0 | 110 | FMAXP (vector) | FEAT_FP16 |
| 1 | 0 | 111 | FDIV (vector) | FEAT_FP16 |
| 1 | 1 | 000 | FMINNMP (vector) | FEAT_FP16 |
| 1 | 1 | 001 | UNALLOCATED | - |
| 1 | 1 | 010 | FABD | FEAT_FP16 |
| 1 | 1 | 011 | UNALLOCATED | - |
| 1 | 1 | 100 | FCMGT (register) | FEAT_FP16 |
| 1 | 1 | 101 | FACGT | FEAT_FP16 |
| 1 | 1 | 110 | FMINP (vector) | FEAT_FP16 |
| 1 | 1 | 111 | UNALLOCATED | - |
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | U | 0 | 1 | 1 | 1 | 0 | a | 1 | 1 | 1 | 1 | 0 | 0 | opcode | 1 | 0 | Rn | Rd | ||||||||||||
| Decode fields | Instruction Details | Feature | ||
|---|---|---|---|---|
| U | a | opcode | ||
| 00xxx | UNALLOCATED | - | ||
| 010xx | UNALLOCATED | - | ||
| 10xxx | UNALLOCATED | - | ||
| 11110 | UNALLOCATED | - | ||
| 0 | 011xx | UNALLOCATED | - | |
| 0 | 11111 | UNALLOCATED | - | |
| 1 | 11100 | UNALLOCATED | - | |
| 0 | 0 | 11000 | FRINTN (vector) | FEAT_FP16 |
| 0 | 0 | 11001 | FRINTM (vector) | FEAT_FP16 |
| 0 | 0 | 11010 | FCVTNS (vector) | FEAT_FP16 |
| 0 | 0 | 11011 | FCVTMS (vector) | FEAT_FP16 |
| 0 | 0 | 11100 | FCVTAS (vector) | FEAT_FP16 |
| 0 | 0 | 11101 | SCVTF (vector, integer) | FEAT_FP16 |
| 0 | 1 | 01100 | FCMGT (zero) | FEAT_FP16 |
| 0 | 1 | 01101 | FCMEQ (zero) | FEAT_FP16 |
| 0 | 1 | 01110 | FCMLT (zero) | FEAT_FP16 |
| 0 | 1 | 01111 | FABS (vector) | FEAT_FP16 |
| 0 | 1 | 11000 | FRINTP (vector) | FEAT_FP16 |
| 0 | 1 | 11001 | FRINTZ (vector) | FEAT_FP16 |
| 0 | 1 | 11010 | FCVTPS (vector) | FEAT_FP16 |
| 0 | 1 | 11011 | FCVTZS (vector, integer) | FEAT_FP16 |
| 0 | 1 | 11101 | FRECPE | FEAT_FP16 |
| 0 | 1 | 11111 | UNALLOCATED | - |
| 1 | 0 | 11000 | FRINTA (vector) | FEAT_FP16 |
| 1 | 0 | 11001 | FRINTX (vector) | FEAT_FP16 |
| 1 | 0 | 11010 | FCVTNU (vector) | FEAT_FP16 |
| 1 | 0 | 11011 | FCVTMU (vector) | FEAT_FP16 |
| 1 | 0 | 11100 | FCVTAU (vector) | FEAT_FP16 |
| 1 | 0 | 11101 | UCVTF (vector, integer) | FEAT_FP16 |
| 1 | 1 | 01100 | FCMGE (zero) | FEAT_FP16 |
| 1 | 1 | 01101 | FCMLE (zero) | FEAT_FP16 |
| 1 | 1 | 01110 | UNALLOCATED | - |
| 1 | 1 | 01111 | FNEG (vector) | FEAT_FP16 |
| 1 | 1 | 11000 | UNALLOCATED | - |
| 1 | 1 | 11001 | FRINTI (vector) | FEAT_FP16 |
| 1 | 1 | 11010 | FCVTPU (vector) | FEAT_FP16 |
| 1 | 1 | 11011 | FCVTZU (vector, integer) | FEAT_FP16 |
| 1 | 1 | 11101 | FRSQRTE | FEAT_FP16 |
| 1 | 1 | 11111 | FSQRT (vector) | FEAT_FP16 |
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | U | 0 | 1 | 1 | 1 | 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd | ||||||||||||||||
| Decode fields | Instruction Details | Feature | |||
|---|---|---|---|---|---|
| Q | U | size | opcode | ||
| 0x | 0011 | UNALLOCATED | - | ||
| 11 | 0011 | UNALLOCATED | - | ||
| 0 | 0000 | UNALLOCATED | - | ||
| 0 | 0001 | UNALLOCATED | - | ||
| 0 | 0010 | SDOT (vector) | FEAT_DotProd | ||
| 0 | 1xxx | UNALLOCATED | - | ||
| 1 | 0000 | SQRDMLAH (vector) | FEAT_RDM | ||
| 1 | 0001 | SQRDMLSH (vector) | FEAT_RDM | ||
| 1 | 0010 | UDOT (vector) | FEAT_DotProd | ||
| 1 | 00 | 1101 | UNALLOCATED | - | |
| 1 | 00 | 1111 | UNALLOCATED | - | |
| 1 | 1x | 1101 | UNALLOCATED | - | |
| 1 | 10 | 0011 | UNALLOCATED | - | |
| 1 | 10 | 1111 | UNALLOCATED | - | |
| 0 | 01xx | UNALLOCATED | - | ||
| 0 | 1 | 01 | 1101 | UNALLOCATED | - |
| 1 | 0x | 01xx | UNALLOCATED | - | |
| 1 | 1x | 011x | UNALLOCATED | - | |
| 1 | 1 | 10 | 0101 | UNALLOCATED | - |
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | U | 0 | 1 | 1 | 1 | 0 | size | 1 | 0 | 0 | 0 | 0 | opcode | 1 | 0 | Rn | Rd | |||||||||||||
| Decode fields | Instruction Details | ||
|---|---|---|---|
| U | size | opcode | |
| 1000x | UNALLOCATED | ||
| 10101 | UNALLOCATED | ||
| 0x | 011xx | UNALLOCATED | |
| 1x | 10111 | UNALLOCATED | |
| 1x | 11110 | UNALLOCATED | |
| 11 | 10110 | UNALLOCATED | |
| 0 | 00000 | REV64 | |
| 0 | 00001 | REV16 (vector) | |
| 0 | 00010 | SADDLP | |
| 0 | 00011 | SUQADD | |
| 0 | 00100 | CLS (vector) | |
| 0 | 00101 | CNT | |
| 0 | 00110 | SADALP | |
| 0 | 00111 | SQABS | |
| 0 | 01000 | CMGT (zero) | |
| 0 | 01001 | CMEQ (zero) | |
| 0 | 01010 | CMLT (zero) | |
| 0 | 01011 | ABS | |
| 0 | 10010 | XTN, XTN2 | |
| 0 | 10011 | UNALLOCATED | |
| 0 | 10100 | SQXTN, SQXTN2 | |
| 0 | 0x | 10110 | FCVTN, FCVTN2 |
| 0 | 0x | 10111 | FCVTL, FCVTL2 |
| 0 | 0x | 11000 | FRINTN (vector) |
| 0 | 0x | 11001 | FRINTM (vector) |
| 0 | 0x | 11010 | FCVTNS (vector) |
| 0 | 0x | 11011 | FCVTMS (vector) |
| 0 | 0x | 11100 | FCVTAS (vector) |
| 0 | 0x | 11101 | SCVTF (vector, integer) |
| 0 | 1x | 01100 | FCMGT (zero) |
| 0 | 1x | 01101 | FCMEQ (zero) |
| 0 | 1x | 01110 | FCMLT (zero) |
| 0 | 1x | 01111 | FABS (vector) |
| 0 | 1x | 11000 | FRINTP (vector) |
| 0 | 1x | 11001 | FRINTZ (vector) |
| 0 | 1x | 11010 | FCVTPS (vector) |
| 0 | 1x | 11011 | FCVTZS (vector, integer) |
| 0 | 1x | 11100 | URECPE |
| 0 | 1x | 11101 | FRECPE |
| 0 | 1x | 11111 | UNALLOCATED |
| 1 | 00000 | REV32 (vector) | |
| 1 | 00001 | UNALLOCATED | |
| 1 | 00010 | UADDLP | |
| 1 | 00011 | USQADD | |
| 1 | 00100 | CLZ (vector) | |
| 1 | 00110 | UADALP | |
| 1 | 00111 | SQNEG | |
| 1 | 01000 | CMGE (zero) | |
| 1 | 01001 | CMLE (zero) | |
| 1 | 01010 | UNALLOCATED | |
| 1 | 01011 | NEG (vector) | |
| 1 | 10010 | SQXTUN, SQXTUN2 | |
| 1 | 10011 | SHLL, SHLL2 | |
| 1 | 10100 | UQXTN, UQXTN2 | |
| 1 | 0x | 10110 | FCVTXN, FCVTXN2 |
| 1 | 0x | 10111 | UNALLOCATED |
| 1 | 0x | 11000 | FRINTA (vector) |
| 1 | 0x | 11001 | FRINTX (vector) |
| 1 | 0x | 11010 | FCVTNU (vector) |
| 1 | 0x | 11011 | FCVTMU (vector) |
| 1 | 0x | 11100 | FCVTAU (vector) |
| 1 | 0x | 11101 | UCVTF (vector, integer) |
| 1 | 00 | 00101 | NOT |
| 1 | 01 | 00101 | RBIT (vector) |
| 1 | 1x | 00101 | UNALLOCATED |
| 1 | 1x | 01100 | FCMGE (zero) |
| 1 | 1x | 01101 | FCMLE (zero) |
| 1 | 1x | 01110 | UNALLOCATED |
| 1 | 1x | 01111 | FNEG (vector) |
| 1 | 1x | 11000 | UNALLOCATED |
| 1 | 1x | 11001 | FRINTI (vector) |
| 1 | 1x | 11010 | FCVTPU (vector) |
| 1 | 1x | 11011 | FCVTZU (vector, integer) |
| 1 | 1x | 11100 | URSQRTE |
| 1 | 1x | 11101 | FRSQRTE |
| 1 | 1x | 11111 | FSQRT (vector) |
| 1 | 10 | 10110 | UNALLOCATED |
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | U | 0 | 1 | 1 | 1 | 0 | size | 1 | 1 | 0 | 0 | 0 | opcode | 1 | 0 | Rn | Rd | |||||||||||||
| Decode fields | Instruction Details | Feature | ||
|---|---|---|---|---|
| U | size | opcode | ||
| 0000x | UNALLOCATED | - | ||
| 00010 | UNALLOCATED | - | ||
| 001xx | UNALLOCATED | - | ||
| 0100x | UNALLOCATED | - | ||
| 01011 | UNALLOCATED | - | ||
| 01101 | UNALLOCATED | - | ||
| 01110 | UNALLOCATED | - | ||
| 10xxx | UNALLOCATED | - | ||
| 1100x | UNALLOCATED | - | ||
| 111xx | UNALLOCATED | - | ||
| 0 | 00011 | SADDLV | - | |
| 0 | 01010 | SMAXV | - | |
| 0 | 11010 | SMINV | - | |
| 0 | 11011 | ADDV | - | |
| 0 | 00 | 01100 | FMAXNMV — half-precision | FEAT_FP16 |
| 0 | 00 | 01111 | FMAXV — half-precision | FEAT_FP16 |
| 0 | 01 | 01100 | UNALLOCATED | - |
| 0 | 01 | 01111 | UNALLOCATED | - |
| 0 | 10 | 01100 | FMINNMV — half-precision | FEAT_FP16 |
| 0 | 10 | 01111 | FMINV — half-precision | FEAT_FP16 |
| 0 | 11 | 01100 | UNALLOCATED | - |
| 0 | 11 | 01111 | UNALLOCATED | - |
| 1 | 00011 | UADDLV | - | |
| 1 | 01010 | UMAXV | - | |
| 1 | 11010 | UMINV | - | |
| 1 | 11011 | UNALLOCATED | - | |
| 1 | 0x | 01100 | FMAXNMV — single-precision and double-precision | - |
| 1 | 0x | 01111 | FMAXV — single-precision and double-precision | - |
| 1 | 1x | 01100 | FMINNMV — single-precision and double-precision | - |
| 1 | 1x | 01111 | FMINV — single-precision and double-precision | - |
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | U | 0 | 1 | 1 | 1 | 0 | size | 1 | Rm | opcode | 0 | 0 | Rn | Rd | ||||||||||||||||
| Decode fields | Instruction Details | |
|---|---|---|
| U | opcode | |
| 1111 | UNALLOCATED | |
| 0 | 0000 | SADDL, SADDL2 |
| 0 | 0001 | SADDW, SADDW2 |
| 0 | 0010 | SSUBL, SSUBL2 |
| 0 | 0011 | SSUBW, SSUBW2 |
| 0 | 0100 | ADDHN, ADDHN2 |
| 0 | 0101 | SABAL, SABAL2 |
| 0 | 0110 | SUBHN, SUBHN2 |
| 0 | 0111 | SABDL, SABDL2 |
| 0 | 1000 | SMLAL, SMLAL2 (vector) |
| 0 | 1001 | SQDMLAL, SQDMLAL2 (vector) |
| 0 | 1010 | SMLSL, SMLSL2 (vector) |
| 0 | 1011 | SQDMLSL, SQDMLSL2 (vector) |
| 0 | 1100 | SMULL, SMULL2 (vector) |
| 0 | 1101 | SQDMULL, SQDMULL2 (vector) |
| 0 | 1110 | PMULL, PMULL2 |
| 1 | 0000 | UADDL, UADDL2 |
| 1 | 0001 | UADDW, UADDW2 |
| 1 | 0010 | USUBL, USUBL2 |
| 1 | 0011 | USUBW, USUBW2 |
| 1 | 0100 | RADDHN, RADDHN2 |
| 1 | 0101 | UABAL, UABAL2 |
| 1 | 0110 | RSUBHN, RSUBHN2 |
| 1 | 0111 | UABDL, UABDL2 |
| 1 | 1000 | UMLAL, UMLAL2 (vector) |
| 1 | 1001 | UNALLOCATED |
| 1 | 1010 | UMLSL, UMLSL2 (vector) |
| 1 | 1011 | UNALLOCATED |
| 1 | 1100 | UMULL, UMULL2 (vector) |
| 1 | 1101 | UNALLOCATED |
| 1 | 1110 | UNALLOCATED |
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | U | 0 | 1 | 1 | 1 | 0 | size | 1 | Rm | opcode | 1 | Rn | Rd | |||||||||||||||||
| Decode fields | Instruction Details | Feature | ||
|---|---|---|---|---|
| U | size | opcode | ||
| 0 | 00000 | SHADD | - | |
| 0 | 00001 | SQADD | - | |
| 0 | 00010 | SRHADD | - | |
| 0 | 00100 | SHSUB | - | |
| 0 | 00101 | SQSUB | - | |
| 0 | 00110 | CMGT (register) | - | |
| 0 | 00111 | CMGE (register) | - | |
| 0 | 01000 | SSHL | - | |
| 0 | 01001 | SQSHL (register) | - | |
| 0 | 01010 | SRSHL | - | |
| 0 | 01011 | SQRSHL | - | |
| 0 | 01100 | SMAX | - | |
| 0 | 01101 | SMIN | - | |
| 0 | 01110 | SABD | - | |
| 0 | 01111 | SABA | - | |
| 0 | 10000 | ADD (vector) | - | |
| 0 | 10001 | CMTST | - | |
| 0 | 10010 | MLA (vector) | - | |
| 0 | 10011 | MUL (vector) | - | |
| 0 | 10100 | SMAXP | - | |
| 0 | 10101 | SMINP | - | |
| 0 | 10110 | SQDMULH (vector) | - | |
| 0 | 10111 | ADDP (vector) | - | |
| 0 | 0x | 11000 | FMAXNM (vector) | - |
| 0 | 0x | 11001 | FMLA (vector) | - |
| 0 | 0x | 11010 | FADD (vector) | - |
| 0 | 0x | 11011 | FMULX | - |
| 0 | 0x | 11100 | FCMEQ (register) | - |
| 0 | 0x | 11110 | FMAX (vector) | - |
| 0 | 0x | 11111 | FRECPS | - |
| 0 | 00 | 00011 | AND (vector) | - |
| 0 | 00 | 11101 | FMLAL, FMLAL2 (vector) — FMLAL | FEAT_FHM |
| 0 | 01 | 00011 | BIC (vector, register) | - |
| 0 | 01 | 11101 | UNALLOCATED | - |
| 0 | 1x | 11000 | FMINNM (vector) | - |
| 0 | 1x | 11001 | FMLS (vector) | - |
| 0 | 1x | 11010 | FSUB (vector) | - |
| 0 | 1x | 11011 | UNALLOCATED | - |
| 0 | 1x | 11100 | UNALLOCATED | - |
| 0 | 1x | 11110 | FMIN (vector) | - |
| 0 | 1x | 11111 | FRSQRTS | - |
| 0 | 10 | 00011 | ORR (vector, register) | - |
| 0 | 10 | 11101 | FMLSL, FMLSL2 (vector) — FMLSL | FEAT_FHM |
| 0 | 11 | 00011 | ORN (vector) | - |
| 0 | 11 | 11101 | UNALLOCATED | - |
| 1 | 00000 | UHADD | - | |
| 1 | 00001 | UQADD | - | |
| 1 | 00010 | URHADD | - | |
| 1 | 00100 | UHSUB | - | |
| 1 | 00101 | UQSUB | - | |
| 1 | 00110 | CMHI (register) | - | |
| 1 | 00111 | CMHS (register) | - | |
| 1 | 01000 | USHL | - | |
| 1 | 01001 | UQSHL (register) | - | |
| 1 | 01010 | URSHL | - | |
| 1 | 01011 | UQRSHL | - | |
| 1 | 01100 | UMAX | - | |
| 1 | 01101 | UMIN | - | |
| 1 | 01110 | UABD | - | |
| 1 | 01111 | UABA | - | |
| 1 | 10000 | SUB (vector) | - | |
| 1 | 10001 | CMEQ (register) | - | |
| 1 | 10010 | MLS (vector) | - | |
| 1 | 10011 | PMUL | - | |
| 1 | 10100 | UMAXP | - | |
| 1 | 10101 | UMINP | - | |
| 1 | 10110 | SQRDMULH (vector) | - | |
| 1 | 10111 | UNALLOCATED | - | |
| 1 | 0x | 11000 | FMAXNMP (vector) | - |
| 1 | 0x | 11010 | FADDP (vector) | - |
| 1 | 0x | 11011 | FMUL (vector) | - |
| 1 | 0x | 11100 | FCMGE (register) | - |
| 1 | 0x | 11101 | FACGE | - |
| 1 | 0x | 11110 | FMAXP (vector) | - |
| 1 | 0x | 11111 | FDIV (vector) | - |
| 1 | 00 | 00011 | EOR (vector) | - |
| 1 | 00 | 11001 | FMLAL, FMLAL2 (vector) — FMLAL2 | FEAT_FHM |
| 1 | 01 | 00011 | BSL | - |
| 1 | 01 | 11001 | UNALLOCATED | - |
| 1 | 1x | 11000 | FMINNMP (vector) | - |
| 1 | 1x | 11010 | FABD | - |
| 1 | 1x | 11011 | UNALLOCATED | - |
| 1 | 1x | 11100 | FCMGT (register) | - |
| 1 | 1x | 11101 | FACGT | - |
| 1 | 1x | 11110 | FMINP (vector) | - |
| 1 | 1x | 11111 | UNALLOCATED | - |
| 1 | 10 | 00011 | BIT | - |
| 1 | 10 | 11001 | FMLSL, FMLSL2 (vector) — FMLSL2 | FEAT_FHM |
| 1 | 11 | 00011 | BIF | - |
| 1 | 11 | 11001 | UNALLOCATED | - |
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | op | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | a | b | c | cmode | o2 | 1 | d | e | f | g | h | Rd | |||||||
| Decode fields | Instruction Details | Feature | |||
|---|---|---|---|---|---|
| Q | op | cmode | o2 | ||
| 0 | 0xxx | 1 | UNALLOCATED | - | |
| 0 | 0xx0 | 0 | MOVI — 32-bit shifted immediate | - | |
| 0 | 0xx1 | 0 | ORR (vector, immediate) — 32-bit | - | |
| 0 | 10xx | 1 | UNALLOCATED | - | |
| 0 | 10x0 | 0 | MOVI — 16-bit shifted immediate | - | |
| 0 | 10x1 | 0 | ORR (vector, immediate) — 16-bit | - | |
| 0 | 110x | 0 | MOVI — 32-bit shifting ones | - | |
| 0 | 110x | 1 | UNALLOCATED | - | |
| 0 | 1110 | 0 | MOVI — 8-bit | - | |
| 0 | 1110 | 1 | UNALLOCATED | - | |
| 0 | 1111 | 0 | FMOV (vector, immediate) — single-precision | - | |
| 0 | 1111 | 1 | FMOV (vector, immediate) — half-precision | FEAT_FP16 | |
| 1 | 1 | UNALLOCATED | - | ||
| 1 | 0xx0 | 0 | MVNI — 32-bit shifted immediate | - | |
| 1 | 0xx1 | 0 | BIC (vector, immediate) — 32-bit | - | |
| 1 | 10x0 | 0 | MVNI — 16-bit shifted immediate | - | |
| 1 | 10x1 | 0 | BIC (vector, immediate) — 16-bit | - | |
| 1 | 110x | 0 | MVNI — 32-bit shifting ones | - | |
| 0 | 1 | 1110 | 0 | MOVI — 64-bit scalar | - |
| 0 | 1 | 1111 | 0 | UNALLOCATED | - |
| 1 | 1 | 1110 | 0 | MOVI — 64-bit vector | - |
| 1 | 1 | 1111 | 0 | FMOV (vector, immediate) — double-precision | - |
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | U | 0 | 1 | 1 | 1 | 1 | 0 | != 0000 | immb | opcode | 1 | Rn | Rd | |||||||||||||||||
| immh | |||||||||||||||||||||||||||||||
The following constraints also apply to this encoding: immh != 0000 && immh != 0000
| Decode fields | Instruction Details | |
|---|---|---|
| U | opcode | |
| 00001 | UNALLOCATED | |
| 00011 | UNALLOCATED | |
| 00101 | UNALLOCATED | |
| 00111 | UNALLOCATED | |
| 01001 | UNALLOCATED | |
| 01011 | UNALLOCATED | |
| 01101 | UNALLOCATED | |
| 01111 | UNALLOCATED | |
| 10101 | UNALLOCATED | |
| 1011x | UNALLOCATED | |
| 110xx | UNALLOCATED | |
| 11101 | UNALLOCATED | |
| 11110 | UNALLOCATED | |
| 0 | 00000 | SSHR |
| 0 | 00010 | SSRA |
| 0 | 00100 | SRSHR |
| 0 | 00110 | SRSRA |
| 0 | 01000 | UNALLOCATED |
| 0 | 01010 | SHL |
| 0 | 01100 | UNALLOCATED |
| 0 | 01110 | SQSHL (immediate) |
| 0 | 10000 | SHRN, SHRN2 |
| 0 | 10001 | RSHRN, RSHRN2 |
| 0 | 10010 | SQSHRN, SQSHRN2 |
| 0 | 10011 | SQRSHRN, SQRSHRN2 |
| 0 | 10100 | SSHLL, SSHLL2 |
| 0 | 11100 | SCVTF (vector, fixed-point) |
| 0 | 11111 | FCVTZS (vector, fixed-point) |
| 1 | 00000 | USHR |
| 1 | 00010 | USRA |
| 1 | 00100 | URSHR |
| 1 | 00110 | URSRA |
| 1 | 01000 | SRI |
| 1 | 01010 | SLI |
| 1 | 01100 | SQSHLU |
| 1 | 01110 | UQSHL (immediate) |
| 1 | 10000 | SQSHRUN, SQSHRUN2 |
| 1 | 10001 | SQRSHRUN, SQRSHRUN2 |
| 1 | 10010 | UQSHRN, UQSHRN2 |
| 1 | 10011 | UQRSHRN, UQRSHRN2 |
| 1 | 10100 | USHLL, USHLL2 |
| 1 | 11100 | UCVTF (vector, fixed-point) |
| 1 | 11111 | FCVTZU (vector, fixed-point) |
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | U | 0 | 1 | 1 | 1 | 1 | size | L | M | Rm | opcode | H | 0 | Rn | Rd | |||||||||||||||
| Decode fields | Instruction Details | Feature | ||
|---|---|---|---|---|
| U | size | opcode | ||
| 01 | 1001 | UNALLOCATED | - | |
| 0 | 0010 | SMLAL, SMLAL2 (by element) | - | |
| 0 | 0011 | SQDMLAL, SQDMLAL2 (by element) | - | |
| 0 | 0110 | SMLSL, SMLSL2 (by element) | - | |
| 0 | 0111 | SQDMLSL, SQDMLSL2 (by element) | - | |
| 0 | 1000 | MUL (by element) | - | |
| 0 | 1010 | SMULL, SMULL2 (by element) | - | |
| 0 | 1011 | SQDMULL, SQDMULL2 (by element) | - | |
| 0 | 1100 | SQDMULH (by element) | - | |
| 0 | 1101 | SQRDMULH (by element) | - | |
| 0 | 1110 | SDOT (by element) | FEAT_DotProd | |
| 0 | 0x | 0000 | UNALLOCATED | - |
| 0 | 0x | 0100 | UNALLOCATED | - |
| 0 | 00 | 0001 | FMLA (by element) — half-precision | FEAT_FP16 |
| 0 | 00 | 0101 | FMLS (by element) — half-precision | FEAT_FP16 |
| 0 | 00 | 1001 | FMUL (by element) — half-precision | FEAT_FP16 |
| 0 | 01 | 0001 | UNALLOCATED | - |
| 0 | 01 | 0101 | UNALLOCATED | - |
| 0 | 1x | 0001 | FMLA (by element) — single-precision and double-precision | - |
| 0 | 1x | 0101 | FMLS (by element) — single-precision and double-precision | - |
| 0 | 1x | 1001 | FMUL (by element) — single-precision and double-precision | - |
| 0 | 10 | 0000 | FMLAL, FMLAL2 (by element) — FMLAL | FEAT_FHM |
| 0 | 10 | 0100 | FMLSL, FMLSL2 (by element) — FMLSL | FEAT_FHM |
| 0 | 11 | 0000 | UNALLOCATED | - |
| 0 | 11 | 0100 | UNALLOCATED | - |
| 1 | 0000 | MLA (by element) | - | |
| 1 | 0010 | UMLAL, UMLAL2 (by element) | - | |
| 1 | 0100 | MLS (by element) | - | |
| 1 | 0110 | UMLSL, UMLSL2 (by element) | - | |
| 1 | 1010 | UMULL, UMULL2 (by element) | - | |
| 1 | 1011 | UNALLOCATED | - | |
| 1 | 1101 | SQRDMLAH (by element) | FEAT_RDM | |
| 1 | 1110 | UDOT (by element) | FEAT_DotProd | |
| 1 | 1111 | SQRDMLSH (by element) | FEAT_RDM | |
| 1 | 0x | 1000 | UNALLOCATED | - |
| 1 | 0x | 1100 | UNALLOCATED | - |
| 1 | 00 | 0001 | UNALLOCATED | - |
| 1 | 00 | 0011 | UNALLOCATED | - |
| 1 | 00 | 0101 | UNALLOCATED | - |
| 1 | 00 | 0111 | UNALLOCATED | - |
| 1 | 00 | 1001 | FMULX (by element) — half-precision | FEAT_FP16 |
| 1 | 1x | 1001 | FMULX (by element) — single-precision and double-precision | - |
| 1 | 10 | 1000 | FMLAL, FMLAL2 (by element) — FMLAL2 | FEAT_FHM |
| 1 | 10 | 1100 | FMLSL, FMLSL2 (by element) — FMLSL2 | FEAT_FHM |
| 1 | 11 | 0001 | UNALLOCATED | - |
| 1 | 11 | 0011 | UNALLOCATED | - |
| 1 | 11 | 0101 | UNALLOCATED | - |
| 1 | 11 | 0111 | UNALLOCATED | - |
| 1 | 11 | 1000 | UNALLOCATED | - |
| 1 | 11 | 1100 | UNALLOCATED | - |
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | Rm | 1 | 0 | imm2 | opcode | Rn | Rd | ||||||||||||||
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | Rm | 1 | O | 0 | 0 | opcode | Rn | Rd | |||||||||||||
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | Op0 | Rm | 0 | Ra | Rn | Rd | |||||||||||||||||
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | opcode | Rn | Rd | |||||||||
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | 0 | S | 1 | 1 | 1 | 1 | 0 | ptype | 0 | rmode | opcode | scale | Rn | Rd | |||||||||||||||||
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| sf | 0 | S | 1 | 1 | 1 | 1 | 0 | ptype | 1 | rmode | opcode | 0 | 0 | 0 | 0 | 0 | 0 | Rn | Rd | ||||||||||||
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| M | 0 | S | 1 | 1 | 1 | 1 | 0 | ptype | 1 | opcode | 1 | 0 | 0 | 0 | 0 | Rn | Rd | ||||||||||||||
| Decode fields | Instruction Details | Feature | |||
|---|---|---|---|---|---|
| M | S | ptype | opcode | ||
| 1xxxxx | UNALLOCATED | - | |||
| 1 | UNALLOCATED | - | |||
| 0 | 0 | 00 | 000000 | FMOV (register) — single-precision | - |
| 0 | 0 | 00 | 000001 | FABS (scalar) — single-precision | - |
| 0 | 0 | 00 | 000010 | FNEG (scalar) — single-precision | - |
| 0 | 0 | 00 | 000011 | FSQRT (scalar) — single-precision | - |
| 0 | 0 | 00 | 000100 | UNALLOCATED | - |
| 0 | 0 | 00 | 000101 | FCVT — single-precision to double-precision | - |
| 0 | 0 | 00 | 000110 | UNALLOCATED | - |
| 0 | 0 | 00 | 000111 | FCVT — single-precision to half-precision | - |
| 0 | 0 | 00 | 001000 | FRINTN (scalar) — single-precision | - |
| 0 | 0 | 00 | 001001 | FRINTP (scalar) — single-precision | - |
| 0 | 0 | 00 | 001010 | FRINTM (scalar) — single-precision | - |
| 0 | 0 | 00 | 001011 | FRINTZ (scalar) — single-precision | - |
| 0 | 0 | 00 | 001100 | FRINTA (scalar) — single-precision | - |
| 0 | 0 | 00 | 001101 | UNALLOCATED | - |
| 0 | 0 | 00 | 001110 | FRINTX (scalar) — single-precision | - |
| 0 | 0 | 00 | 001111 | FRINTI (scalar) — single-precision | - |
| 0 | 0 | 00 | 0101xx | UNALLOCATED | - |
| 0 | 0 | 00 | 011xxx | UNALLOCATED | - |
| 0 | 0 | 01 | 000000 | FMOV (register) — double-precision | - |
| 0 | 0 | 01 | 000001 | FABS (scalar) — double-precision | - |
| 0 | 0 | 01 | 000010 | FNEG (scalar) — double-precision | - |
| 0 | 0 | 01 | 000011 | FSQRT (scalar) — double-precision | - |
| 0 | 0 | 01 | 000100 | FCVT — double-precision to single-precision | - |
| 0 | 0 | 01 | 000101 | UNALLOCATED | - |
| 0 | 0 | 01 | 000111 | FCVT — double-precision to half-precision | - |
| 0 | 0 | 01 | 001000 | FRINTN (scalar) — double-precision | - |
| 0 | 0 | 01 | 001001 | FRINTP (scalar) — double-precision | - |
| 0 | 0 | 01 | 001010 | FRINTM (scalar) — double-precision | - |
| 0 | 0 | 01 | 001011 | FRINTZ (scalar) — double-precision | - |
| 0 | 0 | 01 | 001100 | FRINTA (scalar) — double-precision | - |
| 0 | 0 | 01 | 001101 | UNALLOCATED | - |
| 0 | 0 | 01 | 001110 | FRINTX (scalar) — double-precision | - |
| 0 | 0 | 01 | 001111 | FRINTI (scalar) — double-precision | - |
| 0 | 0 | 01 | 0101xx | UNALLOCATED | - |
| 0 | 0 | 01 | 011xxx | UNALLOCATED | - |
| 0 | 0 | 10 | 0xxxxx | UNALLOCATED | - |
| 0 | 0 | 11 | 000000 | FMOV (register) — half-precision | FEAT_FP16 |
| 0 | 0 | 11 | 000001 | FABS (scalar) — half-precision | FEAT_FP16 |
| 0 | 0 | 11 | 000010 | FNEG (scalar) — half-precision | FEAT_FP16 |
| 0 | 0 | 11 | 000011 | FSQRT (scalar) — half-precision | FEAT_FP16 |
| 0 | 0 | 11 | 000100 | FCVT — half-precision to single-precision | - |
| 0 | 0 | 11 | 000101 | FCVT — half-precision to double-precision | - |
| 0 | 0 | 11 | 00011x | UNALLOCATED | - |
| 0 | 0 | 11 | 001000 | FRINTN (scalar) — half-precision | FEAT_FP16 |
| 0 | 0 | 11 | 001001 | FRINTP (scalar) — half-precision | FEAT_FP16 |
| 0 | 0 | 11 | 001010 | FRINTM (scalar) — half-precision | FEAT_FP16 |
| 0 | 0 | 11 | 001011 | FRINTZ (scalar) — half-precision | FEAT_FP16 |
| 0 | 0 | 11 | 001100 | FRINTA (scalar) — half-precision | FEAT_FP16 |
| 0 | 0 | 11 | 001101 | UNALLOCATED | - |
| 0 | 0 | 11 | 001110 | FRINTX (scalar) — half-precision | FEAT_FP16 |
| 0 | 0 | 11 | 001111 | FRINTI (scalar) — half-precision | FEAT_FP16 |
| 0 | 0 | 11 | 01xxxx | UNALLOCATED | - |
| 1 | UNALLOCATED | - | |||
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| M | 0 | S | 1 | 1 | 1 | 1 | 0 | ptype | 1 | Rm | op | 1 | 0 | 0 | 0 | Rn | opcode2 | ||||||||||||||
| Decode fields | Instruction Details | Feature | ||||
|---|---|---|---|---|---|---|
| M | S | ptype | op | opcode2 | ||
| xxxx1 | UNALLOCATED | - | ||||
| xxx1x | UNALLOCATED | - | ||||
| xx1xx | UNALLOCATED | - | ||||
| x1 | UNALLOCATED | - | ||||
| 1x | UNALLOCATED | - | ||||
| 10 | UNALLOCATED | - | ||||
| 1 | UNALLOCATED | - | ||||
| 0 | 0 | 00 | 00 | 00000 | FCMP | - |
| 0 | 0 | 00 | 00 | 01000 | FCMP | - |
| 0 | 0 | 00 | 00 | 10000 | FCMPE | - |
| 0 | 0 | 00 | 00 | 11000 | FCMPE | - |
| 0 | 0 | 01 | 00 | 00000 | FCMP | - |
| 0 | 0 | 01 | 00 | 01000 | FCMP | - |
| 0 | 0 | 01 | 00 | 10000 | FCMPE | - |
| 0 | 0 | 01 | 00 | 11000 | FCMPE | - |
| 0 | 0 | 11 | 00 | 00000 | FCMP | FEAT_FP16 |
| 0 | 0 | 11 | 00 | 01000 | FCMP | FEAT_FP16 |
| 0 | 0 | 11 | 00 | 10000 | FCMPE | FEAT_FP16 |
| 0 | 0 | 11 | 00 | 11000 | FCMPE | FEAT_FP16 |
| 1 | UNALLOCATED | - | ||||
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| M | 0 | S | 1 | 1 | 1 | 1 | 0 | ptype | 1 | imm8 | 1 | 0 | 0 | imm5 | Rd | ||||||||||||||||
| Decode fields | Instruction Details | Feature | |||
|---|---|---|---|---|---|
| M | S | ptype | imm5 | ||
| xxxx1 | UNALLOCATED | - | |||
| xxx1x | UNALLOCATED | - | |||
| xx1xx | UNALLOCATED | - | |||
| x1xxx | UNALLOCATED | - | |||
| 1xxxx | UNALLOCATED | - | |||
| 10 | UNALLOCATED | - | |||
| 1 | UNALLOCATED | - | |||
| 0 | 0 | 00 | 00000 | FMOV (scalar, immediate) — single-precision | - |
| 0 | 0 | 01 | 00000 | FMOV (scalar, immediate) — double-precision | - |
| 0 | 0 | 11 | 00000 | FMOV (scalar, immediate) — half-precision | FEAT_FP16 |
| 1 | UNALLOCATED | - | |||
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| M | 0 | S | 1 | 1 | 1 | 1 | 0 | ptype | 1 | Rm | cond | 0 | 1 | Rn | op | nzcv | |||||||||||||||
| Decode fields | Instruction Details | Feature | |||
|---|---|---|---|---|---|
| M | S | ptype | op | ||
| 10 | UNALLOCATED | - | |||
| 1 | UNALLOCATED | - | |||
| 0 | 0 | 00 | 0 | FCCMP — single-precision | - |
| 0 | 0 | 00 | 1 | FCCMPE — single-precision | - |
| 0 | 0 | 01 | 0 | FCCMP — double-precision | - |
| 0 | 0 | 01 | 1 | FCCMPE — double-precision | - |
| 0 | 0 | 11 | 0 | FCCMP — half-precision | FEAT_FP16 |
| 0 | 0 | 11 | 1 | FCCMPE — half-precision | FEAT_FP16 |
| 1 | UNALLOCATED | - | |||
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| M | 0 | S | 1 | 1 | 1 | 1 | 0 | ptype | 1 | Rm | opcode | 1 | 0 | Rn | Rd | ||||||||||||||||
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| M | 0 | S | 1 | 1 | 1 | 1 | 0 | ptype | 1 | Rm | cond | 1 | 1 | Rn | Rd | ||||||||||||||||
| Decode fields | Instruction Details | Feature | ||
|---|---|---|---|---|
| M | S | ptype | ||
| 10 | UNALLOCATED | - | ||
| 1 | UNALLOCATED | - | ||
| 0 | 0 | 00 | FCSEL — single-precision | - |
| 0 | 0 | 01 | FCSEL — double-precision | - |
| 0 | 0 | 11 | FCSEL — half-precision | FEAT_FP16 |
| 1 | UNALLOCATED | - | ||
These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| M | 0 | S | 1 | 1 | 1 | 1 | 1 | ptype | o1 | Rm | o0 | Ra | Rn | Rd | |||||||||||||||||
| Decode fields | Instruction Details | Feature | ||||
|---|---|---|---|---|---|---|
| M | S | ptype | o1 | o0 | ||
| 10 | UNALLOCATED | - | ||||
| 1 | UNALLOCATED | - | ||||
| 0 | 0 | 00 | 0 | 0 | FMADD — single-precision | - |
| 0 | 0 | 00 | 0 | 1 | FMSUB — single-precision | - |
| 0 | 0 | 00 | 1 | 0 | FNMADD — single-precision | - |
| 0 | 0 | 00 | 1 | 1 | FNMSUB — single-precision | - |
| 0 | 0 | 01 | 0 | 0 | FMADD — double-precision | - |
| 0 | 0 | 01 | 0 | 1 | FMSUB — double-precision | - |
| 0 | 0 | 01 | 1 | 0 | FNMADD — double-precision | - |
| 0 | 0 | 01 | 1 | 1 | FNMSUB — double-precision | - |
| 0 | 0 | 11 | 0 | 0 | FMADD — half-precision | FEAT_FP16 |
| 0 | 0 | 11 | 0 | 1 | FMSUB — half-precision | FEAT_FP16 |
| 0 | 0 | 11 | 1 | 0 | FNMADD — half-precision | FEAT_FP16 |
| 0 | 0 | 11 | 1 | 1 | FNMSUB — half-precision | FEAT_FP16 |
| 1 | UNALLOCATED | - | ||||
Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.