Store Pair of capabilities (immediate pre-index) determines the base register to be used, derives an address from the base register, and stores two capabilities to memory from two Capability registers. The address to use is derived from a base register value in A64 or capability base register in C64 and a immediate offset scaled by 16. For information about memory accesses, see Load/Store addressing modes.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | imm7 | Ct2 | Rn | Ct | ||||||||||||||||||
| L | |||||||||||||||||||||||||||||||
integer t = UInt(Ct); integer t2 = UInt(Ct2); integer n = UInt(Rn); AccType acctype = AccType_NORMAL; bits(64) offset = SignExtend(imm7:'0000', 64);
| <Ct> |
Is the capability name of the transfer register, encoded in the "Ct" field. |
| <Ct2> |
Is the capability name of the second transfer register, encoded in the "Ct2" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Cn|CSP> |
Is the capability name of the base register or stack pointer, encoded in the "Rn" field. |
| <imm> |
Is the signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, encoded in the "imm7" field. |
CheckCapabilitiesEnabled(); VirtualAddress base; Capability data1; Capability data2; boolean rt_unknown = FALSE; if (t == n || t2 == n) && n != 31 then Constraint c = ConstrainUnpredictable(Unpredictable_WBOVERLAPST); assert c IN {Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_NONE rt_unknown = FALSE; // value stored is pre-writeback when Constraint_UNKNOWN rt_unknown = TRUE; // value stored is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP EndOfInstruction(); base = BaseReg[n]; bits(64) addr1 = VAddress(base) + offset; bits(64) addr2 = addr1 + CAPABILITY_DBYTES<63:0>; if rt_unknown && t == n then data1 = Capability UNKNOWN; else data1 = C[t]; if rt_unknown && t2 == n then data2 = Capability UNKNOWN; else data2 = C[t2]; bits(64) cap_required1 = CAP_PERM_STORE; bits(64) cap_required2 = CAP_PERM_STORE; if CapIsTagSet(data1) then cap_required1 = cap_required1 OR CAP_PERM_STORE_CAP; if CapIsLocal(data1) then cap_required1 = cap_required1 OR CAP_PERM_STORE_LOCAL; if CapIsTagSet(data2) then cap_required2 = cap_required2 OR CAP_PERM_STORE_CAP; if CapIsLocal(data2) then cap_required2 = cap_required2 OR CAP_PERM_STORE_LOCAL; VACheckAddress(base, addr1, CAPABILITY_DBYTES, cap_required1, acctype); MemC[addr1, acctype] = data1; VACheckAddress(base, addr2, CAPABILITY_DBYTES, cap_required2, acctype); MemC[addr2, acctype] = data2; BaseReg[n] = VAAdd(base, offset);
Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23
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