LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB -- A64

LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB

Atomic bit clear on byte in memory atomically loads an 8-bit byte from memory, performs a bitwise AND with the complement of the value held in a register on it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register.

If the destination register is not WZR, LDCLRAB and LDCLRALB load from memory with acquire semantics.
LDCLRLB and LDCLRALB store to memory with release semantics.
LDCLRB has no memory ordering requirements.

For more information about memory ordering semantics, see Load-Acquire, Store-Release.

For information about memory accesses, see Load/Store addressing modes.

This instruction is used by the alias STCLRB, STCLRLB.

Integer
(FEAT_LSE)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	1	1	1	0	0	0	A	R	1	Rs					0	0	0	1	0	0	Rn					Rt
size																	opc

LDCLRAB (A == 1 && R == 0)

LDCLRAB <Ws>, <Wt>, [<Xn|SP>] // (PSTATE.C64 == '0')

LDCLRAB <Ws>, <Wt>, [<Cn|CSP>] // (PSTATE.C64 == '1')

LDCLRALB (A == 1 && R == 1)

LDCLRALB <Ws>, <Wt>, [<Xn|SP>] // (PSTATE.C64 == '0')

LDCLRALB <Ws>, <Wt>, [<Cn|CSP>] // (PSTATE.C64 == '1')

LDCLRB (A == 0 && R == 0)

LDCLRB <Ws>, <Wt>, [<Xn|SP>] // (PSTATE.C64 == '0')

LDCLRB <Ws>, <Wt>, [<Cn|CSP>] // (PSTATE.C64 == '1')

LDCLRLB (A == 0 && R == 1)

LDCLRLB <Ws>, <Wt>, [<Xn|SP>] // (PSTATE.C64 == '0')

LDCLRLB <Ws>, <Wt>, [<Cn|CSP>] // (PSTATE.C64 == '1')

if !HaveAtomicExt() then UNDEFINED; integer t = UInt(Rt); integer n = UInt(Rn); integer s = UInt(Rs); integer datasize = 8 << UInt(size); integer regsize = if datasize == 64 then 64 else 32; AccType ldacctype = if A == '1' && Rt != '11111' then AccType_ORDEREDATOMICRW else AccType_ATOMICRW; AccType stacctype = if R == '1' then AccType_ORDEREDATOMICRW else AccType_ATOMICRW; MemAtomicOp op; case opc of when '000' op = MemAtomicOp_ADD; when '001' op = MemAtomicOp_BIC; when '010' op = MemAtomicOp_EOR; when '011' op = MemAtomicOp_ORR; when '100' op = MemAtomicOp_SMAX; when '101' op = MemAtomicOp_SMIN; when '110' op = MemAtomicOp_UMAX; when '111' op = MemAtomicOp_UMIN;

Assembler Symbols

<Ws>	Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

<Wt>	Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Cn|CSP>

Is the name of the capability register or capability stack pointer holding the base address, encoded in the "Rn" field.

Alias Conditions

Alias	Is preferred when
STCLRB, STCLRLB	A == '0' && Rt == '11111'

Operation

bits(64) address; bits(datasize) value; bits(datasize) data; value = X[s]; VirtualAddress base = BaseReg[n]; data = MemAtomic(base, op, value, ldacctype, stacctype); if t != 31 then X[t] = ZeroExtend(data, regsize);

Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23