Load-Acquire RCpc capability determines the base register to be used, derives an address from the base register, loads a capability from memory, and writes it to the destination Capability register. The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that:
* There is no ordering requirement, separate from the requirements of a Load-AcquirePC or a Store-Release, created by having a Store-Release followed by a Load-AcquirePC instruction. * The reading of a value written by a Store-Release by a Load-AcquirePC instruction by the same observer does not make the write of the Store-Release globally observed.
This difference in memory ordering is not described in the pseudocode. For information about memory accesses, see Load/Store addressing modes.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | Rn | Ct | ||||||||
integer t = UInt(Ct); integer n = UInt(Rn); AccType acctype = AccType_ORDERED;
| <Ct> |
Is the capability name of the transfer register, encoded in the "Ct" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Cn|CSP> |
Is the capability name of the base register or stack pointer, encoded in the "Rn" field. |
CheckCapabilitiesEnabled(); VirtualAddress base; base = BaseReg[n]; bits(64) addr = VAddress(base); VACheckAddress(base, addr, CAPABILITY_DBYTES, CAP_PERM_LOAD, acctype); Capability data = MemC[addr, acctype]; data = CapSquashPostLoadCap(data, base); C[t] = data;
Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23
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