Load capability tags loads 4 Capability Tags from memory and writes them to the destination register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | Rn | Rt | ||||||||
| opc<1> | opc<0> | ||||||||||||||||||||||||||||||
integer t = UInt(Rt); integer n = UInt(Rn);
| <Xt> |
Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Cn|CSP> |
Is the capability name of the base register or stack pointer, encoded in the "Rn" field. |
CheckCapabilitiesEnabled(); VirtualAddress base = BaseReg[n]; integer count = 4; bits(64) addr = VAddress(base); VACheckAddress(base, addr, CAPABILITY_DBYTES*count, CAP_PERM_LOAD, AccType_NORMAL); bits(64) data = Zeros(64); if addr != Align(addr, CAPABILITY_DBYTES*count) then boolean iswrite = FALSE; boolean secondstage = FALSE; AArch64.Abort(addr, AArch64.AlignmentFault(AccType_NORMAL, iswrite, secondstage)); for i = 0 to count-1 bits(1) tag = AArch64.CapabilityTag(addr, AccType_NORMAL); data<i> = tag; addr = addr + CAPABILITY_DBYTES; if !VACheckPerm(base, CAP_PERM_LOAD_CAP) then data = Zeros(64); X[t] = data;
Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23
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