Load Exclusive Pair of capabilities determines the base register to be used, derives an address from the base register, loads two capabilities from memory, and writes the result to two Capability registers. A 256-bit pair requires the address to be 256-bit aligned. The PE marks the physical address being accessed as an exclusive access. This exclusive access mark is checked by Store Exclusive instructions. See Synchronization and semaphores. For information about memory accesses, see Load/Store addressing modes.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | Ct2 | Rn | Ct | ||||||||||||
| L | |||||||||||||||||||||||||||||||
integer t = UInt(Ct); integer t2 = UInt(Ct2); integer n = UInt(Rn); AccType acctype = AccType_ATOMIC;
| <Ct> |
Is the capability name of the transfer register, encoded in the "Ct" field. |
| <Ct2> |
Is the capability name of the second transfer register, encoded in the "Ct2" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Cn|CSP> |
Is the capability name of the base register or stack pointer, encoded in the "Rn" field. |
CheckCapabilitiesEnabled(); VirtualAddress base; boolean rt_unknown = FALSE; if t == t2 then Constraint c = ConstrainUnpredictable(Unpredictable_LDPOVERLAP); assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_UNKNOWN rt_unknown = TRUE; // result is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP EndOfInstruction(); base = BaseReg[n]; bits(64) addr = VAddress(base); VACheckAddress(base, addr, CAPABILITY_DBYTES*2, CAP_PERM_LOAD, acctype); AArch64.SetExclusiveMonitors(addr, CAPABILITY_DBYTES*2); if addr != Align(addr, CAPABILITY_DBYTES*2) then boolean iswrite = FALSE; boolean secondstage = FALSE; AArch64.Abort(addr, AArch64.AlignmentFault(acctype, iswrite, secondstage)); Capability data1 = MemC[addr, acctype]; Capability data2 = MemC[addr + CAPABILITY_DBYTES, acctype]; if rt_unknown then C[t] = Capability UNKNOWN; C[t2] = Capability UNKNOWN; else C[t] = CapSquashPostLoadCap(data1, base); C[t2] = CapSquashPostLoadCap(data2, base);
Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23
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