Unseal load and branch loads a capability and an offset, derives, unseals, and branches to the destination Capability register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | imm7 | 1 | 0 | 0 | Cn | 0 | 0 | 0 | 0 | 0 | ||||||||||
integer n = UInt(Cn); bits(64) offset = SignExtend(imm7:'0000',64); BranchType branch_type = BranchType_INDIR;
| <Cn|CSP> |
Is the capability name of the base register or stack pointer, encoded in the "Cn" field. |
| <imm> |
Is the signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, encoded in the "imm7" field. |
CheckCapabilitiesEnabled(); Capability base; Capability target; if n == 31 then CheckSPAlignment(); base = CSP[]; else base = C[n]; // When C29 is used, the unsealed capability is written back to C29. if n == 29 then if CapIsTagSet(base) && CapIsSealed(base) && CapGetObjectType(base) == CAP_SEAL_TYPE_LB then base = CapUnseal(base); VirtualAddress vabase = VAFromCapability(base); bits(64) addr = VAddress(vabase) + offset; VACheckAddress(vabase,addr,CAPABILITY_DBYTES,CAP_PERM_LOAD,AccType_NORMAL); target = MemC[addr,AccType_NORMAL]; target = CapSquashPostLoadCap(target,vabase); C[29] = base; else VirtualAddress vabase = VAFromCapability(base); bits(64) addr = VAddress(vabase) + offset; VACheckAddress(vabase,addr,CAPABILITY_DBYTES,CAP_PERM_LOAD,AccType_NORMAL); target = MemC[addr,AccType_NORMAL]; target = CapSquashPostLoadCap(target,vabase); if !IsInRestricted() && !CapCheckPermissions(target, CAP_PERM_EXECUTIVE) then target = CapWithTagClear(target); if CapIsTagSet(target) && CapIsSealed(target) && CapGetObjectType(target) == CAP_SEAL_TYPE_RB then target = CapUnseal(target); BranchXToCapability(target, branch_type);
Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23
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