SQRSHRN, SQRSHRN2
Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.
The SQRSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the SQRSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.
If saturation occurs, the cumulative saturation bit FPSR.QC is set.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 2 classes:
Scalar
and
Vector
Scalar
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | != 0000 | immb | 1 | 0 | 0 | 1 | 1 | 1 | Rn | Rd |
| U | | immh | | | op | | | |
integer d = UInt(Rd);
integer n = UInt(Rn);
if immh == '0000' then UNDEFINED;
if immh<3> == '1' then UNDEFINED;
integer esize = 8 << HighestSetBit(immh);
integer datasize = esize;
integer elements = 1;
integer part = 0;
integer shift = (2 * esize) - UInt(immh:immb);
boolean round = (op == '1');
boolean unsigned = (U == '1');
Vector
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 0 | 0 | 1 | 1 | 1 | 1 | 0 | != 0000 | immb | 1 | 0 | 0 | 1 | 1 | 1 | Rn | Rd |
| | U | | immh | | | op | | | |
integer d = UInt(Rd);
integer n = UInt(Rn);
if immh == '0000' then SEE(asimdimm);
if immh<3> == '1' then UNDEFINED;
integer esize = 8 << HighestSetBit(immh);
integer datasize = 64;
integer part = UInt(Q);
integer elements = datasize DIV esize;
integer shift = (2 * esize) - UInt(immh:immb);
boolean round = (op == '1');
boolean unsigned = (U == '1');
Assembler Symbols
| 2 |
Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is
encoded in
Q :
| Q |
2 |
| 0 |
[absent] |
| 1 |
[present] |
|
| <Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
|
| <Tb> |
Is an arrangement specifier,
encoded in
immh:Q :
|
| <Vn> |
Is the name of the SIMD&FP source register, encoded in the "Rn" field.
|
| <Ta> |
Is an arrangement specifier,
encoded in
immh :
|
| <Vb> |
Is the destination width specifier,
encoded in
immh :
| immh |
<Vb> |
| 0000 |
RESERVED |
| 0001 |
B |
| 001x |
H |
| 01xx |
S |
| 1xxx |
RESERVED |
|
| <d> |
Is the number of the SIMD&FP destination register, in the "Rd" field.
|
| <Va> |
Is the source width specifier,
encoded in
immh :
| immh |
<Va> |
| 0000 |
RESERVED |
| 0001 |
H |
| 001x |
S |
| 01xx |
D |
| 1xxx |
RESERVED |
|
| <n> |
Is the number of the first SIMD&FP source register, encoded in the "Rn" field.
|
| <shift> |
For the scalar variant: is the right shift amount, in the range 1 to the destination operand width in bits,
encoded in
immh:immb :
| immh |
<shift> |
| 0000 |
RESERVED |
| 0001 |
(16-UInt(immh:immb)) |
| 001x |
(32-UInt(immh:immb)) |
| 01xx |
(64-UInt(immh:immb)) |
| 1xxx |
RESERVED |
|
|
For the vector variant: is the right shift amount, in the range 1 to the destination element width in bits,
encoded in
immh:immb :
|
Operation
CheckFPAdvSIMDEnabled64();
bits(datasize*2) operand = V[n];
bits(datasize) result;
integer round_const = if round then (1 << (shift - 1)) else 0;
integer element;
boolean sat;
for e = 0 to elements-1
element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
(Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
if sat then FPSR.QC = '1';
Vpart[d, part] = result;
Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2
; Build timestamp: 2022-01-11T11:23
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