SHA1 hash update (parity).
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | Rm | 0 | 0 | 0 | 1 | 0 | 0 | Rn | Rd | ||||||||||||
integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); if !HaveSHA1Ext() then UNDEFINED;
| <Qd> |
Is the 128-bit name of the SIMD&FP source and destination, encoded in the "Rd" field. |
| <Sn> |
Is the 32-bit name of the second SIMD&FP source register, encoded in the "Rn" field. |
| <Vm> |
Is the name of the third SIMD&FP source register, encoded in the "Rm" field. |
AArch64.CheckFPAdvSIMDEnabled(); bits(128) X = V[d]; bits(32) Y = V[n]; // Note: 32 not 128 bits wide bits(128) W = V[m]; bits(32) t; for e = 0 to 3 t = SHAparity(X<63:32>, X<95:64>, X<127:96>); Y = Y + ROL(X<31:0>, 5) + t + Elem[W, e, 32]; X<63:32> = ROL(X<63:32>, 30); <Y, X> = ROL(Y : X, 32); V[d] = X;
Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.