CSNEG -- A64

Conditional Select Negation returns, in the destination register, the value of the first source register if the condition is TRUE, and otherwise returns the negated value of the second source register.

integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); integer datasize = if sf == '1' then 64 else 32; bits(4) condition = cond; boolean else_inv = (op == '1'); boolean else_inc = (o2 == '1');

Assembler Symbols

<Wd>	Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Wn>	Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field.

<Wm>	Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field.

<Xd>	Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Xn>	Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field.

<Xm>	Is the 64-bit name of the second general-purpose source register, encoded in the "Rm" field.

<cond>

Is one of the standard conditions, encoded in the "cond" field in the standard way.

Alias Conditions

Alias	Is preferred when
CNEG	cond != '111x' && Rn == Rm

Operation

bits(datasize) result; bits(datasize) operand1 = X[n]; bits(datasize) operand2 = X[m]; if ConditionHolds(condition) then result = operand1; else result = operand2; if else_inv then result = NOT(result); if else_inc then result = result + 1; X[d] = result;

Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
sf	1	0	1	1	0	1	0	1	0	0	Rm					cond				0	1	Rn					Rd
	op																				o2

CSNEG

32-bit (sf == 0)

64-bit (sf == 1)

Assembler Symbols

Alias Conditions

Operation