LDR (unsigned offset, capability, normal base)

Load capability (unsigned offset) determines the base register to be used, derives an address from the base register and an immediate offset, loads a capability from memory, and writes the result to the destination Capability register. For information about memory accesses, see Load/Store addressing modes.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	0	0	0	1	0	0	1	imm12												Rn					Ct
									L

LDR <Ct>, [<Xn|SP>{, #<imm>}] // (PSTATE.C64 == '0')

LDR <Ct>, [<Cn|CSP>{, #<imm>}] // (PSTATE.C64 == '1')

integer t = UInt(Ct); integer n = UInt(Rn); bits(64) offset = ZeroExtend(imm12:'0000', 64);

Assembler Symbols

<Ct>	Is the capability name of the transfer register, encoded in the "Ct" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Cn|CSP>

Is the capability name of the base register or stack pointer, encoded in the "Rn" field.

<imm>

Is the optional unsigned immediate byte offset, a multiple of 16 in the range 0 to 65520, defaulting to 0, encoded in the "imm12" field.

Operation

CheckCapabilitiesEnabled(); VirtualAddress base; Capability data; acctype = AccType_NORMAL; base = BaseReg[n]; bits(64) addr = VAddress(base) + offset; VACheckAddress(base, addr, CAPABILITY_DBYTES, CAP_PERM_LOAD, acctype); data = MemC[addr, acctype]; data = CapSquashPostLoadCap(data, base); C[t] = data;

Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23