STRH

Store Register Halfword (register) via alternate base determines the base register to be used, derives an address from the base register and an offset register, and stores a halfword to the calculated address in memory. The offset register can optionally be shifted and extended. The base register used by this operation depends on PSTATE.C64: if PSTATE.C64 is 1, the base register is a 64-bit general-purpose register; if PSTATE.C64 is 0, the base register is a capability general-purpose register. For information about memory accesses, see Load/Store addressing modes.

STRH <Wt>, [<Cn|CSP>, <R><m>{, <extend> <amount>}] // (PSTATE.C64 == '0')

STRH <Wt>, [<Xn|SP>, <R><m>{, <extend> <amount>}] // (PSTATE.C64 == '1')

integer t = UInt(Rt); integer n = UInt(Rn); integer m = UInt(Rm); integer scale = 1; ExtendType extend_type = DecodeRegExtend(sign:'1':sz); integer shift = if S == '1' then scale else 0; integer regsize = 32;

Assembler Symbols

<Wt>	Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Cn|CSP>

Is the capability name of the base register or stack pointer, encoded in the "Rn" field.

<R>

Is a width specifier, encoded in sz:

sz	<R>
0	W
1	X

<m>	Is the number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field.

Is the index extend and shift specifier, encoded in sign:sz:

sign	sz	<extend>
0	0	UXTW
0	1	LSL
1	0	SXTW
1	1	SXTX

Is the index shift amount, encoded in S:

S	<amount>
0	[absent]
1	#1

Operation

CheckCapabilitiesEnabled(); bits(64) offset = ExtendReg(m, extend_type, shift); VirtualAddress base = AltBaseReg[n]; integer datasize = 8 << scale; bits(64) addr = VAddress(base) + offset; VACheckAddress(base, addr, datasize DIV 8, CAP_PERM_STORE, AccType_NORMAL); bits(datasize) data = X[t]; Mem[addr, datasize DIV 8, AccType_NORMAL] = data;

Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	0	0	0	0	0	1	0	1	0	0	Rm					sign	1	sz	S	1	1	Rn					Rt
									L											opc