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LDR (immediate)

Load Register (immediate) loads a word or doubleword from memory and writes it to a register. The address that is used for the load is calculated from a base register and an immediate offset. For information about memory accesses, see Load/Store addressing modes. The Unsigned offset variant scales the immediate offset value by the size of the value accessed before adding it to the base register value.

It has encodings from 3 classes: Post-index , Pre-index and Unsigned offset

Post-index

313029282726252423222120191817161514131211109876543210
1x111000010imm901RnRt
sizeopc

32-bit (size == 10)

LDR <Wt>, [<Xn|SP>], #<simm> // (PSTATE.C64 == '0')

LDR <Wt>, [<Cn|CSP>], #<simm> // (PSTATE.C64 == '1')

64-bit (size == 11)

LDR <Xt>, [<Xn|SP>], #<simm> // (PSTATE.C64 == '0')

LDR <Xt>, [<Cn|CSP>], #<simm> // (PSTATE.C64 == '1')

boolean wback = TRUE; boolean postindex = TRUE; integer scale = UInt(size); bits(64) offset = SignExtend(imm9, 64);

Pre-index

313029282726252423222120191817161514131211109876543210
1x111000010imm911RnRt
sizeopc

32-bit (size == 10)

LDR <Wt>, [<Xn|SP>, #<simm>]! // (PSTATE.C64 == '0')

LDR <Wt>, [<Cn|CSP>, #<simm>]! // (PSTATE.C64 == '1')

64-bit (size == 11)

LDR <Xt>, [<Xn|SP>, #<simm>]! // (PSTATE.C64 == '0')

LDR <Xt>, [<Cn|CSP>, #<simm>]! // (PSTATE.C64 == '1')

boolean wback = TRUE; boolean postindex = FALSE; integer scale = UInt(size); bits(64) offset = SignExtend(imm9, 64);

Unsigned offset

313029282726252423222120191817161514131211109876543210
1x11100101imm12RnRt
sizeopc

32-bit (size == 10)

LDR <Wt>, [<Xn|SP>{, #<pimm>}] // (PSTATE.C64 == '0')

LDR <Wt>, [<Cn|CSP>{, #<pimm>}] // (PSTATE.C64 == '1')

64-bit (size == 11)

LDR <Xt>, [<Xn|SP>{, #<pimm>}] // (PSTATE.C64 == '0')

LDR <Xt>, [<Cn|CSP>{, #<pimm>}] // (PSTATE.C64 == '1')

boolean wback = FALSE; boolean postindex = FALSE; integer scale = UInt(size); bits(64) offset = LSL(ZeroExtend(imm12, 64), scale);

For information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDR (immediate).

Assembler Symbols

<Wt>

Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xt>

Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Cn|CSP>

Is the name of the capability register or capability stack pointer holding the base address, encoded in the "Rn" field.

<simm>

Is the signed immediate byte offset, in the range -256 to 255, encoded in the "imm9" field.

<pimm>

For the 32-bit variant: is the optional positive immediate byte offset, a multiple of 4 in the range 0 to 16380, defaulting to 0 and encoded in the "imm12" field as <pimm>/4.

For the 64-bit variant: is the optional positive immediate byte offset, a multiple of 8 in the range 0 to 32760, defaulting to 0 and encoded in the "imm12" field as <pimm>/8.

Shared Decode

integer n = UInt(Rn); integer t = UInt(Rt); AccType acctype = AccType_NORMAL; MemOp memop; boolean signed; integer regsize; if opc<1> == '0' then // store or zero-extending load memop = if opc<0> == '1' then MemOp_LOAD else MemOp_STORE; regsize = if size == '11' then 64 else 32; signed = FALSE; else if size == '11' then UNDEFINED; else // sign-extending load memop = MemOp_LOAD; if size == '10' && opc<0> == '1' then UNDEFINED; regsize = if opc<0> == '1' then 32 else 64; signed = TRUE; integer datasize = 8 << scale;

Operation

bits(64) address; bits(datasize) data; boolean wb_unknown = FALSE; boolean rt_unknown = FALSE; if memop == MemOp_LOAD && wback && n == t && n != 31 then c = ConstrainUnpredictable(Unpredictable_WBOVERLAPLD); assert c IN {Constraint_WBSUPPRESS, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_WBSUPPRESS wback = FALSE; // writeback is suppressed when Constraint_UNKNOWN wb_unknown = TRUE; // writeback is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP EndOfInstruction(); if memop == MemOp_STORE && wback && n == t && n != 31 then c = ConstrainUnpredictable(Unpredictable_WBOVERLAPST); assert c IN {Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_NONE rt_unknown = FALSE; // value stored is original value when Constraint_UNKNOWN rt_unknown = TRUE; // value stored is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP EndOfInstruction(); VirtualAddress base; base = BaseReg[n, memop == MemOp_PREFETCH]; address = VAddress(base); if ! postindex then address = address + offset; case memop of when MemOp_STORE VACheckAddress(base, address, datasize DIV 8, CAP_PERM_STORE, acctype); if rt_unknown then data = bits(datasize) UNKNOWN; else data = X[t]; Mem[address, datasize DIV 8, acctype] = data; when MemOp_LOAD VACheckAddress(base, address, datasize DIV 8, CAP_PERM_LOAD, acctype); data = Mem[address, datasize DIV 8, acctype]; if signed then X[t] = SignExtend(data, regsize); else X[t] = ZeroExtend(data, regsize); when MemOp_PREFETCH address = VAddress(base); Prefetch(address, t<4:0>); if wback then if wb_unknown then base = VirtualAddress UNKNOWN; else base = VAAdd(base,offset); BaseReg[n] = base;

Base Instructions
SIMD&FP Instructions
Morello Instructions
Index by Encoding
Shared Pseudocode
Proprietary Notice

Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23

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