Load-Acquire Exclusive capability determines the base register to be used, derives an address from the base register, loads two capabilities from memory, and writes the result to two Capability registers. The memory access is atomic. The PE marks the physical address being accessed as an exclusive access. This exclusive access mark is checked by Store Exclusive instructions. See Synchronization and semaphores. See Synchronization and semaphores. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about memory accesses, see Load/Store addressing modes.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | Rn | Ct | ||||||||
| L | |||||||||||||||||||||||||||||||
integer t = UInt(Ct); integer n = UInt(Rn); AccType acctype = AccType_ORDEREDATOMIC;
| <Ct> |
Is the capability name of the transfer register, encoded in the "Ct" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Cn|CSP> |
Is the capability name of the base register or stack pointer, encoded in the "Rn" field. |
CheckCapabilitiesEnabled(); VirtualAddress base; base = BaseReg[n]; bits(64) addr = VAddress(base); VACheckAddress(base, addr, CAPABILITY_DBYTES, CAP_PERM_LOAD, acctype); AArch64.SetExclusiveMonitors(addr, CAPABILITY_DBYTES); Capability data = MemC[addr, acctype]; data = CapSquashPostLoadCap(data, base); C[t] = data;
Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23
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