SHA256 schedule update 0.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | Rn | Rd | ||||||||
integer d = UInt(Rd); integer n = UInt(Rn); if !HaveSHA256Ext() then UNDEFINED;
| <Vd> |
Is the name of the SIMD&FP source and destination register, encoded in the "Rd" field. |
| <Vn> |
Is the name of the second SIMD&FP source register, encoded in the "Rn" field. |
AArch64.CheckFPAdvSIMDEnabled(); bits(128) operand1 = V[d]; bits(128) operand2 = V[n]; bits(128) result; bits(128) T = operand2<31:0> : operand1<127:32>; bits(32) elt; for e = 0 to 3 elt = Elem[T, e, 32]; elt = ROR(elt, 7) EOR ROR(elt, 18) EOR LSR(elt, 3); Elem[result, e, 32] = elt + Elem[operand1, e, 32]; V[d] = result;
Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.