Base Instructions
SIMD&FP Instructions
Morello Instructions
Index by Encoding
Shared Pseudocode
Proprietary Notice

LDP (SIMD&FP)

Load Pair of SIMD&FP registers. This instruction loads a pair of SIMD&FP registers from memory. The address that is used for the load is calculated from a base register value and an optional immediate offset.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 3 classes: Post-index , Pre-index and Signed offset

Post-index

313029282726252423222120191817161514131211109876543210
opc10110011imm7Rt2RnRt
L

32-bit (opc == 00)

LDP <St1>, <St2>, [<Xn|SP>], #<imm> // (PSTATE.C64 == '0')

LDP <St1>, <St2>, [<Cn|CSP>], #<imm> // (PSTATE.C64 == '1')

64-bit (opc == 01)

LDP <Dt1>, <Dt2>, [<Xn|SP>], #<imm> // (PSTATE.C64 == '0')

LDP <Dt1>, <Dt2>, [<Cn|CSP>], #<imm> // (PSTATE.C64 == '1')

128-bit (opc == 10)

LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm> // (PSTATE.C64 == '0')

LDP <Qt1>, <Qt2>, [<Cn|CSP>], #<imm> // (PSTATE.C64 == '1')

boolean wback = TRUE; boolean postindex = TRUE;

Pre-index

313029282726252423222120191817161514131211109876543210
opc10110111imm7Rt2RnRt
L

32-bit (opc == 00)

LDP <St1>, <St2>, [<Xn|SP>, #<imm>]! // (PSTATE.C64 == '0')

LDP <St1>, <St2>, [<Cn|CSP>, #<imm>]! // (PSTATE.C64 == '1')

64-bit (opc == 01)

LDP <Dt1>, <Dt2>, [<Xn|SP>, #<imm>]! // (PSTATE.C64 == '0')

LDP <Dt1>, <Dt2>, [<Cn|CSP>, #<imm>]! // (PSTATE.C64 == '1')

128-bit (opc == 10)

LDP <Qt1>, <Qt2>, [<Xn|SP>, #<imm>]! // (PSTATE.C64 == '0')

LDP <Qt1>, <Qt2>, [<Cn|CSP>, #<imm>]! // (PSTATE.C64 == '1')

boolean wback = TRUE; boolean postindex = FALSE;

Signed offset

313029282726252423222120191817161514131211109876543210
opc10110101imm7Rt2RnRt
L

32-bit (opc == 00)

LDP <St1>, <St2>, [<Xn|SP>{, #<imm>}] // (PSTATE.C64 == '0')

LDP <St1>, <St2>, [<Cn|CSP>{, #<imm>}] // (PSTATE.C64 == '1')

64-bit (opc == 01)

LDP <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}] // (PSTATE.C64 == '0')

LDP <Dt1>, <Dt2>, [<Cn|CSP>{, #<imm>}] // (PSTATE.C64 == '1')

128-bit (opc == 10)

LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}] // (PSTATE.C64 == '0')

LDP <Qt1>, <Qt2>, [<Cn|CSP>{, #<imm>}] // (PSTATE.C64 == '1')

boolean wback = FALSE; boolean postindex = FALSE;

For information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDP (SIMD&FP).

Assembler Symbols

<Dt1>

Is the 64-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.

<Dt2>

Is the 64-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.

<Qt1>

Is the 128-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.

<Qt2>

Is the 128-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.

<St1>

Is the 32-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.

<St2>

Is the 32-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Cn|CSP>

Is the name of the capability register or capability stack pointer holding the base address, encoded in the "Rn" field.

<imm>

For the 32-bit post-index and 32-bit pre-index variant: is the signed immediate byte offset, a multiple of 4 in the range -256 to 252, encoded in the "imm7" field as <imm>/4.

For the 32-bit signed offset variant: is the optional signed immediate byte offset, a multiple of 4 in the range -256 to 252, defaulting to 0 and encoded in the "imm7" field as <imm>/4.

For the 64-bit post-index and 64-bit pre-index variant: is the signed immediate byte offset, a multiple of 8 in the range -512 to 504, encoded in the "imm7" field as <imm>/8.

For the 64-bit signed offset variant: is the optional signed immediate byte offset, a multiple of 8 in the range -512 to 504, defaulting to 0 and encoded in the "imm7" field as <imm>/8.

For the 128-bit post-index and 128-bit pre-index variant: is the signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, encoded in the "imm7" field as <imm>/16.

For the 128-bit signed offset variant: is the optional signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, defaulting to 0 and encoded in the "imm7" field as <imm>/16.

Shared Decode

integer n = UInt(Rn); integer t = UInt(Rt); integer t2 = UInt(Rt2); AccType acctype = AccType_VEC; MemOp memop = if L == '1' then MemOp_LOAD else MemOp_STORE; if opc == '11' then UNDEFINED; integer scale = 2 + UInt(opc); integer datasize = 8 << scale; bits(64) offset = LSL(SignExtend(imm7, 64), scale);

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) data1; bits(datasize) data2; constant integer dbytes = datasize DIV 8; boolean rt_unknown = FALSE; if memop == MemOp_LOAD && t == t2 then Constraint c = ConstrainUnpredictable(Unpredictable_LDPOVERLAP); assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_UNKNOWN rt_unknown = TRUE; // result is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP EndOfInstruction(); VirtualAddress base = BaseReg[n]; bits(64) address = VAddress(base); if ! postindex then address = address + offset; case memop of when MemOp_STORE VACheckAddress(base, address, dbytes * 2, CAP_PERM_STORE, acctype); data1 = V[t]; data2 = V[t2]; Mem[address + 0 , dbytes, acctype] = data1; Mem[address + dbytes, dbytes, acctype] = data2; when MemOp_LOAD VACheckAddress(base, address, dbytes * 2, CAP_PERM_LOAD, acctype); data1 = Mem[address + 0 , dbytes, acctype]; data2 = Mem[address + dbytes, dbytes, acctype]; if rt_unknown then data1 = bits(datasize) UNKNOWN; data2 = bits(datasize) UNKNOWN; V[t] = data1; V[t2] = data2; if wback then base = VAAdd(base,offset); BaseReg[n] = base;

Base Instructions
SIMD&FP Instructions
Morello Instructions
Index by Encoding
Shared Pseudocode
Proprietary Notice

Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23

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