Store Pair of Registers, with non-temporal hint, calculates an address from a base register value and an immediate offset, and stores two 32-bit words or two 64-bit doublewords to the calculated address, from two registers. For information about memory accesses, see Load/Store addressing modes. For information about Non-temporal pair instructions, see Load/Store Non-temporal pair.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| x | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | imm7 | Rt2 | Rn | Rt | ||||||||||||||||||
| opc | L | ||||||||||||||||||||||||||||||
STNP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}] // (PSTATE.C64 == '0')
STNP <Wt1>, <Wt2>, [<Cn|CSP>{, #<imm>}] // (PSTATE.C64 == '1')
STNP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}] // (PSTATE.C64 == '0')
STNP <Xt1>, <Xt2>, [<Cn|CSP>{, #<imm>}] // (PSTATE.C64 == '1')
boolean wback = FALSE; boolean postindex = FALSE;
| <Wt1> |
Is the 32-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field. |
| <Wt2> |
Is the 32-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field. |
| <Xt1> |
Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field. |
| <Xt2> |
Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Cn|CSP> |
Is the name of the capability register or capability stack pointer holding the base address, encoded in the "Rn" field. |
integer n = UInt(Rn); integer t = UInt(Rt); integer t2 = UInt(Rt2); AccType acctype = AccType_STREAM; MemOp memop = if L == '1' then MemOp_LOAD else MemOp_STORE; if opc<0> == '1' then UNDEFINED; integer scale = 2 + UInt(opc<1>); integer datasize = 8 << scale; bits(64) offset = LSL(SignExtend(imm7, 64), scale);
bits(datasize) data1; bits(datasize) data2; constant integer dbytes = datasize DIV 8; boolean rt_unknown = FALSE; if memop == MemOp_LOAD && t == t2 then Constraint c = ConstrainUnpredictable(Unpredictable_LDPOVERLAP); assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_UNKNOWN rt_unknown = TRUE; // result is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP EndOfInstruction(); VirtualAddress base = BaseReg[n]; bits(64) address = VAddress(base); if ! postindex then address = address + offset; case memop of when MemOp_STORE VACheckAddress(base, address, dbytes * 2, CAP_PERM_STORE, acctype); if rt_unknown && t == n then data1 = bits(datasize) UNKNOWN; else data1 = X[t]; if rt_unknown && t2 == n then data2 = bits(datasize) UNKNOWN; else data2 = X[t2]; Mem[address + 0 , dbytes, acctype] = data1; Mem[address + dbytes, dbytes, acctype] = data2; when MemOp_LOAD VACheckAddress(base, address, dbytes * 2, CAP_PERM_LOAD, acctype); data1 = Mem[address + 0 , dbytes, acctype]; data2 = Mem[address + dbytes, dbytes, acctype]; if rt_unknown then data1 = bits(datasize) UNKNOWN; data2 = bits(datasize) UNKNOWN; X[t] = data1; X[t2] = data2; if wback then base = VAAdd(base,offset); BaseReg[n] = base;
Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23
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