Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | imm5 | 0 | 0 | 1 | 0 | 1 | 1 | Rn | Rd | ||||||||||||
integer d = UInt(Rd); integer n = UInt(Rn); integer size; case Q:imm5 of when 'xxxxx1' size = 0; // SMOV [WX]d, Vn.B when 'xxxx10' size = 1; // SMOV [WX]d, Vn.H when '1xx100' size = 2; // SMOV Xd, Vn.S otherwise UNDEFINED; integer idxdsize = if imm5<4> == '1' then 128 else 64; integer index = UInt(imm5<4:size+1>); integer esize = 8 << size; integer datasize = if Q == '1' then 64 else 32;
| <Wd> |
Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. |
| <Xd> |
Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. |
| <Vn> |
Is the name of the SIMD&FP source register, encoded in the "Rn" field. |
| <index> |
For the 32-bit variant: is the element index
encoded in
imm5:
| ||||||||||
For the 64-reg,SMOV-64-reg variant: is the element index
encoded in
imm5:
|
CheckFPAdvSIMDEnabled64(); bits(idxdsize) operand = V[n]; X[d] = SignExtend(Elem[operand, index, esize], datasize);
Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23
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