STLR -- A64

Store-Release Register stores a 32-bit word or a 64-bit doubleword to a memory location, from a register. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about memory accesses, see Load/Store addressing modes.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	x	0	0	1	0	0	0	1	0	0	(1)	(1)	(1)	(1)	(1)	1	(1)	(1)	(1)	(1)	(1)	Rn					Rt
size									L		Rs					o0	Rt2

32-bit (size == 10)

STLR <Wt>, [<Xn|SP>{,#0}] // (PSTATE.C64 == '0')

STLR <Wt>, [<Cn|CSP>{,#0}] // (PSTATE.C64 == '1')

64-bit (size == 11)

STLR <Xt>, [<Xn|SP>{,#0}] // (PSTATE.C64 == '0')

STLR <Xt>, [<Cn|CSP>{,#0}] // (PSTATE.C64 == '1')

integer n = UInt(Rn); integer t = UInt(Rt); integer t2 = UInt(Rt2); // ignored by load/store single register integer s = UInt(Rs); // ignored by all loads and store-release AccType acctype = if o0 == '0' then AccType_LIMITEDORDERED else AccType_ORDERED; MemOp memop = if L == '1' then MemOp_LOAD else MemOp_STORE; integer elsize = 8 << UInt(size); integer regsize = if elsize == 64 then 64 else 32; integer datasize = elsize;

Assembler Symbols

<Wt>	Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xt>	Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Cn|CSP>

Is the name of the capability register or capability stack pointer holding the base address, encoded in the "Rn" field.

Operation

bits(datasize) data; constant integer dbytes = datasize DIV 8; VirtualAddress base = BaseReg[n]; bits(64) address = VAddress(base); case memop of when MemOp_STORE VACheckAddress(base, address, datasize DIV 8, CAP_PERM_STORE, acctype); data = X[t]; Mem[address, dbytes, acctype] = data; when MemOp_LOAD VACheckAddress(base, address, datasize DIV 8, CAP_PERM_LOAD, acctype); data = Mem[address, dbytes, acctype]; X[t] = ZeroExtend(data, regsize);

Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23