Floating-point signaling Compare (scalar). This instruction compares the two SIMD&FP source register values, or the first SIMD&FP source register value and zero. It writes the result to the PSTATE.{N, Z, C, V} flags.
If either operand is any type of NaN, or if either operand is a signaling NaN, the instruction raises an Invalid Operation exception.
A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | ftype | 1 | Rm | 0 | 0 | 1 | 0 | 0 | 0 | Rn | 1 | x | 0 | 0 | 0 | |||||||||
| opc | |||||||||||||||||||||||||||||||
FCMPE <Hn>, #0.0
FCMPE <Sn>, #0.0
FCMPE <Dn>, #0.0
integer n = UInt(Rn); integer m = UInt(Rm); // ignored when opc<0> == '1' integer datasize; case ftype of when '00' datasize = 32; when '01' datasize = 64; when '10' UNDEFINED; when '11' if HaveFP16Ext() then datasize = 16; else UNDEFINED; boolean signal_all_nans = (opc<1> == '1'); boolean cmp_with_zero = (opc<0> == '1');
| <Dm> |
Is the 64-bit name of the second SIMD&FP source register, encoded in the "Rm" field. |
| <Hm> |
Is the 16-bit name of the second SIMD&FP source register, encoded in the "Rm" field. |
| <Sm> |
Is the 32-bit name of the second SIMD&FP source register, encoded in the "Rm" field. |
NaNs
The IEEE 754 standard specifies that the result of a comparison is precisely one of <, ==, > or unordered. If either or both of the operands are NaNs, they are unordered, and all three of (Operand1 < Operand2), (Operand1 == Operand2) and (Operand1 > Operand2) are false. This case results in the FPSCR flags being set to N=0, Z=0, C=1, and V=1.
FCMPE raises an Invalid Operation exception if either operand is any type of NaN, and is suitable for testing for <, <=, >, >=, and other predicates that raise an exception when the operands are unordered.
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2; operand2 = if cmp_with_zero then FPZero('0') else V[m]; PSTATE.<N,Z,C,V> = FPCompare(operand1, operand2, signal_all_nans, FPCR);
Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23
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