Load SIMD&FP Register (PC-relative literal). This instruction loads a SIMD&FP register from memory. The address that is used for the load is calculated from the PC value and an immediate offset.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| opc | 0 | 1 | 1 | 1 | 0 | 0 | imm19 | Rt | |||||||||||||||||||||||
integer t = UInt(Rt); integer size; bits(64) offset; case opc of when '00' size = 4; when '01' size = 8; when '10' size = 16; when '11' UNDEFINED; offset = SignExtend(imm19:'00', 64);
| <Dt> |
Is the 64-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field. |
| <Qt> |
Is the 128-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field. |
| <St> |
Is the 32-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field. |
| <label> |
Is the program label from which the data is to be loaded. Its offset from the address of this instruction, in the range +/-1MB, is encoded as "imm19" times 4. |
VirtualAddress base = VAFromCapability(PCC); bits(64) address = VAddress(base) + offset; bits(size*8) data; CheckFPAdvSIMDEnabled64(); VACheckAddress(base, address, size, CAP_PERM_LOAD, AccType_VEC); data = Mem[address, size, AccType_VEC]; V[t] = data;
Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23
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