STUR (integer)

Store Register (unscaled) via alternate base determines the base register to be used, derives an address from the base register and an immediate offset, and stores a 32-bit word or 64-bit doubleword to the calculated address in memory. The base register used by this operation depends on PSTATE.C64: if PSTATE.C64 is 1, the base register is a 64-bit general-purpose register; if PSTATE.C64 is 0, the base register is a capability general-purpose register. For information about memory accesses, see Load/Store addressing modes.

Doubleword

STUR <Xt>, [<Cn|CSP>{, #<imm>}] // (PSTATE.C64 == '0')

STUR <Xt>, [<Xn|SP>{, #<imm>}] // (PSTATE.C64 == '1')

integer t = UInt(Rt); integer n = UInt(Rn); bits(64) offset = SignExtend(imm9, 64); datasize = 64; regsize = 64;

Word

STUR <Wt>, [<Cn|CSP>{, #<imm>}] // (PSTATE.C64 == '0')

STUR <Wt>, [<Xn|SP>{, #<imm>}] // (PSTATE.C64 == '1')

integer t = UInt(Rt); integer n = UInt(Rn); bits(64) offset = SignExtend(imm9, 64); datasize = 32; regsize = 32;

Assembler Symbols

<Wt>	Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xt>	Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Cn|CSP>

Is the capability name of the base register or stack pointer, encoded in the "Rn" field.

<imm>

Is the optional signed immediate byte offset, in the range -256 to 255, defaulting to 0, encoded in the "imm9" field.

Operation

CheckCapabilitiesEnabled(); VirtualAddress base = AltBaseReg[n]; bits(64) addr = VAddress(base) + offset; VACheckAddress(base, addr, datasize DIV 8, CAP_PERM_STORE, AccType_NORMAL); bits(datasize) data = X[t]; Mem[addr, datasize DIV 8, AccType_NORMAL] = data;

Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23

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1	1	1	0	0	0	1	0	1	1	0	imm9									0	0	Rn					Rt
								op1<1>	op1<0>	V										op2

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	0	0	0	1	0	1	0	0	imm9									0	0	Rn					Rt
								op1<1>	op1<0>	V										op2