STR (unsigned offset, integer)

Store Register (unsigned offset) via alternate base determines the base register to be used, derives an address from the base register and an immediate offset, and stores a 32-bit word or 64-bit doubleword to the calculated address in memory. The base register used by this operation depends on PSTATE.C64: if PSTATE.C64 is 1, the base register is a 64-bit general-purpose register; if PSTATE.C64 is 0, the base register is a capability general-purpose register. For information about memory accesses, see Load/Store addressing modes.

Doubleword

integer t = UInt(Rt); integer n = UInt(Rn); bits(64) offset = ZeroExtend(imm9:'000', 64); datasize = 64; regsize = 64;

Word

integer t = UInt(Rt); integer n = UInt(Rn); bits(64) offset = ZeroExtend(imm9:'00', 64); datasize = 32; regsize = 32;

Assembler Symbols

<Wt>	Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xt>	Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Cn|CSP>

Is the capability name of the base register or stack pointer, encoded in the "Rn" field.

<imm>	For the doubleword variant: is the optional unsigned immediate byte offset, a multiple of 8 in the range 0 to 4088, defaulting to 0, encoded in the "imm9" field.
	For the word variant: is the optional unsigned immediate byte offset, a multiple of 4 in the range 0 to 2044, defaulting to 0, encoded in the "imm9" field.

Operation

CheckCapabilitiesEnabled(); VirtualAddress base = AltBaseReg[n]; bits(64) addr = VAddress(base) + offset; VACheckAddress(base, addr, datasize DIV 8, CAP_PERM_STORE, AccType_NORMAL); bits(datasize) data = X[t]; Mem[addr, datasize DIV 8, AccType_NORMAL] = data;

Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23

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1	0	0	0	0	0	1	0	0	1	0	imm9									1	1	Rn					Rt
										L										op

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	0	0	0	0	0	1	0	0	1	0	imm9									1	0	Rn					Rt
										L										op