SYS -- A64

SYS

System instruction. For more information, see Op0 equals 0b01, cache maintenance, TLB maintenance, and address translation instructions for the encodings of System instructions.

This instruction is used by the aliases AT, DC, IC, and TLBI.

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1	1	0	1	0	1	0	1	0	0	0	0	1	op1			CRn				CRm				op2			Rt
										L

SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}

AArch64.CheckSystemAccess('01', op1, CRn, CRm, op2, Rt, L); integer t = UInt(Rt); integer sys_op0 = 1; integer sys_op1 = UInt(op1); integer sys_op2 = UInt(op2); integer sys_crn = UInt(CRn); integer sys_crm = UInt(CRm); boolean has_result = (L == '1');

Assembler Symbols

<op1>

Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op1" field.

<Cn>	Is a name 'Cn', with 'n' in the range 0 to 15, encoded in the "CRn" field.

<Cm>	Is a name 'Cm', with 'm' in the range 0 to 15, encoded in the "CRm" field.

<op2>

Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op2" field.

<Xt>	Is the 64-bit name of the optional general-purpose source register, defaulting to '11111', encoded in the "Rt" field.

Alias Conditions

Alias	Is preferred when
AT	CRn == '0111' && CRm == '100x' && SysOp(op1,'0111',CRm,op2) == Sys_AT
DC	CRn == '0111' && SysOp(op1,'0111',CRm,op2) == Sys_DC
IC	CRn == '0111' && SysOp(op1,'0111',CRm,op2) == Sys_IC
TLBI	CRn == '1000' && SysOp(op1,'1000',CRm,op2) == Sys_TLBI

Operation

if has_result then X[t] = AArch64.SysInstrWithResult(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2); else if AArch64.SysInstrInputIsCapability(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2) then AArch64.SysInstrWithCapability(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2, C[t]); else AArch64.SysInstr(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2, X[t]);

Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23

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1	1	0	1	0	1	0	1	0	0	0	0	1	op1			CRn				CRm				op2			Rt
										L

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	1	0	1	0	1	0	0	0	0	1	op1			CRn				CRm				op2			Rt
										L

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	1	0	1	0	1	0	0	0	0	1	op1			CRn				CRm				op2			Rt
										L