Load-Acquire RCpc Register Halfword derives an address from a base register value, loads a halfword from the derived address in memory, zero-extends it and writes it to a register.
The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that:
This difference in memory ordering is not described in the pseudocode.
For information about memory accesses, see Load/Store addressing modes.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | (1) | (1) | (1) | (1) | (1) | 1 | 1 | 0 | 0 | 0 | 0 | Rn | Rt | ||||||||
| size | Rs | ||||||||||||||||||||||||||||||
integer n = UInt(Rn); integer t = UInt(Rt); integer s = UInt(Rs); // ignored by all loads and store-release AccType acctype = AccType_ORDERED; integer elsize = 8 << UInt(size); integer regsize = if elsize == 64 then 64 else 32; integer datasize = elsize;
| <Wt> |
Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Cn|CSP> |
Is the name of the capability register or capability stack pointer holding the base address, encoded in the "Rn" field. |
bits(datasize) data; constant integer dbytes = datasize DIV 8; VirtualAddress base = BaseReg[n]; bits(64) address = VAddress(base); VACheckAddress(base, address, dbytes, CAP_PERM_LOAD, acctype); data = Mem[address, dbytes, acctype]; X[t] = ZeroExtend(data, regsize);
Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.