LDAPR -- A64

LDAPR

Load-Acquire RCpc Register derives an address from a base register value, loads a 32-bit word or 64-bit doubleword from the derived address in memory, and writes it to a register.

The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that:

There is no ordering requirement, separate from the requirements of a Load-AcquirePC or a Store-Release, created by having a Store-Release followed by a Load-AcquirePC instruction.
The reading of a value written by a Store-Release by a Load-AcquirePC instruction by the same observer does not make the write of the Store-Release globally observed.

This difference in memory ordering is not described in the pseudocode.

For information about memory accesses, see Load/Store addressing modes.

Integer
(FEAT_LRCPC)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	x	1	1	1	0	0	0	1	0	1	(1)	(1)	(1)	(1)	(1)	1	1	0	0	0	0	Rn					Rt
size											Rs

32-bit (size == 10)

LDAPR <Wt>, [<Xn|SP> {,#0}] // (PSTATE.C64 == '0')

LDAPR <Wt>, [<Cn|CSP> {,#0}] // (PSTATE.C64 == '1')

64-bit (size == 11)

LDAPR <Xt>, [<Xn|SP> {,#0}] // (PSTATE.C64 == '0')

LDAPR <Xt>, [<Cn|CSP> {,#0}] // (PSTATE.C64 == '1')

integer n = UInt(Rn); integer t = UInt(Rt); integer s = UInt(Rs); // ignored by all loads and store-release AccType acctype = AccType_ORDERED; integer elsize = 8 << UInt(size); integer regsize = if elsize == 64 then 64 else 32; integer datasize = elsize;

Assembler Symbols

<Wt>	Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

<Xt>	Is the 64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Cn|CSP>

Is the name of the capability register or capability stack pointer holding the base address, encoded in the "Rn" field.

Operation

bits(datasize) data; constant integer dbytes = datasize DIV 8; VirtualAddress base = BaseReg[n]; bits(64) address = VAddress(base); VACheckAddress(base, address, dbytes, CAP_PERM_LOAD, acctype); data = Mem[address, dbytes, acctype]; X[t] = ZeroExtend(data, regsize);