LDTR

Load capability (unprivileged) determines the base register to be used, derives an address from the base register and an immediate offset, loads a capability from memory, and writes the result to the destination Capability register. For information about memory accesses, see Load/Store addressing modes. Memory accesses made by the instruction behave as if the instruction was executed at EL0 if the Effective value of PSTATE.UAO is 0 and either:

* The instruction is executed at EL1. * The instruction is executed at EL2 when the Effective value of both HCR_EL2.E2H and HCR_EL2.TGE are 1.

Otherwise, the memory access operates with the restrictions determined by the Exception level at which the instruction is executed.

In all cases the memory access operates with the capability restrictions as determined by the Exception level at which the instruction is executed.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	0	1	0	0	0	1	0	0	1	0	imm9									1	0	Rn					Ct
								opc<1>	opc<0>

LDTR <Ct>, [<Xn|SP>, #<imm>] // (PSTATE.C64 == '0')

LDTR <Ct>, [<Cn|CSP>, #<imm>] // (PSTATE.C64 == '1')

integer t = UInt(Ct); integer n = UInt(Rn); bits(64) offset = SignExtend(imm9:'0000', 64);

Assembler Symbols

<Ct>	Is the capability name of the transfer register, encoded in the "Ct" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Cn|CSP>

Is the capability name of the base register or stack pointer, encoded in the "Rn" field.

<imm>

Is the signed immediate byte offset, a multiple of 16 in the range -4096 to 4080, encoded in the "imm9" field.

Operation

CheckCapabilitiesEnabled(); VirtualAddress base; Capability data; unpriv_at_el1 = PSTATE.EL == EL1; unpriv_at_el2 = PSTATE.EL == EL2 && HaveVirtHostExt() && HCR_EL2.<E2H,TGE> == '11'; user_access_override = HaveUAOExt() && PSTATE.UAO == '1'; if !user_access_override && (unpriv_at_el1 || unpriv_at_el2) then acctype = AccType_UNPRIV; else acctype = AccType_NORMAL; base = BaseReg[n]; bits(64) addr = VAddress(base) + offset; VACheckAddress(base, addr, CAPABILITY_DBYTES, CAP_PERM_LOAD, acctype); data = MemC[addr, acctype]; data = CapSquashPostLoadCap(data, base); C[t] = data;

Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23