Store-Release Register Byte via alternate base determines the base register to be used, derives an address from the base register and an offset register, and stores a byte to the calculated address in memory. The base register used by this operation depends on PSTATE.C64: if PSTATE.C64 is 1, the base register is a 64-bit general-purpose register; if PSTATE.C64 is 0, the base register is a capability general-purpose register. This instruction loads from memory with acquire semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release. For information about memory accesses, see Load/Store addressing modes.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | Rn | Rt | ||||||||
| L | |||||||||||||||||||||||||||||||
integer t = UInt(Rt); integer n = UInt(Rn); datasize=8; regsize=32; AccType acctype = AccType_ORDERED;
| <Wt> |
Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Cn|CSP> |
Is the capability name of the base register or stack pointer, encoded in the "Rn" field. |
CheckCapabilitiesEnabled(); VirtualAddress address; bits(datasize) data; base = AltBaseReg[n]; data = X[t]; bits(64) addr = VAddress(base); VACheckAddress(base, addr, datasize DIV 8, CAP_PERM_STORE, acctype); Mem[addr, datasize DIV 8, acctype] = data;
Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23
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