BIT -- A64

Bitwise Insert if True. This instruction inserts each bit from the first source SIMD&FP register into the SIMD&FP destination register if the corresponding bit of the second source SIMD&FP register is 1, otherwise leaves the bit in the destination register unchanged.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	Q	1	0	1	1	1	0	1	0	1	Rm					0	0	0	1	1	1	Rn					Rd
								opc2

integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); integer esize = 8; integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; VBitOp op; case opc2 of when '00' op = VBitOp_VEOR; when '01' op = VBitOp_VBSL; when '10' op = VBitOp_VBIT; when '11' op = VBitOp_VBIF;

Assembler Symbols

<Vd>	Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>

Is an arrangement specifier, encoded in Q:

Q	<T>
0	8B
1	16B

<Vn>	Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm>	Is the name of the second SIMD&FP source register, encoded in the "Rm" field.

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand1; bits(datasize) operand2; bits(datasize) operand3; bits(datasize) operand4 = V[n]; case op of when VBitOp_VEOR operand1 = V[m]; operand2 = Zeros(); operand3 = Ones(); when VBitOp_VBSL operand1 = V[m]; operand2 = operand1; operand3 = V[d]; when VBitOp_VBIT operand1 = V[d]; operand2 = operand1; operand3 = V[m]; when VBitOp_VBIF operand1 = V[d]; operand2 = operand1; operand3 = NOT(V[m]); V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);

Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23