LDUR (SIMD&FP) -- A64

LDUR (SIMD&FP)

Load SIMD&FP Register (unscaled offset). This instruction loads a SIMD&FP register from memory. The address that is used for the load is calculated from a base register value and an optional immediate offset.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
size		1	1	1	1	0	0	x	1	0	imm9									0	0	Rn					Rt
								opc

8-bit (size == 00 && opc == 01)

LDUR <Bt>, [<Xn|SP>{, #<simm>}] // (PSTATE.C64 == '0')

LDUR <Bt>, [<Cn|CSP>{, #<simm>}] // (PSTATE.C64 == '1')

16-bit (size == 01 && opc == 01)

LDUR <Ht>, [<Xn|SP>{, #<simm>}] // (PSTATE.C64 == '0')

LDUR <Ht>, [<Cn|CSP>{, #<simm>}] // (PSTATE.C64 == '1')

32-bit (size == 10 && opc == 01)

LDUR <St>, [<Xn|SP>{, #<simm>}] // (PSTATE.C64 == '0')

LDUR <St>, [<Cn|CSP>{, #<simm>}] // (PSTATE.C64 == '1')

64-bit (size == 11 && opc == 01)

LDUR <Dt>, [<Xn|SP>{, #<simm>}] // (PSTATE.C64 == '0')

LDUR <Dt>, [<Cn|CSP>{, #<simm>}] // (PSTATE.C64 == '1')

128-bit (size == 00 && opc == 11)

LDUR <Qt>, [<Xn|SP>{, #<simm>}] // (PSTATE.C64 == '0')

LDUR <Qt>, [<Cn|CSP>{, #<simm>}] // (PSTATE.C64 == '1')

boolean wback = FALSE; boolean postindex = FALSE; integer scale = UInt(opc<1>:size); if scale > 4 then UNDEFINED; bits(64) offset = SignExtend(imm9, 64);

Assembler Symbols

<Bt>	Is the 8-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<Dt>	Is the 64-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<Ht>	Is the 16-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<Qt>	Is the 128-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<St>	Is the 32-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Cn|CSP>

Is the name of the capability register or capability stack pointer holding the base address, encoded in the "Rn" field.

<simm>

Is the optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.

Shared Decode

integer n = UInt(Rn); integer t = UInt(Rt); AccType acctype = AccType_VEC; MemOp memop = if opc<0> == '1' then MemOp_LOAD else MemOp_STORE; integer datasize = 8 << scale;

Operation

CheckFPAdvSIMDEnabled64(); bits(64) address; bits(datasize) data; VirtualAddress base; base = BaseReg[n]; address = VAddress(base); if ! postindex then address = address + offset; case memop of when MemOp_STORE VACheckAddress(base, address, datasize DIV 8, CAP_PERM_STORE, acctype); data = V[t]; Mem[address, datasize DIV 8, acctype] = data; when MemOp_LOAD VACheckAddress(base, address, datasize DIV 8, CAP_PERM_LOAD, acctype); data = Mem[address, datasize DIV 8, acctype]; V[t] = data; if wback then base = VAAdd(base,offset); BaseReg[n] = base;

Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23