LDARB

Load-Acquire Register Byte via alternate base determines the base register to be used, derives an address from the base register and an offset register, loads a byte from memory, zero-extends it, and writes the result to the destination register. The base register used by this operation depends on PSTATE.C64: if PSTATE.C64 is 1, the base register is a 64-bit general-purpose register; if PSTATE.C64 is 0, the base register is a capability general-purpose register. This instruction loads from memory with acquire semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release. For information about memory accesses, see Load/Store addressing modes.

313029282726252423222120191817161514131211109876543210
0100001001111111011111RnRt
L

LDARB <Wt>, [<Cn|CSP>] // (PSTATE.C64 == '0')

LDARB <Wt>, [<Xn|SP>] // (PSTATE.C64 == '1')

integer t = UInt(Rt); integer n = UInt(Rn); datasize=8; regsize=32; AccType acctype = AccType_ORDERED;

Assembler Symbols

<Wt>

Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Cn|CSP>

Is the capability name of the base register or stack pointer, encoded in the "Rn" field.

Operation

CheckCapabilitiesEnabled(); VirtualAddress address; base = AltBaseReg[n]; bits(64) addr = VAddress(base); VACheckAddress(base, addr, datasize DIV 8, CAP_PERM_LOAD, acctype); bits(datasize) data = Mem[addr, datasize DIV 8, acctype]; X[t] = ZeroExtend(data,regsize);


Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23

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