LDNP

Load Pair of capabilities, with non-temporal hint determines the base register to be used, derives an address from the base register and an immediate offset, loads two capabilities from memory, and writes them to two Capability registers. The address to use is derived from a base register value in A64 or capability base register in C64 and a immediate offset scaled by 16. For information about Non-temporal pair instructions, see Load/Store Non-temporal pair. For information about memory accesses, see Load/Store addressing modes.

LDNP <Ct>, <Ct2>, [<Xn|SP>, #<imm>] // (PSTATE.C64 == '0')

LDNP <Ct>, <Ct2>, [<Cn|CSP>, #<imm>] // (PSTATE.C64 == '1')

integer t = UInt(Ct); integer t2 = UInt(Ct2); integer n = UInt(Rn); AccType acctype = AccType_STREAM; bits(64) offset = SignExtend(imm7:'0000', 64);

Assembler Symbols

<Ct>	Is the capability name of the transfer register, encoded in the "Ct" field.

<Ct2>

Is the capability name of the second transfer register, encoded in the "Ct2" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Cn|CSP>

Is the capability name of the base register or stack pointer, encoded in the "Rn" field.

<imm>

Is the signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, encoded in the "imm7" field.

Operation

CheckCapabilitiesEnabled(); VirtualAddress base; boolean rt_unknown = FALSE; if t == t2 then Constraint c = ConstrainUnpredictable(Unpredictable_LDPOVERLAP); assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_UNKNOWN rt_unknown = TRUE; // result is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP EndOfInstruction(); base = BaseReg[n]; bits(64) addr = VAddress(base) + offset; VACheckAddress(base, addr, CAPABILITY_DBYTES*2, CAP_PERM_LOAD, acctype); Capability data1 = MemC[addr, acctype]; Capability data2 = MemC[addr + CAPABILITY_DBYTES, acctype]; if rt_unknown then C[t] = Capability UNKNOWN; C[t2] = Capability UNKNOWN; else C[t] = CapSquashPostLoadCap(data1, base); C[t2] = CapSquashPostLoadCap(data2, base);

Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	0	0	0	1	0	0	1	imm7							Ct2					Rn					Ct
									L