CAS

Compare and Swap capabilities in memory determines the base register to be used, derives an address from the base register, atomically loads a Capability register from the calculated address in memory, and performs a comparison between this first Capability register with a second Capability register. If the result of the comparison is equal, the second Capability register is atomically stored to the calculated address in memory.

CAS <Cs>, <Ct>, [<Xn|SP>] // (PSTATE.C64 == '0')

CAS <Cs>, <Ct>, [<Cn|CSP>] // (PSTATE.C64 == '1')

AccType ldacctype = AccType_ATOMICRW; AccType stacctype = AccType_ATOMICRW; integer t = UInt(Ct); integer s = UInt(Cs); integer n = UInt(Rn);

Assembler Symbols

<Cs>	Is the capability name of the register to be compared and loaded, encoded in the "Cs" field.

<Ct>	Is the capability name of the register to be conditionally stored, encoded in the "Ct" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Cn|CSP>

Is the capability name of the base register or stack pointer, encoded in the "Rn" field.

Operation

CheckCapabilitiesEnabled(); VirtualAddress base; Capability comparecap; Capability newcap; Capability data; comparecap = C[s]; newcap = C[t]; base = BaseReg[n]; bits(64) addr = VAddress(base); VACheckAddress(base, addr, CAPABILITY_DBYTES, CAP_PERM_LOAD, ldacctype); bits(64) cap_required = CAP_PERM_STORE; if CapIsTagSet(newcap) then cap_required = cap_required OR CAP_PERM_STORE_CAP; if CapIsLocal(newcap) then cap_required = cap_required OR CAP_PERM_STORE_LOCAL; VACheckAddress(base, addr, CAPABILITY_DBYTES, cap_required, stacctype); // Both the original VirtualAddress and 64 bit address are passed in // order to be able to squash permissions and tags correctly. C[s] = MemAtomicCompareAndSwapC(base,addr,comparecap,newcap,ldacctype,stacctype);

Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	0	1	0	0	0	1	0	1	0	1	Cs					0	1	1	1	1	1	Rn					Ct
									L							R

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	0	1	0	0	0	1	0	1	0	1	Cs					0	1	1	1	1	1	Rn					Ct
									L							R

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	0	1	0	0	0	1	0	1	0	1	Cs					0	1	1	1	1	1	Rn					Ct
									L							R

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	0	1	0	0	0	1	0	1	0	1	Cs					0	1	1	1	1	1	Rn					Ct
									L							R