SUBS (shifted register) -- A64

Subtract (shifted register), setting flags, subtracts an optionally-shifted register value from a register value, and writes the result to the destination register. It updates the condition flags based on the result.

integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); integer datasize = if sf == '1' then 64 else 32; boolean sub_op = (op == '1'); boolean setflags = (S == '1'); if shift == '11' then UNDEFINED; if sf == '0' && imm6<5> == '1' then UNDEFINED; ShiftType shift_type = DecodeShift(shift); integer shift_amount = UInt(imm6);

Assembler Symbols

<Wd>	Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Wn>	Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field.

<Wm>	Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field.

<Xd>	Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Xn>	Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field.

<Xm>	Is the 64-bit name of the second general-purpose source register, encoded in the "Rm" field.

<shift>

Is the optional shift type to be applied to the second source operand, defaulting to LSL and encoded in shift:

shift	<shift>
00	LSL
01	LSR
10	ASR
11	RESERVED

<amount>	For the 32-bit variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.
	For the 64-bit variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field.

Alias Conditions

Alias	Is preferred when
CMP (shifted register)	Rd == '11111'
NEGS	Rn == '11111' && Rd != '11111'

Operation

bits(datasize) result; bits(datasize) operand1 = X[n]; bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount); bits(4) nzcv; bit carry_in; if sub_op then operand2 = NOT(operand2); carry_in = '1'; else carry_in = '0'; (result, nzcv) = AddWithCarry(operand1, operand2, carry_in); if setflags then PSTATE.<N,Z,C,V> = nzcv; X[d] = result;

Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23