DUP (element) -- A64

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Scalar

integer d = UInt(Rd); integer n = UInt(Rn); integer size = LowestSetBit(imm5); if size > 3 then UNDEFINED; integer index = UInt(imm5<4:size+1>); integer idxdsize = if imm5<4> == '1' then 128 else 64; integer esize = 8 << size; integer datasize = esize; integer elements = 1;

Vector

integer d = UInt(Rd); integer n = UInt(Rn); integer size = LowestSetBit(imm5); if size > 3 then UNDEFINED; integer index = UInt(imm5<4:size+1>); integer idxdsize = if imm5<4> == '1' then 128 else 64; if size == 3 && Q == '0' then UNDEFINED; integer esize = 8 << size; integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize;

Assembler Symbols

<T>

For the scalar variant: is the element width specifier, encoded in imm5:

imm5	<T>
x0000	RESERVED
xxxx1	B
xxx10	H
xx100	S
x1000	D

For the vector variant: is an arrangement specifier, encoded in imm5:Q:

imm5	Q	<T>
x0000	x	RESERVED
xxxx1	0	8B
xxxx1	1	16B
xxx10	0	4H
xxx10	1	8H
xx100	0	2S
xx100	1	4S
x1000	0	RESERVED
x1000	1	2D

<Ts>

Is an element size specifier, encoded in imm5:

imm5	<Ts>
x0000	RESERVED
xxxx1	B
xxx10	H
xx100	S
x1000	D

<V>

Is the destination width specifier, encoded in imm5:

imm5	<V>
x0000	RESERVED
xxxx1	B
xxx10	H
xx100	S
x1000	D

<Vn>	Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<index>

Is the element index encoded in imm5:

imm5	<index>
x0000	RESERVED
xxxx1	imm5<4:1>
xxx10	imm5<4:2>
xx100	imm5<4:3>
x1000	imm5<4>

<d>	Is the number of the SIMD&FP destination register, encoded in the "Rd" field.

<Vd>	Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

Operation

CheckFPAdvSIMDEnabled64(); bits(idxdsize) operand = V[n]; bits(datasize) result; bits(esize) element; element = Elem[operand, index, esize]; for e = 0 to elements-1 Elem[result, e, esize] = element; V[d] = result;

Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23