Store capability tags stores four Capability Tags to memory. The address that is used for the store is calculated from a base register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | Rn | Rt | ||||||||
| opc<1> | opc<0> | ||||||||||||||||||||||||||||||
integer t = UInt(Rt); integer n = UInt(Rn);
| <Xt> |
Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Cn|CSP> |
Is the capability name of the base register or stack pointer, encoded in the "Rn" field. |
if PSTATE.EL == EL0 then UNDEFINED; CheckCapabilitiesEnabled(); VirtualAddress base = BaseReg[n]; integer count = 4; boolean willabort = FALSE; boolean iswrite; boolean secondstage; bits(64) data = X[t]; bits(64) addr = VAddress(base); if addr != Align(addr, CAPABILITY_DBYTES*count) then iswrite = TRUE; secondstage = FALSE; willabort = TRUE; for i = 0 to count-1 bits(1) tag; if CapIsSystemAccessEnabled() && !IsTagSettingDisabled() then tag = data<i>; else tag = '0'; bits(64) cap_required = CAP_PERM_STORE; if tag == '1' then cap_required = cap_required OR CAP_PERM_STORE_CAP; VACheckAddress(base, addr, CAPABILITY_DBYTES, cap_required, AccType_NORMAL); if willabort == TRUE then AArch64.Abort(addr, AArch64.AlignmentFault(AccType_NORMAL, iswrite, secondstage)); AArch64.CapabilityTag[addr, AccType_NORMAL] = tag; addr = addr + CAPABILITY_DBYTES;
Internal version only: isa v32.13, AdvSIMD v29.04, pseudocode morello-2022-01_rc2, capabilities morello-2022-01_rc2 ; Build timestamp: 2022-01-11T11:23
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