Base Instructions
SIMD&FP Instructions
SVE Instructions
SME Instructions
Index by Encoding
Shared Pseudocode
Proprietary Notice

A64 instruction set encoding

313029282726252423222120191817161514131211109876543210
op0op1
Decode fieldsInstruction details
op0op1
0 0000 Reserved
1 0000 SME encodings
0010 SVE encodings
00x1 UNALLOCATED
100x Data Processing -- Immediate
101x Branches, Exception Generating and System instructions
x101 Data Processing -- Register
x111 Data Processing -- Scalar Floating-Point and Advanced SIMD
x1x0 Loads and Stores

Reserved

The encodings in this section are decoded from A64 instruction set encoding.

313029282726252423222120191817161514131211109876543210
0op00000op1
Decode fieldsInstruction details
op0op1
00 000000000 UDF
00 != 000000000 UNALLOCATED
!= 00 UNALLOCATED

SME encodings

The encodings in this section are decoded from A64 instruction set encoding.

313029282726252423222120191817161514131211109876543210
1op00000op1op2
Decode fieldsInstruction details
op0op1op2
00 x00xxxxx0x00000 0xx0xx SME2 Quarter Tile Outer Product - 16-bit and 32-bit
00 x00xxxxx0x00000 1xx0xx UNALLOCATED
00 x00xxxxx0x00001 xxx0xx UNALLOCATED
00 x00xxxxx0x0001x xxx0xx UNALLOCATED
00 x00xxxxx0x001xx xxx0xx UNALLOCATED
00 x00xxxxx0x01xxx xxx0xx UNALLOCATED
00 x00xxxxx1x0xxxx xxx0xx UNALLOCATED
00 x01xxxxxxx0xxxx xxx0xx SME2 Sparse Outer Product
00 x0xxxxxxxx0xxxx xxx1xx UNALLOCATED
00 x0xxxxxxxx1xxxx UNALLOCATED
00 x10xxxxxxxxxxxx xx00xx SME FP Outer Product - 32 bit
00 x10xxxxxxxxxxxx xx10xx SME2 Outer Product - Misc
01 00xxxxxxxxxxxxx SME2 Multi-vector - Memory (Contiguous)
01 10xxxxxxxxxxxxx SME2 Multi-vector - Memory (Strided)
01 x10xxxxxxxxxxxx xxx0xx SME Integer Outer Product - 32 bit
0x x10xxxxxxxxxxxx xxx1xx UNALLOCATED
0x x11xxxxx0000000 0x1xxx SME2 Quarter Tile Outer Product - 64-bit
0x x11xxxxx0000000 1x1xxx UNALLOCATED
0x x11xxxxx0000001 xx1xxx UNALLOCATED
0x x11xxxxx000001x xx1xxx UNALLOCATED
0x x11xxxxx00001xx xx1xxx UNALLOCATED
0x x11xxxxx0001xxx xx1xxx UNALLOCATED
0x x11xxxxx001xxxx xx1xxx UNALLOCATED
0x x11xxxxx01xxxxx xx1xxx UNALLOCATED
0x x11xxxxx1xxxxxx xx1xxx UNALLOCATED
0x x11xxxxxxxxxxxx xx0xxx SME Outer Product - 64 bit
10 0000010xxxxxxxx SME zero array
10 0000011xxxxxxxx SME2 Multiple Zero
10 0010010xxxxxxxx SME2 zero lookup table
10 0010011xxxxxxxx SME2 Move Lookup Table
10 00x011xxxxxxxxx UNALLOCATED
10 010011xxxxxxxxx SME2 Expand Lookup Table (Non-contiguous)
10 011011xxxxxxxxx UNALLOCATED
10 01x001xxxxxxxxx SME2 Expand Lookup Table (Contiguous)
10 0xx000x0xxxxxxx x0xxxx SME Move into Array
10 0xx000x0xxxxxxx x1xxxx UNALLOCATED
10 0xx000x1xxxxxxx SME Move from Array
10 0xx010xxxxxxxxx xx0xxx SME Add Vector to Array
10 0xx010xxxxxxxxx xx1xxx UNALLOCATED
10 0xx1xxxxxxxxxxx UNALLOCATED
10 10x10xxxx0xxxxx SME2 Multi-vector - Multiple and Single Array Vectors (Two registers)
10 10x11xxxx0xxxxx SME2 Multi-vector - Multiple and Single Array Vectors (Four registers)
10 11x1xxxx00xxxxx SME2 Multi-vector - Multiple Array Vectors (Two registers)
10 11x1xxxx10xxxxx SME2 Multi-vector - Multiple Array Vectors (Four registers)
10 1xx00xxxxxxxxxx SME2 Multi-vector - Indexed (One register)
10 1xx01xxxx0xxxxx SME2 Multi-vector - Indexed (Two registers)
10 1xx01xxxx1xxxxx SME2 Multi-vector - Indexed (Four registers)
10 1xx10xxxx10100x SME2 Multi-vector - Multiple and Single SVE Destructive (Two registers)
10 1xx10xxxx10101x xxxx0x SME2 Multi-vector - Multiple and Single SVE Destructive (Four registers)
10 1xx10xxxx10101x xxxx1x UNALLOCATED
10 1xx11xxxx1010xx UNALLOCATED
10 1xx1xxx00101110 xxxx0x SME2 Multi-vector - Multiple Vectors SVE Destructive (Four registers)
10 1xx1xxx00101111 xxxx0x SME2 Multi-vector - Multiple Vectors SVE Saturating Multiply (Four registers)
10 1xx1xxx0010111x xxxx1x UNALLOCATED
10 1xx1xxx1010111x UNALLOCATED
10 1xx1xxxx0101100 SME2 Multi-vector - Multiple Vectors SVE Destructive (Two registers)
10 1xx1xxxx0101101 SME2 Multi-vector - Multiple Vectors SVE Saturating Multiply (Two registers)
10 1xx1xxxx01111xx UNALLOCATED
10 1xx1xxxx11x11xx UNALLOCATED
10 1xx1xxxxx100xxx SME2 Multi-vector - SVE Select
10 1xx1xxxxx110xxx SME2 Multi-vector - SVE Constructive Binary
10 1xx1xxxxx111000 SME2 Multi-vector - SVE Constructive Unary
10 1xx1xxxxx111001 0xxxx0 SME2 Multi-vector - FP Multiply
10 1xx1xxxxx111001 0xxxx1 UNALLOCATED
10 1xx1xxxxx111001 1xxxxx UNALLOCATED
10 1xx1xxxxx111010 0xxxx0 SME2 Multiple and Single Vector - FP multiply
10 1xx1xxxxx111010 0xxxx1 UNALLOCATED
10 1xx1xxxxx111010 1xxxxx UNALLOCATED
10 1xx1xxxxx111011 UNALLOCATED
11 SME Memory

SME2 Quarter Tile Outer Product - 16-bit and 32-bit

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
1000000op000op10op2000000op30op4
Decode fieldsInstruction details
op0op1op2op3op4
0 0 0 x0 SME2 FP32 non-widening quarter tile outer product
0 0 0 x1 0 UNALLOCATED
0 1 0 00 SME2 FP8 to FP32 quarter tile outer product
0 1 0 01 0 SME2 FP8 to FP16 quarter tile outer product
0 1 0 10 1 UNALLOCATED
0 1 0 1x 0 UNALLOCATED
1 0 0 x0 SME2 BF16 to FP32 quarter tile outer product
1 0 0 x1 0 SME2 FP16 non-widening quarter tile outer product
1 1 0 x0 SME2 FP16 to FP32 quarter tile outer product
1 1 0 x1 0 SME2 BF16 non-widening quarter tile outer product
0 1 x1 SME2 Int16 to Int32 quarter tile outer product
1 1 x1 UNALLOCATED
0 x1 1 UNALLOCATED
1 x0 SME2 Int8 to Int32 quarter tile outer product

SME2 FP32 non-widening quarter tile outer product

The encodings in this section are decoded from SME2 Quarter Tile Outer Product - 16-bit and 32-bit.

313029282726252423222120191817161514131211109876543210
10000000000MZm0000000NZn0S00ZAda
Decode fields Instruction Details Feature
M N S
0 0 0 FMOP4A (non-widening) — Single-precision, single vectorsFEAT_SME_MOP4
0 0 1 FMOP4S (non-widening) — Single-precision, single vectorsFEAT_SME_MOP4
0 1 0 FMOP4A (non-widening) — Single-precision, multiple and single vectorsFEAT_SME_MOP4
0 1 1 FMOP4S (non-widening) — Single-precision, multiple and single vectorsFEAT_SME_MOP4
1 0 0 FMOP4A (non-widening) — Single-precision, single and multiple vectorsFEAT_SME_MOP4
1 0 1 FMOP4S (non-widening) — Single-precision, single and multiple vectorsFEAT_SME_MOP4
1 1 0 FMOP4A (non-widening) — Single-precision, multiple vectorsFEAT_SME_MOP4
1 1 1 FMOP4S (non-widening) — Single-precision, multiple vectorsFEAT_SME_MOP4

SME2 FP8 to FP32 quarter tile outer product

The encodings in this section are decoded from SME2 Quarter Tile Outer Product - 16-bit and 32-bit.

313029282726252423222120191817161514131211109876543210
10000000001MZm0000000NZn0000ZAda
Decode fields Instruction Details Feature
M N
0 0 FMOP4A (widening, 4-way) — Single vectorsFEAT_SME_MOP4 && FEAT_SME_F8F32
0 1 FMOP4A (widening, 4-way) — Multiple and single vectorsFEAT_SME_MOP4 && FEAT_SME_F8F32
1 0 FMOP4A (widening, 4-way) — Single and multiple vectorsFEAT_SME_MOP4 && FEAT_SME_F8F32
1 1 FMOP4A (widening, 4-way) — Multiple vectorsFEAT_SME_MOP4 && FEAT_SME_F8F32

SME2 FP8 to FP16 quarter tile outer product

The encodings in this section are decoded from SME2 Quarter Tile Outer Product - 16-bit and 32-bit.

313029282726252423222120191817161514131211109876543210
10000000001MZm0000000NZn00100ZA
Decode fields Instruction Details Feature
M N
0 0 FMOP4A (widening, 2-way, FP8 to FP16) — Single vectorsFEAT_SME_MOP4 && FEAT_SME_F8F16
0 1 FMOP4A (widening, 2-way, FP8 to FP16) — Multiple and single vectorsFEAT_SME_MOP4 && FEAT_SME_F8F16
1 0 FMOP4A (widening, 2-way, FP8 to FP16) — Single and multiple vectorsFEAT_SME_MOP4 && FEAT_SME_F8F16
1 1 FMOP4A (widening, 2-way, FP8 to FP16) — Multiple vectorsFEAT_SME_MOP4 && FEAT_SME_F8F16

SME2 BF16 to FP32 quarter tile outer product

The encodings in this section are decoded from SME2 Quarter Tile Outer Product - 16-bit and 32-bit.

313029282726252423222120191817161514131211109876543210
10000001000MZm0000000NZn0S00ZAda
Decode fields Instruction Details Feature
M N S
0 0 0 BFMOP4A (widening) — Single vectorsFEAT_SME_MOP4
0 0 1 BFMOP4S (widening) — Single vectorsFEAT_SME_MOP4
0 1 0 BFMOP4A (widening) — Multiple and single vectorsFEAT_SME_MOP4
0 1 1 BFMOP4S (widening) — Multiple and single vectorsFEAT_SME_MOP4
1 0 0 BFMOP4A (widening) — Single and multiple vectorsFEAT_SME_MOP4
1 0 1 BFMOP4S (widening) — Single and multiple vectorsFEAT_SME_MOP4
1 1 0 BFMOP4A (widening) — Multiple vectorsFEAT_SME_MOP4
1 1 1 BFMOP4S (widening) — Multiple vectorsFEAT_SME_MOP4

SME2 FP16 non-widening quarter tile outer product

The encodings in this section are decoded from SME2 Quarter Tile Outer Product - 16-bit and 32-bit.

313029282726252423222120191817161514131211109876543210
10000001000MZm0000000NZn0S100ZA
Decode fields Instruction Details Feature
M N S
0 0 0 FMOP4A (non-widening) — Half-precision, single vectorsFEAT_SME_MOP4 && FEAT_SME_F16F16
0 0 1 FMOP4S (non-widening) — Half-precision, single vectorsFEAT_SME_MOP4 && FEAT_SME_F16F16
0 1 0 FMOP4A (non-widening) — Half-precision, multiple and single vectorsFEAT_SME_MOP4 && FEAT_SME_F16F16
0 1 1 FMOP4S (non-widening) — Half-precision, multiple and single vectorsFEAT_SME_MOP4 && FEAT_SME_F16F16
1 0 0 FMOP4A (non-widening) — Half-precision, single and multiple vectorsFEAT_SME_MOP4 && FEAT_SME_F16F16
1 0 1 FMOP4S (non-widening) — Half-precision, single and multiple vectorsFEAT_SME_MOP4 && FEAT_SME_F16F16
1 1 0 FMOP4A (non-widening) — Half-precision, multiple vectorsFEAT_SME_MOP4 && FEAT_SME_F16F16
1 1 1 FMOP4S (non-widening) — Half-precision, multiple vectorsFEAT_SME_MOP4 && FEAT_SME_F16F16

SME2 FP16 to FP32 quarter tile outer product

The encodings in this section are decoded from SME2 Quarter Tile Outer Product - 16-bit and 32-bit.

313029282726252423222120191817161514131211109876543210
10000001001MZm0000000NZn0S00ZAda
Decode fields Instruction Details Feature
M N S
0 0 0 FMOP4A (widening, 2-way, FP16 to FP32) — Single vectorsFEAT_SME_MOP4
0 0 1 FMOP4S (widening) — Single vectorsFEAT_SME_MOP4
0 1 0 FMOP4A (widening, 2-way, FP16 to FP32) — Multiple and single vectorsFEAT_SME_MOP4
0 1 1 FMOP4S (widening) — Multiple and single vectorsFEAT_SME_MOP4
1 0 0 FMOP4A (widening, 2-way, FP16 to FP32) — Single and multiple vectorsFEAT_SME_MOP4
1 0 1 FMOP4S (widening) — Single and multiple vectorsFEAT_SME_MOP4
1 1 0 FMOP4A (widening, 2-way, FP16 to FP32) — Multiple vectorsFEAT_SME_MOP4
1 1 1 FMOP4S (widening) — Multiple vectorsFEAT_SME_MOP4

SME2 BF16 non-widening quarter tile outer product

The encodings in this section are decoded from SME2 Quarter Tile Outer Product - 16-bit and 32-bit.

313029282726252423222120191817161514131211109876543210
10000001001MZm0000000NZn0S100ZA
Decode fields Instruction Details Feature
M N S
0 0 0 BFMOP4A (non-widening) — Single vectorsFEAT_SME_MOP4 && FEAT_SME_B16B16
0 0 1 BFMOP4S (non-widening) — Single vectorsFEAT_SME_MOP4 && FEAT_SME_B16B16
0 1 0 BFMOP4A (non-widening) — Multiple and single vectorsFEAT_SME_MOP4 && FEAT_SME_B16B16
0 1 1 BFMOP4S (non-widening) — Multiple and single vectorsFEAT_SME_MOP4 && FEAT_SME_B16B16
1 0 0 BFMOP4A (non-widening) — Single and multiple vectorsFEAT_SME_MOP4 && FEAT_SME_B16B16
1 0 1 BFMOP4S (non-widening) — Single and multiple vectorsFEAT_SME_MOP4 && FEAT_SME_B16B16
1 1 0 BFMOP4A (non-widening) — Multiple vectorsFEAT_SME_MOP4 && FEAT_SME_B16B16
1 1 1 BFMOP4S (non-widening) — Multiple vectorsFEAT_SME_MOP4 && FEAT_SME_B16B16

SME2 Int16 to Int32 quarter tile outer product

The encodings in this section are decoded from SME2 Quarter Tile Outer Product - 16-bit and 32-bit.

313029282726252423222120191817161514131211109876543210
1000000u0000MZm0100000NZn0S10ZAda
Decode fields Instruction Details Feature
u0 M N S
0 0 0 0 SMOP4A (2-way) — Single vectorsFEAT_SME_MOP4
0 0 0 1 SMOP4S (2-way) — Single vectorsFEAT_SME_MOP4
0 0 1 0 SMOP4A (2-way) — Multiple and single vectorsFEAT_SME_MOP4
0 0 1 1 SMOP4S (2-way) — Multiple and single vectorsFEAT_SME_MOP4
0 1 0 0 SMOP4A (2-way) — Single and multiple vectorsFEAT_SME_MOP4
0 1 0 1 SMOP4S (2-way) — Single and multiple vectorsFEAT_SME_MOP4
0 1 1 0 SMOP4A (2-way) — Multiple vectorsFEAT_SME_MOP4
0 1 1 1 SMOP4S (2-way) — Multiple vectorsFEAT_SME_MOP4
1 0 0 0 UMOP4A (2-way) — Single vectorsFEAT_SME_MOP4
1 0 0 1 UMOP4S (2-way) — Single vectorsFEAT_SME_MOP4
1 0 1 0 UMOP4A (2-way) — Multiple and single vectorsFEAT_SME_MOP4
1 0 1 1 UMOP4S (2-way) — Multiple and single vectorsFEAT_SME_MOP4
1 1 0 0 UMOP4A (2-way) — Single and multiple vectorsFEAT_SME_MOP4
1 1 0 1 UMOP4S (2-way) — Single and multiple vectorsFEAT_SME_MOP4
1 1 1 0 UMOP4A (2-way) — Multiple vectorsFEAT_SME_MOP4
1 1 1 1 UMOP4S (2-way) — Multiple vectorsFEAT_SME_MOP4

SME2 Int8 to Int32 quarter tile outer product

The encodings in this section are decoded from SME2 Quarter Tile Outer Product - 16-bit and 32-bit.

313029282726252423222120191817161514131211109876543210
1000000u000u1MZm0100000NZn0S00ZAda
Decode fields Instruction Details Feature
u0 u1 M N S
0 0 0 0 0 SMOP4A (4-way) — 32-bit, single vectorsFEAT_SME_MOP4
0 0 0 0 1 SMOP4S (4-way) — 32-bit, single vectorsFEAT_SME_MOP4
0 0 0 1 0 SMOP4A (4-way) — 32-bit, multiple and single vectorsFEAT_SME_MOP4
0 0 0 1 1 SMOP4S (4-way) — 32-bit, multiple and single vectorsFEAT_SME_MOP4
0 0 1 0 0 SMOP4A (4-way) — 32-bit, single and multiple vectorsFEAT_SME_MOP4
0 0 1 0 1 SMOP4S (4-way) — 32-bit, single and multiple vectorsFEAT_SME_MOP4
0 0 1 1 0 SMOP4A (4-way) — 32-bit, multiple vectorsFEAT_SME_MOP4
0 0 1 1 1 SMOP4S (4-way) — 32-bit, multiple vectorsFEAT_SME_MOP4
0 1 0 0 0 SUMOP4A — 32-bit, single vectorsFEAT_SME_MOP4
0 1 0 0 1 SUMOP4S — 32-bit, single vectorsFEAT_SME_MOP4
0 1 0 1 0 SUMOP4A — 32-bit, multiple and single vectorsFEAT_SME_MOP4
0 1 0 1 1 SUMOP4S — 32-bit, multiple and single vectorsFEAT_SME_MOP4
0 1 1 0 0 SUMOP4A — 32-bit, single and multiple vectorsFEAT_SME_MOP4
0 1 1 0 1 SUMOP4S — 32-bit, single and multiple vectorsFEAT_SME_MOP4
0 1 1 1 0 SUMOP4A — 32-bit, multiple vectorsFEAT_SME_MOP4
0 1 1 1 1 SUMOP4S — 32-bit, multiple vectorsFEAT_SME_MOP4
1 0 0 0 0 USMOP4A — 32-bit, single vectorsFEAT_SME_MOP4
1 0 0 0 1 USMOP4S — 32-bit, single vectorsFEAT_SME_MOP4
1 0 0 1 0 USMOP4A — 32-bit, multiple and single vectorsFEAT_SME_MOP4
1 0 0 1 1 USMOP4S — 32-bit, multiple and single vectorsFEAT_SME_MOP4
1 0 1 0 0 USMOP4A — 32-bit, single and multiple vectorsFEAT_SME_MOP4
1 0 1 0 1 USMOP4S — 32-bit, single and multiple vectorsFEAT_SME_MOP4
1 0 1 1 0 USMOP4A — 32-bit, multiple vectorsFEAT_SME_MOP4
1 0 1 1 1 USMOP4S — 32-bit, multiple vectorsFEAT_SME_MOP4
1 1 0 0 0 UMOP4A (4-way) — 32-bit, single vectorsFEAT_SME_MOP4
1 1 0 0 1 UMOP4S (4-way) — 32-bit, single vectorsFEAT_SME_MOP4
1 1 0 1 0 UMOP4A (4-way) — 32-bit, multiple and single vectorsFEAT_SME_MOP4
1 1 0 1 1 UMOP4S (4-way) — 32-bit, multiple and single vectorsFEAT_SME_MOP4
1 1 1 0 0 UMOP4A (4-way) — 32-bit, single and multiple vectorsFEAT_SME_MOP4
1 1 1 0 1 UMOP4S (4-way) — 32-bit, single and multiple vectorsFEAT_SME_MOP4
1 1 1 1 0 UMOP4A (4-way) — 32-bit, multiple vectorsFEAT_SME_MOP4
1 1 1 1 1 UMOP4S (4-way) — 32-bit, multiple vectorsFEAT_SME_MOP4

SME2 Sparse Outer Product

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
1000000op001op1op20op3op40op5
Decode fieldsInstruction detailsFeature
op0op1op2op3op4op5
0 0 0 0 0 FTMOPA (non-widening) — Single-precisionFEAT_SME_TMOP
0 0 0 0 1 0 UNALLOCATED-
0 1 0 0 0 FTMOPA (widening, 4-way)FEAT_SME_TMOP && FEAT_SME_F8F32
0 1 0 0 1 0 FTMOPA (widening, 2-way, FP8 to FP16)FEAT_SME_TMOP && FEAT_SME_F8F16
1 0 0 0 0 BFTMOPA (widening)FEAT_SME_TMOP
1 0 0 0 1 0 FTMOPA (non-widening) — Half-precisionFEAT_SME_TMOP && FEAT_SME_F16F16
1 1 0 0 0 FTMOPA (widening, 2-way, FP16 to FP32)FEAT_SME_TMOP
1 1 0 0 1 0 BFTMOPA (non-widening)FEAT_SME_TMOP && FEAT_SME_B16B16
0 1 0 1 SME2 Int16 to Int32 sparse outer product-
1 1 0 1 UNALLOCATED-
0 0 1 1 UNALLOCATED-
1 0 0 SME Int8 to Int32 sparse outer product-
1 UNALLOCATED-

SME2 Int16 to Int32 sparse outer product

The encodings in this section are decoded from SME2 Sparse Outer Product.

313029282726252423222120191817161514131211109876543210
1000000u0010Zm100KZkZni210ZAda
Decode fields Instruction Details Feature
u0
0 STMOPA (2-way)FEAT_SME_TMOP
1 UTMOPA (2-way)FEAT_SME_TMOP

SME Int8 to Int32 sparse outer product

The encodings in this section are decoded from SME2 Sparse Outer Product.

313029282726252423222120191817161514131211109876543210
1000000u001u1Zm100KZkZni200ZAda
Decode fields Instruction Details Feature
u0 u1
0 0 STMOPA (4-way)FEAT_SME_TMOP
0 1 SUTMOPAFEAT_SME_TMOP
1 0 USTMOPAFEAT_SME_TMOP
1 1 UTMOPA (4-way)FEAT_SME_TMOP

SME FP Outer Product - 32 bit

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
1000000op010op1op200
Decode fieldsInstruction detailsFeature
op0op1op2
0 0 SME FP32 outer product-
0 1 0 FMOPA (widening, 4-way)FEAT_SME_F8F32
0 1 1 UNALLOCATED-
1 0 SME BF16 widening outer product-
1 1 SME FP16 widening outer product-

SME FP32 outer product

The encodings in this section are decoded from SME FP Outer Product - 32 bit.

313029282726252423222120191817161514131211109876543210
10000000100ZmPmPnZnS00ZAda
Decode fields Instruction Details Feature
S
0 FMOPA (non-widening)FEAT_SME
1 FMOPS (non-widening)FEAT_SME

SME BF16 widening outer product

The encodings in this section are decoded from SME FP Outer Product - 32 bit.

313029282726252423222120191817161514131211109876543210
10000001100ZmPmPnZnS00ZAda
Decode fields Instruction Details Feature
S
0 BFMOPA (widening)FEAT_SME
1 BFMOPS (widening)FEAT_SME

SME FP16 widening outer product

The encodings in this section are decoded from SME FP Outer Product - 32 bit.

313029282726252423222120191817161514131211109876543210
10000001101ZmPmPnZnS00ZAda
Decode fields Instruction Details Feature
S
0 FMOPA (widening, 2-way, FP16 to FP32)FEAT_SME
1 FMOPS (widening)FEAT_SME

SME2 Outer Product - Misc

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
1000000op010op1op210op3
Decode fieldsInstruction detailsFeature
op0op1op2op3
0 0 SME2 32-bit binary outer product-
0 1 0 0 FMOPA (widening, 2-way, FP8 to FP16)FEAT_SME_F8F16
0 1 1 0 UNALLOCATED-
0 1 1 UNALLOCATED-
1 0 0 SME2 FP16 non-widening outer product-
1 1 0 SME2 BF16 non-widening outer product-
1 1 UNALLOCATED-

SME2 32-bit binary outer product

The encodings in this section are decoded from SME2 Outer Product - Misc.

313029282726252423222120191817161514131211109876543210
10000000100ZmPmPnZnS10ZAda
Decode fields Instruction Details Feature
S
0 BMOPAFEAT_SME2
1 BMOPSFEAT_SME2

SME2 FP16 non-widening outer product

The encodings in this section are decoded from SME2 Outer Product - Misc.

313029282726252423222120191817161514131211109876543210
10000001100ZmPmPnZnS100ZAda
Decode fields Instruction Details Feature
S
0 FMOPA (non-widening)FEAT_SME_F16F16
1 FMOPS (non-widening)FEAT_SME_F16F16

SME2 BF16 non-widening outer product

The encodings in this section are decoded from SME2 Outer Product - Misc.

313029282726252423222120191817161514131211109876543210
10000001101ZmPmPnZnS100ZAda
Decode fields Instruction Details Feature
S
0 BFMOPA (non-widening)FEAT_SME_B16B16
1 BFMOPS (non-widening)FEAT_SME_B16B16

SME2 Multi-vector - Memory (Contiguous)

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
101000000op0op1op2
Decode fieldsInstruction details
op0op1op2
00x 0 SME2 multi-vec contiguous load (scalar plus scalar, two registers)
00x 1 0 SME2 multi-vec contiguous load (scalar plus scalar, four registers)
01x 0 SME2 multi-vec contiguous store (scalar plus scalar, two registers)
01x 1 0 SME2 multi-vec contiguous store (scalar plus scalar, four registers)
0x1 1 1 UNALLOCATED
100 0 SME2 multi-vec contiguous load (scalar plus immediate, two registers)
100 1 0 SME2 multi-vec contiguous load (scalar plus immediate, four registers)
110 0 SME2 multi-vec contiguous store (scalar plus immediate, two registers)
110 1 0 SME2 multi-vec contiguous store (scalar plus immediate, four registers)
1x1 UNALLOCATED
xx0 1 1 UNALLOCATED

SME2 multi-vec contiguous load (scalar plus scalar, two registers)

The encodings in this section are decoded from SME2 Multi-vector - Memory (Contiguous).

313029282726252423222120191817161514131211109876543210
10100000000Rm0mszPNgRnZtN
Decode fields Instruction Details Feature
msz N
00 0 LD1B (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
00 1 LDNT1B (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
01 0 LD1H (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
01 1 LDNT1H (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
10 0 LD1W (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
10 1 LDNT1W (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
11 0 LD1D (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
11 1 LDNT1D (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1

SME2 multi-vec contiguous load (scalar plus scalar, four registers)

The encodings in this section are decoded from SME2 Multi-vector - Memory (Contiguous).

313029282726252423222120191817161514131211109876543210
10100000000Rm1mszPNgRnZt0N
Decode fields Instruction Details Feature
msz N
00 0 LD1B (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
00 1 LDNT1B (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
01 0 LD1H (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
01 1 LDNT1H (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
10 0 LD1W (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
10 1 LDNT1W (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
11 0 LD1D (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
11 1 LDNT1D (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1

SME2 multi-vec contiguous store (scalar plus scalar, two registers)

The encodings in this section are decoded from SME2 Multi-vector - Memory (Contiguous).

313029282726252423222120191817161514131211109876543210
10100000001Rm0mszPNgRnZtN
Decode fields Instruction Details Feature
msz N
00 0 ST1B (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
00 1 STNT1B (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
01 0 ST1H (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
01 1 STNT1H (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
10 0 ST1W (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
10 1 STNT1W (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
11 0 ST1D (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
11 1 STNT1D (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1

SME2 multi-vec contiguous store (scalar plus scalar, four registers)

The encodings in this section are decoded from SME2 Multi-vector - Memory (Contiguous).

313029282726252423222120191817161514131211109876543210
10100000001Rm1mszPNgRnZt0N
Decode fields Instruction Details Feature
msz N
00 0 ST1B (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
00 1 STNT1B (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
01 0 ST1H (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
01 1 STNT1H (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
10 0 ST1W (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
10 1 STNT1W (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
11 0 ST1D (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
11 1 STNT1D (scalar plus scalar, consecutive registers)FEAT_SME2 || FEAT_SVE2p1

SME2 multi-vec contiguous load (scalar plus immediate, two registers)

The encodings in this section are decoded from SME2 Multi-vector - Memory (Contiguous).

313029282726252423222120191817161514131211109876543210
101000000100imm40mszPNgRnZtN
Decode fields Instruction Details Feature
msz N
00 0 LD1B (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
00 1 LDNT1B (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
01 0 LD1H (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
01 1 LDNT1H (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
10 0 LD1W (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
10 1 LDNT1W (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
11 0 LD1D (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
11 1 LDNT1D (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1

SME2 multi-vec contiguous load (scalar plus immediate, four registers)

The encodings in this section are decoded from SME2 Multi-vector - Memory (Contiguous).

313029282726252423222120191817161514131211109876543210
101000000100imm41mszPNgRnZt0N
Decode fields Instruction Details Feature
msz N
00 0 LD1B (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
00 1 LDNT1B (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
01 0 LD1H (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
01 1 LDNT1H (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
10 0 LD1W (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
10 1 LDNT1W (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
11 0 LD1D (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
11 1 LDNT1D (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1

SME2 multi-vec contiguous store (scalar plus immediate, two registers)

The encodings in this section are decoded from SME2 Multi-vector - Memory (Contiguous).

313029282726252423222120191817161514131211109876543210
101000000110imm40mszPNgRnZtN
Decode fields Instruction Details Feature
msz N
00 0 ST1B (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
00 1 STNT1B (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
01 0 ST1H (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
01 1 STNT1H (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
10 0 ST1W (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
10 1 STNT1W (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
11 0 ST1D (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
11 1 STNT1D (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1

SME2 multi-vec contiguous store (scalar plus immediate, four registers)

The encodings in this section are decoded from SME2 Multi-vector - Memory (Contiguous).

313029282726252423222120191817161514131211109876543210
101000000110imm41mszPNgRnZt0N
Decode fields Instruction Details Feature
msz N
00 0 ST1B (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
00 1 STNT1B (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
01 0 ST1H (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
01 1 STNT1H (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
10 0 ST1W (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
10 1 STNT1W (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
11 0 ST1D (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1
11 1 STNT1D (scalar plus immediate, consecutive registers)FEAT_SME2 || FEAT_SVE2p1

SME2 Multi-vector - Memory (Strided)

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
101000010op0op1op2
Decode fieldsInstruction details
op0op1op2
00x 0 SME2 multi-vec non-contiguous load (scalar plus scalar, two registers)
00x 1 0 SME2 multi-vec non-contiguous load (scalar plus scalar, four registers)
01x 0 SME2 multi-vec non-contiguous store (scalar plus scalar, two registers)
01x 1 0 SME2 multi-vec non-contiguous store (scalar plus scalar, four registers)
0x1 1 1 UNALLOCATED
100 0 SME2 multi-vec non-contiguous load (scalar plus immediate, two registers)
100 1 0 SME2 multi-vec non-contiguous load (scalar plus immediate, four registers)
110 0 SME2 multi-vec non-contiguous store (scalar plus immediate, two registers)
110 1 0 SME2 multi-vec non-contiguous store (scalar plus immediate, four registers)
1x1 UNALLOCATED
xx0 1 1 UNALLOCATED

SME2 multi-vec non-contiguous load (scalar plus scalar, two registers)

The encodings in this section are decoded from SME2 Multi-vector - Memory (Strided).

313029282726252423222120191817161514131211109876543210
10100001000Rm0mszPNgRnTNZt
Decode fields Instruction Details Feature
msz N
00 0 LD1B (scalar plus scalar, strided registers)FEAT_SME2
00 1 LDNT1B (scalar plus scalar, strided registers)FEAT_SME2
01 0 LD1H (scalar plus scalar, strided registers)FEAT_SME2
01 1 LDNT1H (scalar plus scalar, strided registers)FEAT_SME2
10 0 LD1W (scalar plus scalar, strided registers)FEAT_SME2
10 1 LDNT1W (scalar plus scalar, strided registers)FEAT_SME2
11 0 LD1D (scalar plus scalar, strided registers)FEAT_SME2
11 1 LDNT1D (scalar plus scalar, strided registers)FEAT_SME2

SME2 multi-vec non-contiguous load (scalar plus scalar, four registers)

The encodings in this section are decoded from SME2 Multi-vector - Memory (Strided).

313029282726252423222120191817161514131211109876543210
10100001000Rm1mszPNgRnTN0Zt
Decode fields Instruction Details Feature
msz N
00 0 LD1B (scalar plus scalar, strided registers)FEAT_SME2
00 1 LDNT1B (scalar plus scalar, strided registers)FEAT_SME2
01 0 LD1H (scalar plus scalar, strided registers)FEAT_SME2
01 1 LDNT1H (scalar plus scalar, strided registers)FEAT_SME2
10 0 LD1W (scalar plus scalar, strided registers)FEAT_SME2
10 1 LDNT1W (scalar plus scalar, strided registers)FEAT_SME2
11 0 LD1D (scalar plus scalar, strided registers)FEAT_SME2
11 1 LDNT1D (scalar plus scalar, strided registers)FEAT_SME2

SME2 multi-vec non-contiguous store (scalar plus scalar, two registers)

The encodings in this section are decoded from SME2 Multi-vector - Memory (Strided).

313029282726252423222120191817161514131211109876543210
10100001001Rm0mszPNgRnTNZt
Decode fields Instruction Details Feature
msz N
00 0 ST1B (scalar plus scalar, strided registers)FEAT_SME2
00 1 STNT1B (scalar plus scalar, strided registers)FEAT_SME2
01 0 ST1H (scalar plus scalar, strided registers)FEAT_SME2
01 1 STNT1H (scalar plus scalar, strided registers)FEAT_SME2
10 0 ST1W (scalar plus scalar, strided registers)FEAT_SME2
10 1 STNT1W (scalar plus scalar, strided registers)FEAT_SME2
11 0 ST1D (scalar plus scalar, strided registers)FEAT_SME2
11 1 STNT1D (scalar plus scalar, strided registers)FEAT_SME2

SME2 multi-vec non-contiguous store (scalar plus scalar, four registers)

The encodings in this section are decoded from SME2 Multi-vector - Memory (Strided).

313029282726252423222120191817161514131211109876543210
10100001001Rm1mszPNgRnTN0Zt
Decode fields Instruction Details Feature
msz N
00 0 ST1B (scalar plus scalar, strided registers)FEAT_SME2
00 1 STNT1B (scalar plus scalar, strided registers)FEAT_SME2
01 0 ST1H (scalar plus scalar, strided registers)FEAT_SME2
01 1 STNT1H (scalar plus scalar, strided registers)FEAT_SME2
10 0 ST1W (scalar plus scalar, strided registers)FEAT_SME2
10 1 STNT1W (scalar plus scalar, strided registers)FEAT_SME2
11 0 ST1D (scalar plus scalar, strided registers)FEAT_SME2
11 1 STNT1D (scalar plus scalar, strided registers)FEAT_SME2

SME2 multi-vec non-contiguous load (scalar plus immediate, two registers)

The encodings in this section are decoded from SME2 Multi-vector - Memory (Strided).

313029282726252423222120191817161514131211109876543210
101000010100imm40mszPNgRnTNZt
Decode fields Instruction Details Feature
msz N
00 0 LD1B (scalar plus immediate, strided registers)FEAT_SME2
00 1 LDNT1B (scalar plus immediate, strided registers)FEAT_SME2
01 0 LD1H (scalar plus immediate, strided registers)FEAT_SME2
01 1 LDNT1H (scalar plus immediate, strided registers)FEAT_SME2
10 0 LD1W (scalar plus immediate, strided registers)FEAT_SME2
10 1 LDNT1W (scalar plus immediate, strided registers)FEAT_SME2
11 0 LD1D (scalar plus immediate, strided registers)FEAT_SME2
11 1 LDNT1D (scalar plus immediate, strided registers)FEAT_SME2

SME2 multi-vec non-contiguous load (scalar plus immediate, four registers)

The encodings in this section are decoded from SME2 Multi-vector - Memory (Strided).

313029282726252423222120191817161514131211109876543210
101000010100imm41mszPNgRnTN0Zt
Decode fields Instruction Details Feature
msz N
00 0 LD1B (scalar plus immediate, strided registers)FEAT_SME2
00 1 LDNT1B (scalar plus immediate, strided registers)FEAT_SME2
01 0 LD1H (scalar plus immediate, strided registers)FEAT_SME2
01 1 LDNT1H (scalar plus immediate, strided registers)FEAT_SME2
10 0 LD1W (scalar plus immediate, strided registers)FEAT_SME2
10 1 LDNT1W (scalar plus immediate, strided registers)FEAT_SME2
11 0 LD1D (scalar plus immediate, strided registers)FEAT_SME2
11 1 LDNT1D (scalar plus immediate, strided registers)FEAT_SME2

SME2 multi-vec non-contiguous store (scalar plus immediate, two registers)

The encodings in this section are decoded from SME2 Multi-vector - Memory (Strided).

313029282726252423222120191817161514131211109876543210
101000010110imm40mszPNgRnTNZt
Decode fields Instruction Details Feature
msz N
00 0 ST1B (scalar plus immediate, strided registers)FEAT_SME2
00 1 STNT1B (scalar plus immediate, strided registers)FEAT_SME2
01 0 ST1H (scalar plus immediate, strided registers)FEAT_SME2
01 1 STNT1H (scalar plus immediate, strided registers)FEAT_SME2
10 0 ST1W (scalar plus immediate, strided registers)FEAT_SME2
10 1 STNT1W (scalar plus immediate, strided registers)FEAT_SME2
11 0 ST1D (scalar plus immediate, strided registers)FEAT_SME2
11 1 STNT1D (scalar plus immediate, strided registers)FEAT_SME2

SME2 multi-vec non-contiguous store (scalar plus immediate, four registers)

The encodings in this section are decoded from SME2 Multi-vector - Memory (Strided).

313029282726252423222120191817161514131211109876543210
101000010110imm41mszPNgRnTN0Zt
Decode fields Instruction Details Feature
msz N
00 0 ST1B (scalar plus immediate, strided registers)FEAT_SME2
00 1 STNT1B (scalar plus immediate, strided registers)FEAT_SME2
01 0 ST1H (scalar plus immediate, strided registers)FEAT_SME2
01 1 STNT1H (scalar plus immediate, strided registers)FEAT_SME2
10 0 ST1W (scalar plus immediate, strided registers)FEAT_SME2
10 1 STNT1W (scalar plus immediate, strided registers)FEAT_SME2
11 0 ST1D (scalar plus immediate, strided registers)FEAT_SME2
11 1 STNT1D (scalar plus immediate, strided registers)FEAT_SME2

SME Integer Outer Product - 32 bit

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
101000010op0op10
Decode fieldsInstruction details
op0op1
0 1 SME2 Int16 two-way outer product
1 1 UNALLOCATED
0 SME Int8 outer product

SME2 Int16 two-way outer product

The encodings in this section are decoded from SME Integer Outer Product - 32 bit.

313029282726252423222120191817161514131211109876543210
1010000u0100ZmPmPnZnS10ZAda
Decode fields Instruction Details Feature
u0 S
0 0 SMOPA (2-way)FEAT_SME2
0 1 SMOPS (2-way)FEAT_SME2
1 0 UMOPA (2-way)FEAT_SME2
1 1 UMOPS (2-way)FEAT_SME2

SME Int8 outer product

The encodings in this section are decoded from SME Integer Outer Product - 32 bit.

313029282726252423222120191817161514131211109876543210
1010000u010u1ZmPmPnZnS00ZAda
Decode fields Instruction Details Feature
u0 u1 S
0 0 0 SMOPA (4-way)FEAT_SME
0 0 1 SMOPS (4-way)FEAT_SME
0 1 0 SUMOPAFEAT_SME
0 1 1 SUMOPSFEAT_SME
1 0 0 USMOPAFEAT_SME
1 0 1 USMOPSFEAT_SME
1 1 0 UMOPA (4-way)FEAT_SME
1 1 1 UMOPS (4-way)FEAT_SME

SME2 Quarter Tile Outer Product - 64-bit

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
10op00000op111op2000000001
Decode fieldsInstruction details
op0op1op2
0 0 0 SME2 FP64 non-widening quarter tile outer product
0 0 1 UNALLOCATED
0 1 UNALLOCATED
1 SME2 Int16 to Int64 quarter tile outer product

SME2 FP64 non-widening quarter tile outer product

The encodings in this section are decoded from SME2 Quarter Tile Outer Product - 64-bit.

313029282726252423222120191817161514131211109876543210
10000000110MZm0000000NZn0S1ZAda
Decode fields Instruction Details Feature
M N S
0 0 0 FMOP4A (non-widening) — Double-precision, single vectorsFEAT_SME_MOP4 && FEAT_SME_F64F64
0 0 1 FMOP4S (non-widening) — Double-precision, single vectorsFEAT_SME_MOP4 && FEAT_SME_F64F64
0 1 0 FMOP4A (non-widening) — Double-precision, multiple and single vectorsFEAT_SME_MOP4 && FEAT_SME_F64F64
0 1 1 FMOP4S (non-widening) — Double-precision, multiple and single vectorsFEAT_SME_MOP4 && FEAT_SME_F64F64
1 0 0 FMOP4A (non-widening) — Double-precision, single and multiple vectorsFEAT_SME_MOP4 && FEAT_SME_F64F64
1 0 1 FMOP4S (non-widening) — Double-precision, single and multiple vectorsFEAT_SME_MOP4 && FEAT_SME_F64F64
1 1 0 FMOP4A (non-widening) — Double-precision, multiple vectorsFEAT_SME_MOP4 && FEAT_SME_F64F64
1 1 1 FMOP4S (non-widening) — Double-precision, multiple vectorsFEAT_SME_MOP4 && FEAT_SME_F64F64

SME2 Int16 to Int64 quarter tile outer product

The encodings in this section are decoded from SME2 Quarter Tile Outer Product - 64-bit.

313029282726252423222120191817161514131211109876543210
1010000u011u1MZm0000000NZn0S1ZAda
Decode fields Instruction Details Feature
u0 u1 M N S
0 0 0 0 0 SMOP4A (4-way) — 64-bit, single vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
0 0 0 0 1 SMOP4S (4-way) — 64-bit, single vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
0 0 0 1 0 SMOP4A (4-way) — 64-bit, multiple and single vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
0 0 0 1 1 SMOP4S (4-way) — 64-bit, multiple and single vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
0 0 1 0 0 SMOP4A (4-way) — 64-bit, single and multiple vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
0 0 1 0 1 SMOP4S (4-way) — 64-bit, single and multiple vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
0 0 1 1 0 SMOP4A (4-way) — 64-bit, multiple vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
0 0 1 1 1 SMOP4S (4-way) — 64-bit, multiple vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
0 1 0 0 0 SUMOP4A — 64-bit, single vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
0 1 0 0 1 SUMOP4S — 64-bit, single vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
0 1 0 1 0 SUMOP4A — 64-bit, multiple and single vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
0 1 0 1 1 SUMOP4S — 64-bit, multiple and single vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
0 1 1 0 0 SUMOP4A — 64-bit, single and multiple vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
0 1 1 0 1 SUMOP4S — 64-bit, single and multiple vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
0 1 1 1 0 SUMOP4A — 64-bit, multiple vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
0 1 1 1 1 SUMOP4S — 64-bit, multiple vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
1 0 0 0 0 USMOP4A — 64-bit, single vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
1 0 0 0 1 USMOP4S — 64-bit, single vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
1 0 0 1 0 USMOP4A — 64-bit, multiple and single vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
1 0 0 1 1 USMOP4S — 64-bit, multiple and single vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
1 0 1 0 0 USMOP4A — 64-bit, single and multiple vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
1 0 1 0 1 USMOP4S — 64-bit, single and multiple vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
1 0 1 1 0 USMOP4A — 64-bit, multiple vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
1 0 1 1 1 USMOP4S — 64-bit, multiple vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
1 1 0 0 0 UMOP4A (4-way) — 64-bit, single vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
1 1 0 0 1 UMOP4S (4-way) — 64-bit, single vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
1 1 0 1 0 UMOP4A (4-way) — 64-bit, multiple and single vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
1 1 0 1 1 UMOP4S (4-way) — 64-bit, multiple and single vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
1 1 1 0 0 UMOP4A (4-way) — 64-bit, single and multiple vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
1 1 1 0 1 UMOP4S (4-way) — 64-bit, single and multiple vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
1 1 1 1 0 UMOP4A (4-way) — 64-bit, multiple vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64
1 1 1 1 1 UMOP4S (4-way) — 64-bit, multiple vectorsFEAT_SME_MOP4 && FEAT_SME_I16I64

SME Outer Product - 64 bit

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
10op00000op111op20
Decode fieldsInstruction details
op0op1op2
0 0 0 SME FP64 outer product
0 0 1 UNALLOCATED
0 1 UNALLOCATED
1 SME Int16 outer product

SME FP64 outer product

The encodings in this section are decoded from SME Outer Product - 64 bit.

313029282726252423222120191817161514131211109876543210
10000000110ZmPmPnZnS0ZAda
Decode fields Instruction Details Feature
S
0 FMOPA (non-widening)FEAT_SME_F64F64
1 FMOPS (non-widening)FEAT_SME_F64F64

SME Int16 outer product

The encodings in this section are decoded from SME Outer Product - 64 bit.

313029282726252423222120191817161514131211109876543210
1010000u011u1ZmPmPnZnS0ZAda
Decode fields Instruction Details Feature
u0 u1 S
0 0 0 SMOPA (4-way)FEAT_SME_I16I64
0 0 1 SMOPS (4-way)FEAT_SME_I16I64
0 1 0 SUMOPAFEAT_SME_I16I64
0 1 1 SUMOPSFEAT_SME_I16I64
1 0 0 USMOPAFEAT_SME_I16I64
1 0 1 USMOPSFEAT_SME_I16I64
1 1 0 UMOPA (4-way)FEAT_SME_I16I64
1 1 1 UMOPS (4-way)FEAT_SME_I16I64

SME zero array

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
11000000000010op0
Decode fieldsInstruction detailsFeature
op0
0000000000 ZERO (tiles)FEAT_SME
!= 0000000000 UNALLOCATED-

SME2 Multiple Zero

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
11000000000011op0
Decode fieldsInstruction details
op0
0000000000 SME multiple vectors zero array
!= 0000000000 UNALLOCATED

SME multiple vectors zero array

The encodings in this section are decoded from SME2 Multiple Zero.

313029282726252423222120191817161514131211109876543210
11000000000011opcRv0000000000opc2
Decode fields Instruction Details Feature
opc opc2
x1x 1xx UNALLOCATED-
000 ZERO (single-vector) — Two ZA single-vectorsFEAT_SME2p1
001 ZERO (double-vector) — One ZA double-vectorFEAT_SME2p1
010 0xx ZERO (double-vector) — Two ZA double-vectorsFEAT_SME2p1
011 0xx ZERO (double-vector) — Four ZA double-vectorsFEAT_SME2p1
100 ZERO (single-vector) — Four ZA single-vectorsFEAT_SME2p1
101 0xx ZERO (quad-vector) — One ZA quad-vectorFEAT_SME2p1
101 1xx UNALLOCATED-
11x 01x UNALLOCATED-
110 00x ZERO (quad-vector) — Two ZA quad-vectorsFEAT_SME2p1
111 00x ZERO (quad-vector) — Four ZA quad-vectorsFEAT_SME2p1

SME2 zero lookup table

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
11000000010010op0
Decode fieldsInstruction details
op0
00000000000000 SME2 zero lookup table
!= 00000000000000 UNALLOCATED

SME2 zero lookup table

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
1100000001001000000000000000opc
Decode fields Instruction Details Feature
opc
0001 ZERO (table)FEAT_SME2
!= 0001 UNALLOCATED-

SME2 zero lookup table

The encodings in this section are decoded from SME2 zero lookup table.

313029282726252423222120191817161514131211109876543210
1100000001001000000000000000opc
Decode fields Instruction Details Feature
opc
0001 ZERO (table)FEAT_SME2
!= 0001 UNALLOCATED-

SME2 Move Lookup Table

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
11000000010011op0op1op2
Decode fieldsInstruction details
op0op1op2
0 00 SME2 move from lookup table
0 10 UNALLOCATED
1 00 SME2 move into lookup table
1 10 0 SME2 move vector to lookup table
1 10 1 UNALLOCATED
x1 UNALLOCATED

SME2 move from lookup table

The encodings in this section are decoded from SME2 Move Lookup Table.

313029282726252423222120191817161514131211109876543210
11000000010011000imm3opcRt
Decode fields Instruction Details Feature
opc
0011111 MOVT (table to scalar)FEAT_SME2
!= 0011111 UNALLOCATED-

SME2 move into lookup table

The encodings in this section are decoded from SME2 Move Lookup Table.

313029282726252423222120191817161514131211109876543210
11000000010011100imm3opcRt
Decode fields Instruction Details Feature
opc
0011111 MOVT (scalar to table)FEAT_SME2
!= 0011111 UNALLOCATED-

SME2 move vector to lookup table

The encodings in this section are decoded from SME2 Move Lookup Table.

313029282726252423222120191817161514131211109876543210
110000000100111100off2opcZt
Decode fields Instruction Details Feature
opc
0011111 MOVT (vector to table)FEAT_SME_LUTv2
!= 0011111 UNALLOCATED-

SME2 Expand Lookup Table (Non-contiguous)

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
1100000010011op0op1op2op3
Decode fieldsInstruction details
op0op1op2op3
011 00 0 00 SME2 lookup table two source registers expand to four non-contiguous destination registers
011 00 1 00 UNALLOCATED
10 00 SME2 lookup table expand four non-contiguous registers
x0 01 UNALLOCATED
x1 0x SME2 lookup table expand two non-contiguous registers
1x UNALLOCATED
!= 011 00 00 UNALLOCATED

SME2 lookup table two source registers expand to four non-contiguous destination registers

The encodings in this section are decoded from SME2 Expand Lookup Table (Non-contiguous).

313029282726252423222120191817161514131211109876543210
110000001001101100sizeopcZn0D00Zd
Decode fields Instruction Details Feature
opc
00 LUTI4 (four registers, 8-bit)FEAT_SME2p1 && FEAT_SME_LUTv2
!= 00 UNALLOCATED-

SME2 lookup table expand four non-contiguous registers

The encodings in this section are decoded from SME2 Expand Lookup Table (Non-contiguous).

313029282726252423222120191817161514131211109876543210
1100000010011opc10sizeopc2ZnD00Zd
Decode fields Instruction Details Feature
opc opc2
!= 00 UNALLOCATED-
00x 00 UNALLOCATED-
01x 00 LUTI4 (four registers, 16-bit & 32-bit)FEAT_SME2p1
1xx 00 LUTI2 (four registers)FEAT_SME2p1

SME2 lookup table expand two non-contiguous registers

The encodings in this section are decoded from SME2 Expand Lookup Table (Non-contiguous).

313029282726252423222120191817161514131211109876543210
1100000010011opc1sizeopc2ZnD0Zd
Decode fields Instruction Details Feature
opc opc2
!= 00 UNALLOCATED-
00xx 00 UNALLOCATED-
01xx 00 LUTI4 (two registers)FEAT_SME2p1
1xxx 00 LUTI2 (two registers)FEAT_SME2p1

SME2 Expand Lookup Table (Contiguous)

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
110000001op0001op1op2op3
Decode fieldsInstruction details
op0op1op2op3
0 00x00 00 UNALLOCATED
0 01000 00 UNALLOCATED
0 01100 0 00 SME2 lookup table two source registers expand to four contiguous destination registers
0 01100 1 00 UNALLOCATED
0 1xx00 00 UNALLOCATED
0 xxx10 00 SME2 lookup table expand four contiguous registers
0 xxxx0 10 UNALLOCATED
0 xxxx1 x0 SME2 lookup table expand two contiguous registers
0 x1 UNALLOCATED
1 SME2 lookup table expand one register

SME2 lookup table two source registers expand to four contiguous destination registers

The encodings in this section are decoded from SME2 Expand Lookup Table (Contiguous).

313029282726252423222120191817161514131211109876543210
110000001000101100sizeopcZn0Zd00
Decode fields Instruction Details Feature
opc
00 LUTI4 (four registers, 8-bit)FEAT_SME_LUTv2
!= 00 UNALLOCATED-

SME2 lookup table expand four contiguous registers

The encodings in this section are decoded from SME2 Expand Lookup Table (Contiguous).

313029282726252423222120191817161514131211109876543210
1100000010001opc10sizeopc2ZnZd00
Decode fields Instruction Details Feature
opc opc2
!= 00 UNALLOCATED-
00x 00 UNALLOCATED-
01x 00 LUTI4 (four registers, 16-bit & 32-bit)FEAT_SME2
1xx 00 LUTI2 (four registers)FEAT_SME2

SME2 lookup table expand two contiguous registers

The encodings in this section are decoded from SME2 Expand Lookup Table (Contiguous).

313029282726252423222120191817161514131211109876543210
1100000010001opc1sizeopc2ZnZd0
Decode fields Instruction Details Feature
opc opc2
!= 00 UNALLOCATED-
00xx 00 UNALLOCATED-
01xx 00 LUTI4 (two registers)FEAT_SME2
1xxx 00 LUTI2 (two registers)FEAT_SME2

SME2 lookup table expand one register

The encodings in this section are decoded from SME2 Expand Lookup Table (Contiguous).

313029282726252423222120191817161514131211109876543210
1100000011001opcsizeopc2ZnZd
Decode fields Instruction Details Feature
opc opc2
!= 00 UNALLOCATED-
00xxx 00 UNALLOCATED-
01xxx 00 LUTI4 (single)FEAT_SME2
1xxxx 00 LUTI2 (single)FEAT_SME2

SME Move into Array

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
11000000op0000op10op2op3op40op5
Decode fieldsInstruction detailsFeature
op0op1op2op3op4op5
00 1 00 010 x0 0 MOVA (vector to array, two registers)FEAT_SME2
00 1 00 011 00 0 MOVA (vector to array, four registers)FEAT_SME2
00 1 00 011 10 0 UNALLOCATED-
00 1 01 01x x0 0 UNALLOCATED-
0 SME move vector to array-
1 0x 000 x0 0 SME2 move vector to tile, two registers-
1 0x 001 00 0 SME2 move vector to tile, four registers-
1 0x 001 10 0 UNALLOCATED-
1 0x 0xx x0 1 UNALLOCATED-
1 0x 0xx x1 UNALLOCATED-
1 0x 1xx UNALLOCATED-
1 1x UNALLOCATED-
!= 00 1 0x 01x x0 0 UNALLOCATED-

SME move vector to array

The encodings in this section are decoded from SME Move into Array.

313029282726252423222120191817161514131211109876543210
11000000size00000QVRsPgZn0opc
Decode fields Instruction Details Feature
size Q
00 0 MOVA (vector to tile, single) — 8-bitFEAT_SME
01 0 MOVA (vector to tile, single) — 16-bitFEAT_SME
10 0 MOVA (vector to tile, single) — 32-bitFEAT_SME
11 0 MOVA (vector to tile, single) — 64-bitFEAT_SME
11 1 MOVA (vector to tile, single) — 128-bitFEAT_SME
!= 11 1 UNALLOCATED-

SME2 move vector to tile, two registers

The encodings in this section are decoded from SME Move into Array.

313029282726252423222120191817161514131211109876543210
11000000size000100VRs000Zn000opc
Decode fields Instruction Details Feature
size
00 MOVA (vector to tile, two registers) — 8-bitFEAT_SME2
01 MOVA (vector to tile, two registers) — 16-bitFEAT_SME2
10 MOVA (vector to tile, two registers) — 32-bitFEAT_SME2
11 MOVA (vector to tile, two registers) — 64-bitFEAT_SME2

SME2 move vector to tile, four registers

The encodings in this section are decoded from SME Move into Array.

313029282726252423222120191817161514131211109876543210
11000000size000100VRs001Zn0000opc
Decode fields Instruction Details Feature
size opc
00 0xx MOVA (vector to tile, four registers) — 8-bitFEAT_SME2
01 0xx MOVA (vector to tile, four registers) — 16-bitFEAT_SME2
10 0xx MOVA (vector to tile, four registers) — 32-bitFEAT_SME2
11 MOVA (vector to tile, four registers) — 64-bitFEAT_SME2
!= 11 1xx UNALLOCATED-

SME Move from Array

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
11000000op0000op11op2op3op4op5
Decode fieldsInstruction detailsFeature
op0op1op2op3op4op5
00 1 00 010 00 x0 MOVA (array to vector, two registers)FEAT_SME2
00 1 00 010 10 x0 MOVAZ (array to vector, two registers)FEAT_SME2p1
00 1 00 011 00 00 MOVA (array to vector, four registers)FEAT_SME2
00 1 00 011 10 00 MOVAZ (array to vector, four registers)FEAT_SME2p1
00 1 00 011 x0 10 UNALLOCATED-
00 1 01 01x x0 x0 UNALLOCATED-
0 000 1x SME zeroing move array to vector-
0 0x SME move array to vector-
0 != 000 1x UNALLOCATED-
1 0x 000 00 x0 SME2 move tile to vector, two registers-
1 0x 000 10 x0 SME2 zeroing move tile to vector, two registers-
1 0x 001 00 00 SME2 move tile to vector, four registers-
1 0x 001 10 00 SME2 zeroing move tile to vector, four registers-
1 0x 001 x0 10 UNALLOCATED-
1 0x 0xx x0 x1 UNALLOCATED-
1 0x 0xx x1 UNALLOCATED-
1 0x 1xx UNALLOCATED-
1 1x UNALLOCATED-
!= 00 1 0x 01x x0 x0 UNALLOCATED-

SME zeroing move array to vector

The encodings in this section are decoded from SME Move from Array.

313029282726252423222120191817161514131211109876543210
11000000size00001QVRs0001opcZd
Decode fields Instruction Details Feature
size Q
00 0 MOVAZ (tile to vector, single) — 8-bitFEAT_SME2p1
01 0 MOVAZ (tile to vector, single) — 16-bitFEAT_SME2p1
10 0 MOVAZ (tile to vector, single) — 32-bitFEAT_SME2p1
11 0 MOVAZ (tile to vector, single) — 64-bitFEAT_SME2p1
11 1 MOVAZ (tile to vector, single) — 128-bitFEAT_SME2p1
!= 11 1 UNALLOCATED-

SME move array to vector

The encodings in this section are decoded from SME Move from Array.

313029282726252423222120191817161514131211109876543210
11000000size00001QVRsPg0opcZd
Decode fields Instruction Details Feature
size Q
00 0 MOVA (tile to vector, single) — 8-bitFEAT_SME
01 0 MOVA (tile to vector, single) — 16-bitFEAT_SME
10 0 MOVA (tile to vector, single) — 32-bitFEAT_SME
11 0 MOVA (tile to vector, single) — 64-bitFEAT_SME
11 1 MOVA (tile to vector, single) — 128-bitFEAT_SME
!= 11 1 UNALLOCATED-

SME2 move tile to vector, two registers

The encodings in this section are decoded from SME Move from Array.

313029282726252423222120191817161514131211109876543210
11000000size000110VRs00000opcZd0
Decode fields Instruction Details Feature
size
00 MOVA (tile to vector, two registers) — 8-bitFEAT_SME2
01 MOVA (tile to vector, two registers) — 16-bitFEAT_SME2
10 MOVA (tile to vector, two registers) — 32-bitFEAT_SME2
11 MOVA (tile to vector, two registers) — 64-bitFEAT_SME2

SME2 zeroing move tile to vector, two registers

The encodings in this section are decoded from SME Move from Array.

313029282726252423222120191817161514131211109876543210
11000000size000110VRs00010opcZd0
Decode fields Instruction Details Feature
size
00 MOVAZ (tile to vector, two registers) — 8-bitFEAT_SME2p1
01 MOVAZ (tile to vector, two registers) — 16-bitFEAT_SME2p1
10 MOVAZ (tile to vector, two registers) — 32-bitFEAT_SME2p1
11 MOVAZ (tile to vector, two registers) — 64-bitFEAT_SME2p1

SME2 move tile to vector, four registers

The encodings in this section are decoded from SME Move from Array.

313029282726252423222120191817161514131211109876543210
11000000size000110VRs00100opcZd00
Decode fields Instruction Details Feature
size opc
00 0xx MOVA (tile to vector, four registers) — 8-bitFEAT_SME2
01 0xx MOVA (tile to vector, four registers) — 16-bitFEAT_SME2
10 0xx MOVA (tile to vector, four registers) — 32-bitFEAT_SME2
11 MOVA (tile to vector, four registers) — 64-bitFEAT_SME2
!= 11 1xx UNALLOCATED-

SME2 zeroing move tile to vector, four registers

The encodings in this section are decoded from SME Move from Array.

313029282726252423222120191817161514131211109876543210
11000000size000110VRs00110opcZd00
Decode fields Instruction Details Feature
size opc
00 0xx MOVAZ (tile to vector, four registers) — 8-bitFEAT_SME2p1
01 0xx MOVAZ (tile to vector, four registers) — 16-bitFEAT_SME2p1
10 0xx MOVAZ (tile to vector, four registers) — 32-bitFEAT_SME2p1
11 MOVAZ (tile to vector, four registers) — 64-bitFEAT_SME2p1
!= 11 1xx UNALLOCATED-

SME Add Vector to Array

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
11000000op0010op1op20
Decode fieldsInstruction details
op0op1op2
0 UNALLOCATED
1 00 0 SME add vector to array
1 00 1 UNALLOCATED
1 != 00 UNALLOCATED

SME add vector to array

The encodings in this section are decoded from SME Add Vector to Array.

313029282726252423222120191817161514131211109876543210
110000001op01000VPmPnZn00opc2
Decode fields Instruction Details Feature
op V opc2
0 1xx UNALLOCATED-
0 0 0xx ADDHA — 32-bitFEAT_SME
0 1 0xx ADDVA — 32-bitFEAT_SME
1 0 ADDHA — 64-bitFEAT_SME_I16I64
1 1 ADDVA — 64-bitFEAT_SME_I16I64

SME2 Multi-vector - Multiple and Single Array Vectors (Two registers)

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
110000010op0100op1op2op3
Decode fieldsInstruction detailsFeature
op0op1op2op3
0 000 000 1 FMLALL (multiple and single vector) — Two ZA quad-vectorsFEAT_SME_F8F32
0 000 != 000 1 UNALLOCATED-
0 010 SME2 single-multi long FMA two sources-
0 011 SME2 multiple and single vector long FMA one source-
0 100 SME2 single-multi FP dot product two registers-
0 101 x1x SME2 single-multi mixed dot product two registers-
1 000 1 UNALLOCATED-
1 010 SME2 single-multi long MLA two sources-
1 011 SME2 multiple and single vector long MLA one source-
1 100 UNALLOCATED-
1 101 x1x SME2 single-multi two-way dot product two registers-
000 0 SME2 single-multi long long MLA two sources-
001 SME2 multiple and single vector long long FMA one source-
101 x0x SME2 single-multi four-way dot product two registers-
110 0xx SME2 single-multi ternary FP two registers-
110 1xx SME2 single-multi ternary int two registers-
111 0xx SME2 single-multi ternary FP16 two registers-
111 1xx UNALLOCATED-

SME2 single-multi long FMA two sources

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000010010Zm0Rv010ZnopSo2off2
Decode fields Instruction Details Feature
op S o2
0 0 0 FMLAL (multiple and single vector, FP16 to FP32)FEAT_SME2
0 0 1 FMLAL (multiple and single vector, FP8 to FP16)FEAT_SME_F8F16
0 1 0 FMLSL (multiple and single vector)FEAT_SME2
0 1 1 UNALLOCATED-
1 1 UNALLOCATED-
1 0 0 BFMLAL (multiple and single vector)FEAT_SME2
1 1 0 BFMLSL (multiple and single vector)FEAT_SME2

SME2 multiple and single vector long FMA one source

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000010010Zm0Rv011ZnopSoff3
Decode fields Instruction Details Feature
op S
0 0 FMLAL (multiple and single vector, FP16 to FP32)FEAT_SME2
0 1 FMLSL (multiple and single vector)FEAT_SME2
1 0 BFMLAL (multiple and single vector)FEAT_SME2
1 1 BFMLSL (multiple and single vector)FEAT_SME2

SME2 single-multi FP dot product two registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000010010Zm0Rv100Znopcoff3
Decode fields Instruction Details Feature
opc
00 FDOT (2-way, multiple and single vector, FP16 to FP32)FEAT_SME2
01 FDOT (2-way, multiple and single vector, FP8 to FP16)FEAT_SME_F8F16
10 BFDOT (multiple and single vector)FEAT_SME2
11 FDOT (4-way, multiple and single vector)FEAT_SME_F8F32

SME2 single-multi mixed dot product two registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000010010Zm0Rv101ZnU1off3
Decode fields Instruction Details Feature
U
0 USDOT (multiple and single vector)FEAT_SME2
1 SUDOT (multiple and single vector)FEAT_SME2

SME2 single-multi long MLA two sources

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000010110Zm0Rv010ZnUSopoff2
Decode fields Instruction Details Feature
U S op
1 UNALLOCATED-
0 0 0 SMLAL (multiple and single vector)FEAT_SME2
0 1 0 SMLSL (multiple and single vector)FEAT_SME2
1 0 0 UMLAL (multiple and single vector)FEAT_SME2
1 1 0 UMLSL (multiple and single vector)FEAT_SME2

SME2 multiple and single vector long MLA one source

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000010110Zm0Rv011ZnUSoff3
Decode fields Instruction Details Feature
U S
0 0 SMLAL (multiple and single vector)FEAT_SME2
0 1 SMLSL (multiple and single vector)FEAT_SME2
1 0 UMLAL (multiple and single vector)FEAT_SME2
1 1 UMLSL (multiple and single vector)FEAT_SME2

SME2 single-multi two-way dot product two registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000010110Zm0Rv101ZnU1off3
Decode fields Instruction Details Feature
U
0 SDOT (2-way, multiple and single vector)FEAT_SME2
1 UDOT (2-way, multiple and single vector)FEAT_SME2

SME2 single-multi long long MLA two sources

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000010sz10Zm0Rv000ZnUSop0o1
Decode fields Instruction Details Feature
sz U S op
0 0 0 SMLALL (multiple and single vector)FEAT_SME2
0 1 0 SMLSLL (multiple and single vector)FEAT_SME2
1 0 0 UMLALL (multiple and single vector)FEAT_SME2
1 1 0 UMLSLL (multiple and single vector)FEAT_SME2
0 1 1 UNALLOCATED-
0 0 0 1 USMLALL (multiple and single vector)FEAT_SME2
0 1 0 1 SUMLALL (multiple and single vector)FEAT_SME2
1 1 UNALLOCATED-

SME2 multiple and single vector long long FMA one source

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000010sz10Zm0Rv001ZnUSopoff2
Decode fields Instruction Details Feature
sz U S op
0 0 0 SMLALL (multiple and single vector)FEAT_SME2
0 1 0 SMLSLL (multiple and single vector)FEAT_SME2
1 0 0 UMLALL (multiple and single vector)FEAT_SME2
1 1 0 UMLSLL (multiple and single vector)FEAT_SME2
0 0 0 1 USMLALL (multiple and single vector)FEAT_SME2
0 0 1 1 UNALLOCATED-
0 1 1 UNALLOCATED-
1 1 UNALLOCATED-

SME2 single-multi four-way dot product two registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000010sz10Zm0Rv101ZnU0off3
Decode fields Instruction Details Feature
U
0 SDOT (4-way, multiple and single vector)FEAT_SME2
1 UDOT (4-way, multiple and single vector)FEAT_SME2

SME2 single-multi ternary FP two registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000010sz10Zm0Rv110Zn0Soff3
Decode fields Instruction Details Feature
S
0 FMLA (multiple and single vector)FEAT_SME2
1 FMLS (multiple and single vector)FEAT_SME2

SME2 single-multi ternary int two registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000010sz10Zm0Rv110Zn1Soff3
Decode fields Instruction Details Feature
S
0 ADD (array results, multiple and single vector)FEAT_SME2
1 SUB (array results, multiple and single vector)FEAT_SME2

SME2 single-multi ternary FP16 two registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000010sz10Zm0Rv111Zn0Soff3
Decode fields Instruction Details Feature
sz S
0 0 FMLA (multiple and single vector)FEAT_SME_F16F16
0 1 FMLS (multiple and single vector)FEAT_SME_F16F16
1 0 BFMLA (multiple and single vector)FEAT_SME_B16B16
1 1 BFMLS (multiple and single vector)FEAT_SME_B16B16

SME2 Multi-vector - Multiple and Single Array Vectors (Four registers)

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
110000010op0110op1op2op3
Decode fieldsInstruction detailsFeature
op0op1op2op3
0 000 000 1 FMLALL (multiple and single vector) — Four ZA quad-vectorsFEAT_SME_F8F32
0 000 != 000 1 UNALLOCATED-
0 001 000 FMLALL (multiple and single vector) — One ZA quad-vectorFEAT_SME_F8F32
0 001 001 UNALLOCATED-
0 010 SME2 single-multi long FMA four sources-
0 011 00x FMLAL (multiple and single vector, FP8 to FP16) — One ZA double-vectorFEAT_SME_F8F16
0 0x1 01x UNALLOCATED-
0 0x1 1xx UNALLOCATED-
0 100 SME2 single-multi FP dot product four registers-
0 101 x1x SME2 single-multi mixed dot product four registers-
1 000 1 UNALLOCATED-
1 010 SME2 single-multi long MLA four sources-
1 0x1 UNALLOCATED-
1 100 UNALLOCATED-
1 101 x1x SME2 single-multi two-way dot product four registers-
000 0 SME2 single-multi long long MLA four sources-
101 x0x SME2 single-multi four-way dot product four registers-
110 0xx SME2 single-multi ternary FP four registers-
110 1xx SME2 single-multi ternary int four registers-
111 0xx SME2 single-multi ternary FP16 four registers-
111 1xx UNALLOCATED-

SME2 single-multi long FMA four sources

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000010011Zm0Rv010ZnopSo2off2
Decode fields Instruction Details Feature
op S o2
0 0 0 FMLAL (multiple and single vector, FP16 to FP32)FEAT_SME2
0 0 1 FMLAL (multiple and single vector, FP8 to FP16)FEAT_SME_F8F16
0 1 0 FMLSL (multiple and single vector)FEAT_SME2
0 1 1 UNALLOCATED-
1 1 UNALLOCATED-
1 0 0 BFMLAL (multiple and single vector)FEAT_SME2
1 1 0 BFMLSL (multiple and single vector)FEAT_SME2

SME2 single-multi FP dot product four registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000010011Zm0Rv100Znopcoff3
Decode fields Instruction Details Feature
opc
00 FDOT (2-way, multiple and single vector, FP16 to FP32)FEAT_SME2
01 FDOT (2-way, multiple and single vector, FP8 to FP16)FEAT_SME_F8F16
10 BFDOT (multiple and single vector)FEAT_SME2
11 FDOT (4-way, multiple and single vector)FEAT_SME_F8F32

SME2 single-multi mixed dot product four registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000010011Zm0Rv101ZnU1off3
Decode fields Instruction Details Feature
U
0 USDOT (multiple and single vector)FEAT_SME2
1 SUDOT (multiple and single vector)FEAT_SME2

SME2 single-multi long MLA four sources

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000010111Zm0Rv010ZnUSopoff2
Decode fields Instruction Details Feature
U S op
1 UNALLOCATED-
0 0 0 SMLAL (multiple and single vector)FEAT_SME2
0 1 0 SMLSL (multiple and single vector)FEAT_SME2
1 0 0 UMLAL (multiple and single vector)FEAT_SME2
1 1 0 UMLSL (multiple and single vector)FEAT_SME2

SME2 single-multi two-way dot product four registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000010111Zm0Rv101ZnU1off3
Decode fields Instruction Details Feature
U
0 SDOT (2-way, multiple and single vector)FEAT_SME2
1 UDOT (2-way, multiple and single vector)FEAT_SME2

SME2 single-multi long long MLA four sources

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000010sz11Zm0Rv000ZnUSop0o1
Decode fields Instruction Details Feature
sz U S op
0 0 0 SMLALL (multiple and single vector)FEAT_SME2
0 1 0 SMLSLL (multiple and single vector)FEAT_SME2
1 0 0 UMLALL (multiple and single vector)FEAT_SME2
1 1 0 UMLSLL (multiple and single vector)FEAT_SME2
0 1 1 UNALLOCATED-
0 0 0 1 USMLALL (multiple and single vector)FEAT_SME2
0 1 0 1 SUMLALL (multiple and single vector)FEAT_SME2
1 1 UNALLOCATED-

SME2 single-multi four-way dot product four registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000010sz11Zm0Rv101ZnU0off3
Decode fields Instruction Details Feature
U
0 SDOT (4-way, multiple and single vector)FEAT_SME2
1 UDOT (4-way, multiple and single vector)FEAT_SME2

SME2 single-multi ternary FP four registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000010sz11Zm0Rv110Zn0Soff3
Decode fields Instruction Details Feature
S
0 FMLA (multiple and single vector)FEAT_SME2
1 FMLS (multiple and single vector)FEAT_SME2

SME2 single-multi ternary int four registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000010sz11Zm0Rv110Zn1Soff3
Decode fields Instruction Details Feature
S
0 ADD (array results, multiple and single vector)FEAT_SME2
1 SUB (array results, multiple and single vector)FEAT_SME2

SME2 single-multi ternary FP16 four registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000010sz11Zm0Rv111Zn0Soff3
Decode fields Instruction Details Feature
sz S
0 0 FMLA (multiple and single vector)FEAT_SME_F16F16
0 1 FMLS (multiple and single vector)FEAT_SME_F16F16
1 0 BFMLA (multiple and single vector)FEAT_SME_B16B16
1 1 BFMLS (multiple and single vector)FEAT_SME_B16B16

SME2 Multi-vector - Multiple Array Vectors (Two registers)

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
110000011op01op1op200op3op4op5op6
Decode fieldsInstruction detailsFeature
op0op1op2op3op4op5op6
0 000 1 000 0 FMLALL (multiple vectors) — Two ZA quad-vectorsFEAT_SME_F8F32
0 000 1 001 0 UNALLOCATED-
0 000 1 10x 0 UNALLOCATED-
0 000 1 x0x 1 UNALLOCATED-
0 010 0 xx0 SME2 multiple vectors long FMA two sources-
0 010 1 000 FMLAL (multiple vectors, FP8 to FP16) — Two ZA double-vectorsFEAT_SME_F8F16
0 010 1 100 UNALLOCATED-
0 010 1 x01 UNALLOCATED-
0 0x1 1 UNALLOCATED-
0 100 x0x SME2 multiple vectors FP dot product two registers-
0 101 0 01x USDOT (multiple vectors) — Two ZA single-vectorsFEAT_SME2
0 101 0 11x UNALLOCATED-
0 110 1 x0x UNALLOCATED-
0 1x1 1 UNALLOCATED-
0 xx0 1 x1x UNALLOCATED-
1 010 0 xx0 SME2 multiple vectors long MLA two sources-
1 100 0 x0x UNALLOCATED-
1 101 0 x1x SME2 multiple vectors two-way dot product two registers-
1 1 UNALLOCATED-
00 00 111 0 0xx SME2 multiple vectors binary FP two registers-
00 00 111 0 1xx SME2 multiple vectors binary int two registers-
00 10 111 0 0xx SME2 multiple vectors binary FP16 two registers-
00 10 111 0 1xx UNALLOCATED-
00 x1 111 0 UNALLOCATED-
000 0 0 SME2 multiple vectors long long MLA two sources-
000 0 1 UNALLOCATED-
010 0 xx1 UNALLOCATED-
0x1 0 UNALLOCATED-
100 0 x1x SME2 multiple vectors ternary FP16 two registers-
101 0 x0x SME2 multiple vectors four-way dot product two registers-
110 0 0xx SME2 multiple vectors ternary FP two registers-
110 0 1xx SME2 multiple vectors ternary int two registers-
!= 00 111 0 UNALLOCATED-

SME2 multiple vectors long FMA two sources

The encodings in this section are decoded from SME2 Multi-vector - Multiple Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
11000001101Zm00Rv010Zn0opS0off2
Decode fields Instruction Details Feature
op S
0 0 FMLAL (multiple vectors, FP16 to FP32)FEAT_SME2
0 1 FMLSL (multiple vectors)FEAT_SME2
1 0 BFMLAL (multiple vectors)FEAT_SME2
1 1 BFMLSL (multiple vectors)FEAT_SME2

SME2 multiple vectors FP dot product two registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
11000001101Zm00Rv100Znopc0off3
Decode fields Instruction Details Feature
opc
00 FDOT (2-way, multiple vectors, FP16 to FP32)FEAT_SME2
01 BFDOT (multiple vectors)FEAT_SME2
10 FDOT (2-way, multiple vectors, FP8 to FP16)FEAT_SME_F8F16
11 FDOT (4-way, multiple vectors)FEAT_SME_F8F32

SME2 multiple vectors long MLA two sources

The encodings in this section are decoded from SME2 Multi-vector - Multiple Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
11000001111Zm00Rv010Zn0US0off2
Decode fields Instruction Details Feature
U S
0 0 SMLAL (multiple vectors)FEAT_SME2
0 1 SMLSL (multiple vectors)FEAT_SME2
1 0 UMLAL (multiple vectors)FEAT_SME2
1 1 UMLSL (multiple vectors)FEAT_SME2

SME2 multiple vectors two-way dot product two registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
11000001111Zm00Rv101Zn0U1off3
Decode fields Instruction Details Feature
U
0 SDOT (2-way, multiple vectors)FEAT_SME2
1 UDOT (2-way, multiple vectors)FEAT_SME2

SME2 multiple vectors binary FP two registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000011sz1000000Rv111Zm00Soff3
Decode fields Instruction Details Feature
S
0 FADDFEAT_SME2
1 FSUBFEAT_SME2

SME2 multiple vectors binary int two registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000011sz1000000Rv111Zm01Soff3
Decode fields Instruction Details Feature
S
0 ADD (array accumulators)FEAT_SME2
1 SUB (array accumulators)FEAT_SME2

SME2 multiple vectors binary FP16 two registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000011sz1001000Rv111Zm00Soff3
Decode fields Instruction Details Feature
sz S
0 0 FADDFEAT_SME_F16F16 || FEAT_SME_F8F16
0 1 FSUBFEAT_SME_F16F16 || FEAT_SME_F8F16
1 0 BFADDFEAT_SME_B16B16
1 1 BFSUBFEAT_SME_B16B16

SME2 multiple vectors long long MLA two sources

The encodings in this section are decoded from SME2 Multi-vector - Multiple Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000011sz1Zm00Rv000Zn0USop0o1
Decode fields Instruction Details Feature
sz U S op
0 0 0 SMLALL (multiple vectors)FEAT_SME2
0 1 0 SMLSLL (multiple vectors)FEAT_SME2
1 0 0 UMLALL (multiple vectors)FEAT_SME2
1 1 0 UMLSLL (multiple vectors)FEAT_SME2
0 0 0 1 USMLALL (multiple vectors)FEAT_SME2
0 0 1 1 UNALLOCATED-
0 1 1 UNALLOCATED-
1 1 UNALLOCATED-

SME2 multiple vectors ternary FP16 two registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000011sz1Zm00Rv100Zn0S1off3
Decode fields Instruction Details Feature
sz S
0 0 FMLA (multiple vectors)FEAT_SME_F16F16
0 1 FMLS (multiple vectors)FEAT_SME_F16F16
1 0 BFMLA (multiple vectors)FEAT_SME_B16B16
1 1 BFMLS (multiple vectors)FEAT_SME_B16B16

SME2 multiple vectors four-way dot product two registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000011sz1Zm00Rv101Zn0U0off3
Decode fields Instruction Details Feature
U
0 SDOT (4-way, multiple vectors)FEAT_SME2
1 UDOT (4-way, multiple vectors)FEAT_SME2

SME2 multiple vectors ternary FP two registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000011sz1Zm00Rv110Zn00Soff3
Decode fields Instruction Details Feature
S
0 FMLA (multiple vectors)FEAT_SME2
1 FMLS (multiple vectors)FEAT_SME2

SME2 multiple vectors ternary int two registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000011sz1Zm00Rv110Zn01Soff3
Decode fields Instruction Details Feature
S
0 ADD (array results, multiple vectors)FEAT_SME2
1 SUB (array results, multiple vectors)FEAT_SME2

SME2 Multi-vector - Multiple Array Vectors (Four registers)

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
110000011op01op1op210op3op4op5op6
Decode fieldsInstruction detailsFeature
op0op1op2op3op4op5op6
0 x0 000 01 000 0 FMLALL (multiple vectors) — Four ZA quad-vectorsFEAT_SME_F8F32
0 x0 000 01 001 0 UNALLOCATED-
0 x0 000 01 10x 0 UNALLOCATED-
0 x0 000 01 x0x 1 UNALLOCATED-
0 x0 010 00 xx0 SME2 multiple vectors long FMA four sources-
0 x0 010 01 000 FMLAL (multiple vectors, FP8 to FP16) — Four ZA double-vectorsFEAT_SME_F8F16
0 x0 010 01 100 UNALLOCATED-
0 x0 010 01 x01 UNALLOCATED-
0 x0 0x1 01 UNALLOCATED-
0 x0 100 0x x0x SME2 multiple vectors FP dot product four registers-
0 x0 101 00 01x USDOT (multiple vectors) — Four ZA single-vectorsFEAT_SME2
0 x0 101 00 11x UNALLOCATED-
0 x0 110 01 x0x UNALLOCATED-
0 x0 1x1 01 UNALLOCATED-
0 x0 xx0 01 x1x UNALLOCATED-
1 x0 010 00 xx0 SME2 multiple vectors long MLA four sources-
1 x0 100 00 x0x UNALLOCATED-
1 x0 101 00 x1x SME2 multiple vectors two-way dot product four registers-
1 x0 01 UNALLOCATED-
00 00 111 00 0xx SME2 multiple vectors binary FP four registers-
00 00 111 00 1xx SME2 multiple vectors binary int four registers-
00 10 111 00 0xx SME2 multiple vectors binary FP16 four registers-
00 10 111 00 1xx UNALLOCATED-
x0 000 00 0 SME2 multiple vectors long long MLA four sources-
x0 000 00 1 UNALLOCATED-
x0 010 00 xx1 UNALLOCATED-
x0 0x1 00 UNALLOCATED-
x0 100 00 x1x SME2 multiple vectors ternary FP16 four registers-
x0 101 00 x0x SME2 multiple vectors four-way dot product four registers-
x0 110 00 0xx SME2 multiple vectors ternary FP four registers-
x0 110 00 1xx SME2 multiple vectors ternary int four registers-
x0 1x UNALLOCATED-
x1 UNALLOCATED-
!= 00 x0 111 00 UNALLOCATED-

SME2 multiple vectors long FMA four sources

The encodings in this section are decoded from SME2 Multi-vector - Multiple Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
11000001101Zm010Rv010Zn00opS0off2
Decode fields Instruction Details Feature
op S
0 0 FMLAL (multiple vectors, FP16 to FP32)FEAT_SME2
0 1 FMLSL (multiple vectors)FEAT_SME2
1 0 BFMLAL (multiple vectors)FEAT_SME2
1 1 BFMLSL (multiple vectors)FEAT_SME2

SME2 multiple vectors FP dot product four registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
11000001101Zm010Rv100Zn0opc0off3
Decode fields Instruction Details Feature
opc
00 FDOT (2-way, multiple vectors, FP16 to FP32)FEAT_SME2
01 BFDOT (multiple vectors)FEAT_SME2
10 FDOT (2-way, multiple vectors, FP8 to FP16)FEAT_SME_F8F16
11 FDOT (4-way, multiple vectors)FEAT_SME_F8F32

SME2 multiple vectors long MLA four sources

The encodings in this section are decoded from SME2 Multi-vector - Multiple Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
11000001111Zm010Rv010Zn00US0off2
Decode fields Instruction Details Feature
U S
0 0 SMLAL (multiple vectors)FEAT_SME2
0 1 SMLSL (multiple vectors)FEAT_SME2
1 0 UMLAL (multiple vectors)FEAT_SME2
1 1 UMLSL (multiple vectors)FEAT_SME2

SME2 multiple vectors two-way dot product four registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
11000001111Zm010Rv101Zn00U1off3
Decode fields Instruction Details Feature
U
0 SDOT (2-way, multiple vectors)FEAT_SME2
1 UDOT (2-way, multiple vectors)FEAT_SME2

SME2 multiple vectors binary FP four registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000011sz1000010Rv111Zm000Soff3
Decode fields Instruction Details Feature
S
0 FADDFEAT_SME2
1 FSUBFEAT_SME2

SME2 multiple vectors binary int four registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000011sz1000010Rv111Zm001Soff3
Decode fields Instruction Details Feature
S
0 ADD (array accumulators)FEAT_SME2
1 SUB (array accumulators)FEAT_SME2

SME2 multiple vectors binary FP16 four registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000011sz1001010Rv111Zm000Soff3
Decode fields Instruction Details Feature
sz S
0 0 FADDFEAT_SME_F16F16 || FEAT_SME_F8F16
0 1 FSUBFEAT_SME_F16F16 || FEAT_SME_F8F16
1 0 BFADDFEAT_SME_B16B16
1 1 BFSUBFEAT_SME_B16B16

SME2 multiple vectors long long MLA four sources

The encodings in this section are decoded from SME2 Multi-vector - Multiple Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000011sz1Zm010Rv000Zn00USop0o1
Decode fields Instruction Details Feature
sz U S op
0 0 0 SMLALL (multiple vectors)FEAT_SME2
0 1 0 SMLSLL (multiple vectors)FEAT_SME2
1 0 0 UMLALL (multiple vectors)FEAT_SME2
1 1 0 UMLSLL (multiple vectors)FEAT_SME2
0 0 0 1 USMLALL (multiple vectors)FEAT_SME2
0 0 1 1 UNALLOCATED-
0 1 1 UNALLOCATED-
1 1 UNALLOCATED-

SME2 multiple vectors ternary FP16 four registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000011sz1Zm010Rv100Zn00S1off3
Decode fields Instruction Details Feature
sz S
0 0 FMLA (multiple vectors)FEAT_SME_F16F16
0 1 FMLS (multiple vectors)FEAT_SME_F16F16
1 0 BFMLA (multiple vectors)FEAT_SME_B16B16
1 1 BFMLS (multiple vectors)FEAT_SME_B16B16

SME2 multiple vectors four-way dot product four registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000011sz1Zm010Rv101Zn00U0off3
Decode fields Instruction Details Feature
U
0 SDOT (4-way, multiple vectors)FEAT_SME2
1 UDOT (4-way, multiple vectors)FEAT_SME2

SME2 multiple vectors ternary FP four registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000011sz1Zm010Rv110Zn000Soff3
Decode fields Instruction Details Feature
S
0 FMLA (multiple vectors)FEAT_SME2
1 FMLS (multiple vectors)FEAT_SME2

SME2 multiple vectors ternary int four registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000011sz1Zm010Rv110Zn001Soff3
Decode fields Instruction Details Feature
S
0 ADD (array results, multiple vectors)FEAT_SME2
1 SUB (array results, multiple vectors)FEAT_SME2

SME2 Multi-vector - Indexed (One register)

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
11000001op000op1op2
Decode fieldsInstruction detailsFeature
op0op1op2
00 SME2 multi-vec indexed long long MLA one source 32-bit-
01 000 FMLALL (multiple and indexed vector) — One ZA quad-vectorFEAT_SME_F8F32
01 != 000 UNALLOCATED-
10 0 xx0 SME2 multi-vec indexed long long MLA one source 64-bit-
10 0 xx1 UNALLOCATED-
10 1 SME2 multi-vec indexed long FMA one source-
11 0 0xx FMLAL (multiple and indexed vector, FP8 to FP16) — One ZA double-vectorFEAT_SME_F8F16
11 0 1xx UNALLOCATED-
11 1 SME2 multi-vec indexed long MLA one source-

SME2 multi-vec indexed long long MLA one source 32-bit

The encodings in this section are decoded from SME2 Multi-vector - Indexed (One register).

313029282726252423222120191817161514131211109876543210
110000010000Zmi4hRvi4lZnUSopoff2
Decode fields Instruction Details Feature
U S op
1 1 UNALLOCATED-
0 0 0 SMLALL (multiple and indexed vector)FEAT_SME2
0 0 1 USMLALL (multiple and indexed vector)FEAT_SME2
0 1 0 SMLSLL (multiple and indexed vector)FEAT_SME2
1 0 0 UMLALL (multiple and indexed vector)FEAT_SME2
1 0 1 SUMLALL (multiple and indexed vector)FEAT_SME2
1 1 0 UMLSLL (multiple and indexed vector)FEAT_SME2

SME2 multi-vec indexed long long MLA one source 64-bit

The encodings in this section are decoded from SME2 Multi-vector - Indexed (One register).

313029282726252423222120191817161514131211109876543210
110000011000Zmi3hRv0i3lZnUS0off2
Decode fields Instruction Details Feature
U S
0 0 SMLALL (multiple and indexed vector)FEAT_SME2 && FEAT_SME_I16I64
0 1 SMLSLL (multiple and indexed vector)FEAT_SME2 && FEAT_SME_I16I64
1 0 UMLALL (multiple and indexed vector)FEAT_SME2 && FEAT_SME_I16I64
1 1 UMLSLL (multiple and indexed vector)FEAT_SME2 && FEAT_SME_I16I64

SME2 multi-vec indexed long FMA one source

The encodings in this section are decoded from SME2 Multi-vector - Indexed (One register).

313029282726252423222120191817161514131211109876543210
110000011000Zmi3hRv1i3lZnopSoff3
Decode fields Instruction Details Feature
op S
0 0 FMLAL (multiple and indexed vector, FP16 to FP32)FEAT_SME2
0 1 FMLSL (multiple and indexed vector)FEAT_SME2
1 0 BFMLAL (multiple and indexed vector)FEAT_SME2
1 1 BFMLSL (multiple and indexed vector)FEAT_SME2

SME2 multi-vec indexed long MLA one source

The encodings in this section are decoded from SME2 Multi-vector - Indexed (One register).

313029282726252423222120191817161514131211109876543210
110000011100Zmi3hRv1i3lZnUSoff3
Decode fields Instruction Details Feature
U S
0 0 SMLAL (multiple and indexed vector)FEAT_SME2
0 1 SMLSL (multiple and indexed vector)FEAT_SME2
1 0 UMLAL (multiple and indexed vector)FEAT_SME2
1 1 UMLSL (multiple and indexed vector)FEAT_SME2

SME2 Multi-vector - Indexed (Two registers)

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
11000001op0010op1op2op3
Decode fieldsInstruction detailsFeature
op0op1op2op3
00 0x SME2 multi-vec indexed long long MLA two sources 32-bit-
00 1x SME2 multi-vec ternary indexed two registers 16-bit-
01 SME2 multi-vec ternary indexed two registers 32-bit-
10 00 0 SME2 multi-vec indexed long long MLA two sources 64-bit-
10 01 0 UNALLOCATED-
10 0x 1 00 FMLALL (multiple and indexed vector) — Two ZA quad-vectorsFEAT_SME_F8F32
10 0x 1 != 00 UNALLOCATED-
10 1x 0 SME2 multi-vec indexed long FMA two sources-
10 1x 1 0x UNALLOCATED-
10 1x 1 1x FMLAL (multiple and indexed vector, FP8 to FP16) — Two ZA double-vectorsFEAT_SME_F8F16
11 00 0 SME2 multi-vec ternary indexed two registers 64-bit-
11 01 0 SME2 multi-vec indexed FP8 two-way vertical dot product to single-precision two registers-
11 1x 0 SME2 multi-vec indexed long MLA two sources-
11 1 0x SME2 multi-vec indexed FP8 two-way dot product to FP16 two registers-
11 1 1x UNALLOCATED-

SME2 multi-vec indexed long long MLA two sources 32-bit

The encodings in this section are decoded from SME2 Multi-vector - Indexed (Two registers).

313029282726252423222120191817161514131211109876543210
110000010001Zm0Rv0i4hZnopUSi4lo1
Decode fields Instruction Details Feature
op U S
0 0 0 SMLALL (multiple and indexed vector)FEAT_SME2
0 0 1 SMLSLL (multiple and indexed vector)FEAT_SME2
0 1 0 UMLALL (multiple and indexed vector)FEAT_SME2
0 1 1 UMLSLL (multiple and indexed vector)FEAT_SME2
1 1 UNALLOCATED-
1 0 0 USMLALL (multiple and indexed vector)FEAT_SME2
1 1 0 SUMLALL (multiple and indexed vector)FEAT_SME2

SME2 multi-vec ternary indexed two registers 16-bit

The encodings in this section are decoded from SME2 Multi-vector - Indexed (Two registers).

313029282726252423222120191817161514131211109876543210
110000010001Zm0Rv1i3hZnopSi3loff3
Decode fields Instruction Details Feature
op S
0 0 FMLA (multiple and indexed vector)FEAT_SME_F16F16
0 1 FMLS (multiple and indexed vector)FEAT_SME_F16F16
1 0 BFMLA (multiple and indexed vector)FEAT_SME_B16B16
1 1 BFMLS (multiple and indexed vector)FEAT_SME_B16B16

SME2 multi-vec ternary indexed two registers 32-bit

The encodings in this section are decoded from SME2 Multi-vector - Indexed (Two registers).

313029282726252423222120191817161514131211109876543210
110000010101Zm0Rvopi2Znopc2off3
Decode fields Instruction Details Feature
op opc2
0 000 FMLA (multiple and indexed vector)FEAT_SME2
0 001 FVDOT (FP16 to FP32)FEAT_SME2
0 010 FMLS (multiple and indexed vector)FEAT_SME2
0 011 BFVDOTFEAT_SME2
0 100 SVDOT (2-way)FEAT_SME2
0 101 UNALLOCATED-
0 110 UVDOT (2-way)FEAT_SME2
0 111 FDOT (4-way, multiple and indexed vector)FEAT_SME_F8F32
1 000 SDOT (2-way, multiple and indexed vector)FEAT_SME2
1 001 FDOT (2-way, multiple and indexed vector, FP16 to FP32)FEAT_SME2
1 010 UDOT (2-way, multiple and indexed vector)FEAT_SME2
1 011 BFDOT (multiple and indexed vector)FEAT_SME2
1 100 SDOT (4-way, multiple and indexed vector)FEAT_SME2
1 101 USDOT (multiple and indexed vector)FEAT_SME2
1 110 UDOT (4-way, multiple and indexed vector)FEAT_SME2
1 111 SUDOT (multiple and indexed vector)FEAT_SME2

SME2 multi-vec indexed long long MLA two sources 64-bit

The encodings in this section are decoded from SME2 Multi-vector - Indexed (Two registers).

313029282726252423222120191817161514131211109876543210
110000011001Zm0Rv00i3hZn0USi3lo1
Decode fields Instruction Details Feature
U S
0 0 SMLALL (multiple and indexed vector)FEAT_SME2 && FEAT_SME_I16I64
0 1 SMLSLL (multiple and indexed vector)FEAT_SME2 && FEAT_SME_I16I64
1 0 UMLALL (multiple and indexed vector)FEAT_SME2 && FEAT_SME_I16I64
1 1 UMLSLL (multiple and indexed vector)FEAT_SME2 && FEAT_SME_I16I64

SME2 multi-vec indexed long FMA two sources

The encodings in this section are decoded from SME2 Multi-vector - Indexed (Two registers).

313029282726252423222120191817161514131211109876543210
110000011001Zm0Rv1i3hZn0opSi3loff2
Decode fields Instruction Details Feature
op S
0 0 FMLAL (multiple and indexed vector, FP16 to FP32)FEAT_SME2
0 1 FMLSL (multiple and indexed vector)FEAT_SME2
1 0 BFMLAL (multiple and indexed vector)FEAT_SME2
1 1 BFMLSL (multiple and indexed vector)FEAT_SME2

SME2 multi-vec ternary indexed two registers 64-bit

The encodings in this section are decoded from SME2 Multi-vector - Indexed (Two registers).

313029282726252423222120191817161514131211109876543210
110000011101Zm0Rv00i1Zn0opcoff3
Decode fields Instruction Details Feature
opc
00 FMLA (multiple and indexed vector)FEAT_SME2 && FEAT_SME_F64F64
01 SDOT (4-way, multiple and indexed vector)FEAT_SME2 && FEAT_SME_I16I64
10 FMLS (multiple and indexed vector)FEAT_SME2 && FEAT_SME_F64F64
11 UDOT (4-way, multiple and indexed vector)FEAT_SME2 && FEAT_SME_I16I64

SME2 multi-vec indexed FP8 two-way vertical dot product to single-precision two registers

The encodings in this section are decoded from SME2 Multi-vector - Indexed (Two registers).

313029282726252423222120191817161514131211109876543210
110000011101Zm0Rv01i2hZn0Ti2loff3
Decode fields Instruction Details Feature
T
0 FVDOTBFEAT_SME_F8F32
1 FVDOTTFEAT_SME_F8F32

SME2 multi-vec indexed long MLA two sources

The encodings in this section are decoded from SME2 Multi-vector - Indexed (Two registers).

313029282726252423222120191817161514131211109876543210
110000011101Zm0Rv1i3hZn0USi3loff2
Decode fields Instruction Details Feature
U S
0 0 SMLAL (multiple and indexed vector)FEAT_SME2
0 1 SMLSL (multiple and indexed vector)FEAT_SME2
1 0 UMLAL (multiple and indexed vector)FEAT_SME2
1 1 UMLSL (multiple and indexed vector)FEAT_SME2

SME2 multi-vec indexed FP8 two-way dot product to FP16 two registers

The encodings in this section are decoded from SME2 Multi-vector - Indexed (Two registers).

313029282726252423222120191817161514131211109876543210
110000011101Zm0Rvopi3hZn10i3loff3
Decode fields Instruction Details Feature
op
0 FDOT (2-way, multiple and indexed vector, FP8 to FP16)FEAT_SME_F8F16
1 FVDOT (FP8 to FP16)FEAT_SME_F8F16

SME2 Multi-vector - Indexed (Four registers)

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
11000001op0011op1op2op3
Decode fieldsInstruction detailsFeature
op0op1op2op3
00 0x 0xx SME2 multi-vec indexed long long MLA four sources 32-bit-
00 0x 100 0 FMLALL (multiple and indexed vector) — Four ZA quad-vectorsFEAT_SME_F8F32
00 0x 100 1 UNALLOCATED-
00 1x 0xx SME2 multi-vec ternary indexed four registers 16-bit-
00 1x 100 FDOT (2-way, multiple and indexed vector, FP8 to FP16) — Four ZA single-vectorsFEAT_SME_F8F16
00 101 UNALLOCATED-
00 11x UNALLOCATED-
01 0xx SME2 multi-vec ternary indexed four registers 32-bit-
10 00 00x SME2 multi-vec indexed long long MLA four sources 64-bit-
10 01 00x UNALLOCATED-
10 0x 01x UNALLOCATED-
10 1x 00x SME2 multi-vec indexed long FMA four sources-
10 1x 010 FMLAL (multiple and indexed vector, FP8 to FP16) — Four ZA double-vectorsFEAT_SME_F8F16
10 1x 011 UNALLOCATED-
11 0x 00x SME2 multi-vec ternary indexed four registers 64-bit-
11 1x 00x SME2 multi-vec indexed long MLA four sources-
11 01x UNALLOCATED-
!= 00 1xx UNALLOCATED-

SME2 multi-vec indexed long long MLA four sources 32-bit

The encodings in this section are decoded from SME2 Multi-vector - Indexed (Four registers).

313029282726252423222120191817161514131211109876543210
110000010001Zm1Rv0i4hZn0opUSi4lo1
Decode fields Instruction Details Feature
op U S
0 0 0 SMLALL (multiple and indexed vector)FEAT_SME2
0 0 1 SMLSLL (multiple and indexed vector)FEAT_SME2
0 1 0 UMLALL (multiple and indexed vector)FEAT_SME2
0 1 1 UMLSLL (multiple and indexed vector)FEAT_SME2
1 1 UNALLOCATED-
1 0 0 USMLALL (multiple and indexed vector)FEAT_SME2
1 1 0 SUMLALL (multiple and indexed vector)FEAT_SME2

SME2 multi-vec ternary indexed four registers 16-bit

The encodings in this section are decoded from SME2 Multi-vector - Indexed (Four registers).

313029282726252423222120191817161514131211109876543210
110000010001Zm1Rv1i3hZn0opSi3loff3
Decode fields Instruction Details Feature
op S
0 0 FMLA (multiple and indexed vector)FEAT_SME_F16F16
0 1 FMLS (multiple and indexed vector)FEAT_SME_F16F16
1 0 BFMLA (multiple and indexed vector)FEAT_SME_B16B16
1 1 BFMLS (multiple and indexed vector)FEAT_SME_B16B16

SME2 multi-vec ternary indexed four registers 32-bit

The encodings in this section are decoded from SME2 Multi-vector - Indexed (Four registers).

313029282726252423222120191817161514131211109876543210
110000010101Zm1Rvopi2Zn0opc2off3
Decode fields Instruction Details Feature
op opc2
0 000 FMLA (multiple and indexed vector)FEAT_SME2
0 001 FDOT (4-way, multiple and indexed vector)FEAT_SME_F8F32
0 010 FMLS (multiple and indexed vector)FEAT_SME2
0 011 UNALLOCATED-
0 100 SVDOT (4-way)FEAT_SME2
0 101 USVDOTFEAT_SME2
0 110 UVDOT (4-way)FEAT_SME2
0 111 SUVDOTFEAT_SME2
1 000 SDOT (2-way, multiple and indexed vector)FEAT_SME2
1 001 FDOT (2-way, multiple and indexed vector, FP16 to FP32)FEAT_SME2
1 010 UDOT (2-way, multiple and indexed vector)FEAT_SME2
1 011 BFDOT (multiple and indexed vector)FEAT_SME2
1 100 SDOT (4-way, multiple and indexed vector)FEAT_SME2
1 101 USDOT (multiple and indexed vector)FEAT_SME2
1 110 UDOT (4-way, multiple and indexed vector)FEAT_SME2
1 111 SUDOT (multiple and indexed vector)FEAT_SME2

SME2 multi-vec indexed long long MLA four sources 64-bit

The encodings in this section are decoded from SME2 Multi-vector - Indexed (Four registers).

313029282726252423222120191817161514131211109876543210
110000011001Zm1Rv00i3hZn00USi3lo1
Decode fields Instruction Details Feature
U S
0 0 SMLALL (multiple and indexed vector)FEAT_SME2 && FEAT_SME_I16I64
0 1 SMLSLL (multiple and indexed vector)FEAT_SME2 && FEAT_SME_I16I64
1 0 UMLALL (multiple and indexed vector)FEAT_SME2 && FEAT_SME_I16I64
1 1 UMLSLL (multiple and indexed vector)FEAT_SME2 && FEAT_SME_I16I64

SME2 multi-vec indexed long FMA four sources

The encodings in this section are decoded from SME2 Multi-vector - Indexed (Four registers).

313029282726252423222120191817161514131211109876543210
110000011001Zm1Rv1i3hZn00opSi3loff2
Decode fields Instruction Details Feature
op S
0 0 FMLAL (multiple and indexed vector, FP16 to FP32)FEAT_SME2
0 1 FMLSL (multiple and indexed vector)FEAT_SME2
1 0 BFMLAL (multiple and indexed vector)FEAT_SME2
1 1 BFMLSL (multiple and indexed vector)FEAT_SME2

SME2 multi-vec ternary indexed four registers 64-bit

The encodings in this section are decoded from SME2 Multi-vector - Indexed (Four registers).

313029282726252423222120191817161514131211109876543210
110000011101Zm1Rv0opi1Zn00opc2off3
Decode fields Instruction Details Feature
op opc2
0 00 FMLA (multiple and indexed vector)FEAT_SME2 && FEAT_SME_F64F64
0 01 SDOT (4-way, multiple and indexed vector)FEAT_SME2 && FEAT_SME_I16I64
0 10 FMLS (multiple and indexed vector)FEAT_SME2 && FEAT_SME_F64F64
0 11 UDOT (4-way, multiple and indexed vector)FEAT_SME2 && FEAT_SME_I16I64
1 x0 UNALLOCATED-
1 01 SVDOT (4-way)FEAT_SME2 && FEAT_SME_I16I64
1 11 UVDOT (4-way)FEAT_SME2 && FEAT_SME_I16I64

SME2 multi-vec indexed long MLA four sources

The encodings in this section are decoded from SME2 Multi-vector - Indexed (Four registers).

313029282726252423222120191817161514131211109876543210
110000011101Zm1Rv1i3hZn00USi3loff2
Decode fields Instruction Details Feature
U S
0 0 SMLAL (multiple and indexed vector)FEAT_SME2
0 1 SMLSL (multiple and indexed vector)FEAT_SME2
1 0 UMLAL (multiple and indexed vector)FEAT_SME2
1 1 UMLSL (multiple and indexed vector)FEAT_SME2

SME2 Multi-vector - Multiple and Single SVE Destructive (Two registers)

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
110000011010100op0op1op2
Decode fieldsInstruction details
op0op1op2
0 00 00x SME2 single-multi int min/max two registers
0 00 101 UNALLOCATED
0 01 00x SME2 single-multi FP min/max two registers
0 01 100 SME2 multiple and single vector FSCALE two registers
0 01 101 UNALLOCATED
0 0x x1x UNALLOCATED
0 10 SME2 single-multi shift two registers
0 11 000 SME2 single-multi add two registers
0 11 != 000 UNALLOCATED
1 00 000 SME2 single-multi signed saturating doubling multiply high two registers
1 00 x10 UNALLOCATED
1 00 xx1 UNALLOCATED
1 != 00 UNALLOCATED
00 100 UNALLOCATED

SME2 single-multi int min/max two registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single SVE Destructive (Two registers).

313029282726252423222120191817161514131211109876543210
11000001size10Zm1010000000opZdnU
Decode fields Instruction Details Feature
op U
0 0 SMAX (multiple and single vector)FEAT_SME2
0 1 UMAX (multiple and single vector)FEAT_SME2
1 0 SMIN (multiple and single vector)FEAT_SME2
1 1 UMIN (multiple and single vector)FEAT_SME2

SME2 single-multi FP min/max two registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single SVE Destructive (Two registers).

313029282726252423222120191817161514131211109876543210
11000001size10Zm1010000100opZdno2
Decode fields Instruction Details Feature
size op o2
00 0 0 BFMAX (multiple and single vector)FEAT_SME2 && FEAT_SVE_B16B16
00 0 1 BFMIN (multiple and single vector)FEAT_SME2 && FEAT_SVE_B16B16
00 1 0 BFMAXNM (multiple and single vector)FEAT_SME2 && FEAT_SVE_B16B16
00 1 1 BFMINNM (multiple and single vector)FEAT_SME2 && FEAT_SVE_B16B16
!= 00 0 0 FMAX (multiple and single vector)FEAT_SME2
!= 00 0 1 FMIN (multiple and single vector)FEAT_SME2
!= 00 1 0 FMAXNM (multiple and single vector)FEAT_SME2
!= 00 1 1 FMINNM (multiple and single vector)FEAT_SME2

SME2 multiple and single vector FSCALE two registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single SVE Destructive (Two registers).

313029282726252423222120191817161514131211109876543210
11000001size10Zm10100001100Zdnop
Decode fields Instruction Details Feature
size op
1 UNALLOCATED-
00 0 BFSCALE (multiple and single vector)FEAT_SME2 && FEAT_SVE_BFSCALE
!= 00 0 FSCALE (multiple and single vector)FEAT_SME2 && FEAT_FP8

SME2 single-multi shift two registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single SVE Destructive (Two registers).

313029282726252423222120191817161514131211109876543210
11000001size10Zm10100010opcZdnU
Decode fields Instruction Details Feature
opc U
001 0 SRSHL (multiple and single vector)FEAT_SME2
001 1 URSHL (multiple and single vector)FEAT_SME2
!= 001 UNALLOCATED-

SME2 single-multi add two registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single SVE Destructive (Two registers).

313029282726252423222120191817161514131211109876543210
11000001size10Zm10100011000Zdnop
Decode fields Instruction Details Feature
op
0 ADD (to vector)FEAT_SME2
1 UNALLOCATED-

SME2 single-multi signed saturating doubling multiply high two registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single SVE Destructive (Two registers).

313029282726252423222120191817161514131211109876543210
11000001size10Zm10100100000Zdnop
Decode fields Instruction Details Feature
op
0 SQDMULH (multiple and single vector)FEAT_SME2
1 UNALLOCATED-

SME2 Multi-vector - Multiple and Single SVE Destructive (Four registers)

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
110000011010101op0op1op20
Decode fieldsInstruction details
op0op1op2
0 00 00x SME2 single-multi int min/max four registers
0 00 101 UNALLOCATED
0 01 00x SME2 single-multi FP min/max four registers
0 01 100 SME2 multiple and single vector FSCALE four registers
0 01 101 UNALLOCATED
0 0x x1x UNALLOCATED
0 10 SME2 single-multi shift four registers
0 11 000 SME2 single-multi add four registers
0 11 != 000 UNALLOCATED
1 00 000 SME2 single-multi signed saturating doubling multiply high four registers
1 00 x10 UNALLOCATED
1 00 xx1 UNALLOCATED
1 != 00 UNALLOCATED
00 100 UNALLOCATED

SME2 single-multi int min/max four registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single SVE Destructive (Four registers).

313029282726252423222120191817161514131211109876543210
11000001size10Zm1010100000opZdn0U
Decode fields Instruction Details Feature
op U
0 0 SMAX (multiple and single vector)FEAT_SME2
0 1 UMAX (multiple and single vector)FEAT_SME2
1 0 SMIN (multiple and single vector)FEAT_SME2
1 1 UMIN (multiple and single vector)FEAT_SME2

SME2 single-multi FP min/max four registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single SVE Destructive (Four registers).

313029282726252423222120191817161514131211109876543210
11000001size10Zm1010100100opZdn0o2
Decode fields Instruction Details Feature
size op o2
00 0 0 BFMAX (multiple and single vector)FEAT_SME2 && FEAT_SVE_B16B16
00 0 1 BFMIN (multiple and single vector)FEAT_SME2 && FEAT_SVE_B16B16
00 1 0 BFMAXNM (multiple and single vector)FEAT_SME2 && FEAT_SVE_B16B16
00 1 1 BFMINNM (multiple and single vector)FEAT_SME2 && FEAT_SVE_B16B16
!= 00 0 0 FMAX (multiple and single vector)FEAT_SME2
!= 00 0 1 FMIN (multiple and single vector)FEAT_SME2
!= 00 1 0 FMAXNM (multiple and single vector)FEAT_SME2
!= 00 1 1 FMINNM (multiple and single vector)FEAT_SME2

SME2 multiple and single vector FSCALE four registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single SVE Destructive (Four registers).

313029282726252423222120191817161514131211109876543210
11000001size10Zm10101001100Zdn0op
Decode fields Instruction Details Feature
size op
1 UNALLOCATED-
00 0 BFSCALE (multiple and single vector)FEAT_SME2 && FEAT_SVE_BFSCALE
!= 00 0 FSCALE (multiple and single vector)FEAT_SME2 && FEAT_FP8

SME2 single-multi shift four registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single SVE Destructive (Four registers).

313029282726252423222120191817161514131211109876543210
11000001size10Zm10101010opcZdn0U
Decode fields Instruction Details Feature
opc U
001 0 SRSHL (multiple and single vector)FEAT_SME2
001 1 URSHL (multiple and single vector)FEAT_SME2
!= 001 UNALLOCATED-

SME2 single-multi add four registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single SVE Destructive (Four registers).

313029282726252423222120191817161514131211109876543210
11000001size10Zm10101011000Zdn0op
Decode fields Instruction Details Feature
op
0 ADD (to vector)FEAT_SME2
1 UNALLOCATED-

SME2 single-multi signed saturating doubling multiply high four registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple and Single SVE Destructive (Four registers).

313029282726252423222120191817161514131211109876543210
11000001size10Zm10101100000Zdn0op
Decode fields Instruction Details Feature
op
0 SQDMULH (multiple and single vector)FEAT_SME2
1 UNALLOCATED-

SME2 Multi-vector - Multiple Vectors SVE Destructive (Four registers)

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
11000001100101110op00
Decode fieldsInstruction details
op0
000 SME2 multiple vectors int min/max four registers
001 UNALLOCATED
010 SME2 multiple vectors FP min/max four registers
011 SME2 multiple vectors FSCALE four registers
10x SME2 multiple vectors shift four registers
11x UNALLOCATED

SME2 multiple vectors int min/max four registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Vectors SVE Destructive (Four registers).

313029282726252423222120191817161514131211109876543210
11000001size1Zm00101110000opcZdn0U
Decode fields Instruction Details Feature
opc U
00 0 SMAX (multiple vectors)FEAT_SME2
00 1 UMAX (multiple vectors)FEAT_SME2
01 0 SMIN (multiple vectors)FEAT_SME2
01 1 UMIN (multiple vectors)FEAT_SME2
1x UNALLOCATED-

SME2 multiple vectors FP min/max four registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Vectors SVE Destructive (Four registers).

313029282726252423222120191817161514131211109876543210
11000001size1Zm00101110010opcZdn0o2
Decode fields Instruction Details Feature
size opc o2
10 0 FAMAXFEAT_SME2 && FEAT_FAMINMAX
10 1 FAMINFEAT_SME2 && FEAT_FAMINMAX
11 UNALLOCATED-
00 00 0 BFMAX (multiple vectors)FEAT_SME2 && FEAT_SVE_B16B16
00 00 1 BFMIN (multiple vectors)FEAT_SME2 && FEAT_SVE_B16B16
00 01 0 BFMAXNM (multiple vectors)FEAT_SME2 && FEAT_SVE_B16B16
00 01 1 BFMINNM (multiple vectors)FEAT_SME2 && FEAT_SVE_B16B16
!= 00 00 0 FMAX (multiple vectors)FEAT_SME2
!= 00 00 1 FMIN (multiple vectors)FEAT_SME2
!= 00 01 0 FMAXNM (multiple vectors)FEAT_SME2
!= 00 01 1 FMINNM (multiple vectors)FEAT_SME2

SME2 multiple vectors FSCALE four registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Vectors SVE Destructive (Four registers).

313029282726252423222120191817161514131211109876543210
11000001size1Zm00101110011opcZdn0o2
Decode fields Instruction Details Feature
size opc o2
00 1 UNALLOCATED-
!= 00 UNALLOCATED-
00 00 0 BFSCALE (multiple vectors)FEAT_SME2 && FEAT_SVE_BFSCALE
!= 00 00 0 FSCALE (multiple vectors)FEAT_SME2 && FEAT_FP8

SME2 multiple vectors shift four registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Vectors SVE Destructive (Four registers).

313029282726252423222120191817161514131211109876543210
11000001size1Zm0010111010opcZdn0U
Decode fields Instruction Details Feature
opc U
001 0 SRSHL (multiple vectors)FEAT_SME2
001 1 URSHL (multiple vectors)FEAT_SME2
!= 001 UNALLOCATED-

SME2 Multi-vector - Multiple Vectors SVE Saturating Multiply (Four registers)

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
11000001100101111op00
Decode fieldsInstruction details
op0
00000 SME2 multi-vector signed saturating doubling multiply high four registers
!= 00000 UNALLOCATED

SME2 multi-vector signed saturating doubling multiply high four registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Vectors SVE Saturating Multiply (Four registers).

313029282726252423222120191817161514131211109876543210
11000001size1Zm0010111100000Zdn0op
Decode fields Instruction Details Feature
op
0 SQDMULH (multiple vectors)FEAT_SME2
1 UNALLOCATED-

SME2 Multi-vector - Multiple Vectors SVE Destructive (Two registers)

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
1100000110101100op0
Decode fieldsInstruction details
op0
000 SME2 multiple vectors int min/max two registers
001 UNALLOCATED
010 SME2 multiple vectors FP min/max two registers
011 SME2 multiple vectors FSCALE two registers
10x SME2 multiple vectors shift two registers
11x UNALLOCATED

SME2 multiple vectors int min/max two registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Vectors SVE Destructive (Two registers).

313029282726252423222120191817161514131211109876543210
11000001size1Zm0101100000opcZdnU
Decode fields Instruction Details Feature
opc U
00 0 SMAX (multiple vectors)FEAT_SME2
00 1 UMAX (multiple vectors)FEAT_SME2
01 0 SMIN (multiple vectors)FEAT_SME2
01 1 UMIN (multiple vectors)FEAT_SME2
1x UNALLOCATED-

SME2 multiple vectors FP min/max two registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Vectors SVE Destructive (Two registers).

313029282726252423222120191817161514131211109876543210
11000001size1Zm0101100010opcZdno2
Decode fields Instruction Details Feature
size opc o2
10 0 FAMAXFEAT_SME2 && FEAT_FAMINMAX
10 1 FAMINFEAT_SME2 && FEAT_FAMINMAX
11 UNALLOCATED-
00 00 0 BFMAX (multiple vectors)FEAT_SME2 && FEAT_SVE_B16B16
00 00 1 BFMIN (multiple vectors)FEAT_SME2 && FEAT_SVE_B16B16
00 01 0 BFMAXNM (multiple vectors)FEAT_SME2 && FEAT_SVE_B16B16
00 01 1 BFMINNM (multiple vectors)FEAT_SME2 && FEAT_SVE_B16B16
!= 00 00 0 FMAX (multiple vectors)FEAT_SME2
!= 00 00 1 FMIN (multiple vectors)FEAT_SME2
!= 00 01 0 FMAXNM (multiple vectors)FEAT_SME2
!= 00 01 1 FMINNM (multiple vectors)FEAT_SME2

SME2 multiple vectors FSCALE two registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Vectors SVE Destructive (Two registers).

313029282726252423222120191817161514131211109876543210
11000001size1Zm0101100011opcZdno2
Decode fields Instruction Details Feature
size opc o2
00 1 UNALLOCATED-
!= 00 UNALLOCATED-
00 00 0 BFSCALE (multiple vectors)FEAT_SME2 && FEAT_SVE_BFSCALE
!= 00 00 0 FSCALE (multiple vectors)FEAT_SME2 && FEAT_FP8

SME2 multiple vectors shift two registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Vectors SVE Destructive (Two registers).

313029282726252423222120191817161514131211109876543210
11000001size1Zm010110010opcZdnU
Decode fields Instruction Details Feature
opc U
001 0 SRSHL (multiple vectors)FEAT_SME2
001 1 URSHL (multiple vectors)FEAT_SME2
!= 001 UNALLOCATED-

SME2 Multi-vector - Multiple Vectors SVE Saturating Multiply (Two registers)

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
1100000110101101op0
Decode fieldsInstruction details
op0
00000 SME2 multi-vector signed saturating doubling multiply high two registers
!= 00000 UNALLOCATED

SME2 multi-vector signed saturating doubling multiply high two registers

The encodings in this section are decoded from SME2 Multi-vector - Multiple Vectors SVE Saturating Multiply (Two registers).

313029282726252423222120191817161514131211109876543210
11000001size1Zm010110100000Zdnop
Decode fields Instruction Details Feature
op
0 SQDMULH (multiple vectors)FEAT_SME2
1 UNALLOCATED-

SME2 Multi-vector - SVE Select

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
110000011op0100op1op2
Decode fieldsInstruction detailsFeature
op0op1op2
01 00 00 SEL — Four registersFEAT_SME2
01 00 10 UNALLOCATED-
01 10 x0 UNALLOCATED-
11 x0 x0 UNALLOCATED-
x0 x0 x0 SEL — Two registersFEAT_SME2
x0 x1 UNALLOCATED-
x1 UNALLOCATED-

SME2 Multi-vector - SVE Constructive Binary

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
11000001op01110op1op2
Decode fieldsInstruction details
op0op1op2
00 101 SME2 multi-vec quadwords ZIP two registers
01 101 UNALLOCATED
10 101 UNALLOCATED
11 101 SME2 multi-vec saturating shift right narrow two registers
000 SME2 multi-vec FCLAMP two registers
001 SME2 multi-vec CLAMP two registers
010 0 SME2 multi-vec FCLAMP four registers
011 0 SME2 multi-vec CLAMP four registers
01x 1 UNALLOCATED
100 SME2 multi-vec ZIP two registers
11x SME2 multi-vec saturating shift right narrow four registers

SME2 multi-vec quadwords ZIP two registers

The encodings in this section are decoded from SME2 Multi-vector - SVE Constructive Binary.

313029282726252423222120191817161514131211109876543210
11000001001Zm110101ZnZdop
Decode fields Instruction Details Feature
op
0 ZIP (two registers)FEAT_SME2
1 UZP (two registers)FEAT_SME2

SME2 multi-vec saturating shift right narrow two registers

The encodings in this section are decoded from SME2 Multi-vector - SVE Constructive Binary.

313029282726252423222120191817161514131211109876543210
11000001111opimm4110101ZnUZd
Decode fields Instruction Details Feature
op U
0 0 SQRSHR (two registers)FEAT_SME2
0 1 UQRSHR (two registers)FEAT_SME2
1 0 SQRSHRU (two registers)FEAT_SME2
1 1 UNALLOCATED-

SME2 multi-vec FCLAMP two registers

The encodings in this section are decoded from SME2 Multi-vector - SVE Constructive Binary.

313029282726252423222120191817161514131211109876543210
11000001size1Zm110000ZnZdop
Decode fields Instruction Details Feature
size op
1 UNALLOCATED-
00 0 BFCLAMPFEAT_SME2 && FEAT_SVE_B16B16
!= 00 0 FCLAMPFEAT_SME2

SME2 multi-vec CLAMP two registers

The encodings in this section are decoded from SME2 Multi-vector - SVE Constructive Binary.

313029282726252423222120191817161514131211109876543210
11000001size1Zm110001ZnZdU
Decode fields Instruction Details Feature
U
0 SCLAMPFEAT_SME2
1 UCLAMPFEAT_SME2

SME2 multi-vec FCLAMP four registers

The encodings in this section are decoded from SME2 Multi-vector - SVE Constructive Binary.

313029282726252423222120191817161514131211109876543210
11000001size1Zm110010ZnZd0op
Decode fields Instruction Details Feature
size op
1 UNALLOCATED-
00 0 BFCLAMPFEAT_SME2 && FEAT_SVE_B16B16
!= 00 0 FCLAMPFEAT_SME2

SME2 multi-vec CLAMP four registers

The encodings in this section are decoded from SME2 Multi-vector - SVE Constructive Binary.

313029282726252423222120191817161514131211109876543210
11000001size1Zm110011ZnZd0U
Decode fields Instruction Details Feature
U
0 SCLAMPFEAT_SME2
1 UCLAMPFEAT_SME2

SME2 multi-vec ZIP two registers

The encodings in this section are decoded from SME2 Multi-vector - SVE Constructive Binary.

313029282726252423222120191817161514131211109876543210
11000001size1Zm110100ZnZdop
Decode fields Instruction Details Feature
op
0 ZIP (two registers)FEAT_SME2
1 UZP (two registers)FEAT_SME2

SME2 multi-vec saturating shift right narrow four registers

The encodings in this section are decoded from SME2 Multi-vector - SVE Constructive Binary.

313029282726252423222120191817161514131211109876543210
11000001tsize1imm511011NZnopUZd
Decode fields Instruction Details Feature
N op U
1 1 UNALLOCATED-
0 0 0 SQRSHR (four registers)FEAT_SME2
0 0 1 UQRSHR (four registers)FEAT_SME2
0 1 0 SQRSHRU (four registers)FEAT_SME2
1 0 0 SQRSHRNFEAT_SME2
1 0 1 UQRSHRNFEAT_SME2
1 1 0 SQRSHRUNFEAT_SME2

SME2 Multi-vector - SVE Constructive Unary

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
11000001op01op1op2111000op3op4
Decode fieldsInstruction details
op0op1op2op3op4
00 000 01 x0 SME2 multi-vec FP to int convert two registers
00 000 10 x0 SME2 multi-vec int to FP two registers
00 001 11 UNALLOCATED
00 100 01 0x 00 SME2 multi-vec FP to int convert four registers
00 100 10 0x 00 SME2 multi-vec int to FP four registers
00 101 00 0x SME2 multi-vec FP8 down convert four registers
00 101 11 00 x0 SME2 multi-vec quadwords ZIP four registers
01 000 01 x0 UNALLOCATED
01 101 00 0x 1x UNALLOCATED
01 10x 00 0x 0x UNALLOCATED
0x 000 00 SME2 multi-vec FP down convert two registers
0x 000 11 SME2 multi-vec int down convert two registers
0x 001 00 x0 SME2 multi-vec FP8 down convert two registers
0x 001 00 x1 UNALLOCATED
10 000 00 SME2 multi-vec convert two registers
10 001 00 1x UNALLOCATED
10 x01 00 0x UNALLOCATED
11 00x 00 UNALLOCATED
11 101 00 0x 1x UNALLOCATED
11 10x 00 0x 0x UNALLOCATED
1x 000 11 x1 UNALLOCATED
1x 000 x1 x0 UNALLOCATED
x0 100 00 0x 0x UNALLOCATED
000 01 x1 UNALLOCATED
000 10 x1 UNALLOCATED
001 01 SME2 multi-vec unpack two registers
001 10 SME2 multi-vec FP8 up convert two registers
01x x0 x0 SME2 multi-vec FRINT two registers
100 01 0x 01 UNALLOCATED
100 01 1x UNALLOCATED
100 10 0x 01 UNALLOCATED
100 11 SME2 multi-vec int down convert four registers
100 != 11 0x 1x UNALLOCATED
101 01 x0 0x SME2 multi-vec unpack four registers
101 01 x0 1x UNALLOCATED
101 01 x1 UNALLOCATED
101 10 00 x0 SME2 multi-vec ZIP four registers
101 11 1x UNALLOCATED
101 1x 00 x1 UNALLOCATED
101 1x 01 UNALLOCATED
10x x0 1x UNALLOCATED
11x 00 00 SME2 multi-vec FRINT four registers
11x 00 10 UNALLOCATED
11x 10 x0 UNALLOCATED
x1x x0 x1 UNALLOCATED
x1x x1 UNALLOCATED
!= 00 000 10 x0 UNALLOCATED
!= 00 001 11 UNALLOCATED
!= 00 100 01 0x 00 UNALLOCATED
!= 00 100 10 0x 00 UNALLOCATED
!= 00 101 11 00 x0 UNALLOCATED

SME2 multi-vec FP to int convert two registers

The encodings in this section are decoded from SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
1100000100100001111000ZnUZd0
Decode fields Instruction Details Feature
U
0 FCVTZSFEAT_SME2
1 FCVTZUFEAT_SME2

SME2 multi-vec int to FP two registers

The encodings in this section are decoded from SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
1100000100100010111000ZnUZd0
Decode fields Instruction Details Feature
U
0 SCVTFFEAT_SME2
1 UCVTFFEAT_SME2

SME2 multi-vec FP to int convert four registers

The encodings in this section are decoded from SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
1100000100110001111000Zn0UZd00
Decode fields Instruction Details Feature
U
0 FCVTZSFEAT_SME2
1 FCVTZUFEAT_SME2

SME2 multi-vec int to FP four registers

The encodings in this section are decoded from SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
1100000100110010111000Zn0UZd00
Decode fields Instruction Details Feature
U
0 SCVTFFEAT_SME2
1 UCVTFFEAT_SME2

SME2 multi-vec FP8 down convert four registers

The encodings in this section are decoded from SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
1100000100110100111000Zn0NZd
Decode fields Instruction Details Feature
N
0 FCVT (narrowing, FP32 to FP8)FEAT_SME2 && FEAT_FP8
1 FCVTN (FP32 to FP8)FEAT_SME2 && FEAT_FP8

SME2 multi-vec quadwords ZIP four registers

The encodings in this section are decoded from SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
1100000100110111111000Zn00Zdop0
Decode fields Instruction Details Feature
op
0 ZIP (four registers)FEAT_SME2
1 UZP (four registers)FEAT_SME2

SME2 multi-vec FP down convert two registers

The encodings in this section are decoded from SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
110000010op100000111000ZnNZd
Decode fields Instruction Details Feature
op N
0 0 FCVT (narrowing, FP32 to FP16)FEAT_SME2
0 1 FCVTN (FP32 to FP16)FEAT_SME2
1 0 BFCVTFEAT_SME2
1 1 BFCVTNFEAT_SME2

SME2 multi-vec int down convert two registers

The encodings in this section are decoded from SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
110000010op100011111000ZnUZd
Decode fields Instruction Details Feature
op U
0 0 SQCVT (two registers)FEAT_SME2
0 1 UQCVT (two registers)FEAT_SME2
1 0 SQCVTU (two registers)FEAT_SME2
1 1 UNALLOCATED-

SME2 multi-vec FP8 down convert two registers

The encodings in this section are decoded from SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
110000010op100100111000Zn0Zd
Decode fields Instruction Details Feature
op
0 FCVT (narrowing, FP16 to FP8)FEAT_SME2 && FEAT_FP8
1 BFCVTFEAT_SME2 && FEAT_FP8

SME2 multi-vec convert two registers

The encodings in this section are decoded from SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
1100000110100000111000ZnZdL
Decode fields Instruction Details Feature
L
0 FCVT (widening)FEAT_SME_F16F16
1 FCVTLFEAT_SME_F16F16

SME2 multi-vec unpack two registers

The encodings in this section are decoded from SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
11000001size100101111000ZnZdU
Decode fields Instruction Details Feature
U
0 SUNPKFEAT_SME2
1 UUNPKFEAT_SME2

SME2 multi-vec FP8 up convert two registers

The encodings in this section are decoded from SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
11000001opc100110111000ZnZdL
Decode fields Instruction Details Feature
opc L
00 0 F1CVT, F2CVT — F1CVTFEAT_SME2 && FEAT_FP8
00 1 F1CVTL, F2CVTL — F1CVTLFEAT_SME2 && FEAT_FP8
01 0 BF1CVT, BF2CVT — BF1CVTFEAT_SME2 && FEAT_FP8
01 1 BF1CVTL, BF2CVTL — BF1CVTLFEAT_SME2 && FEAT_FP8
10 0 F1CVT, F2CVT — F2CVTFEAT_SME2 && FEAT_FP8
10 1 F1CVTL, F2CVTL — F2CVTLFEAT_SME2 && FEAT_FP8
11 0 BF1CVT, BF2CVT — BF2CVTFEAT_SME2 && FEAT_FP8
11 1 BF1CVTL, BF2CVTL — BF2CVTLFEAT_SME2 && FEAT_FP8

SME2 multi-vec FRINT two registers

The encodings in this section are decoded from SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
11000001size101opc111000Zn0Zd0
Decode fields Instruction Details Feature
size opc
10 000 FRINTNFEAT_SME2
10 001 FRINTPFEAT_SME2
10 010 FRINTMFEAT_SME2
10 011 UNALLOCATED-
10 100 FRINTAFEAT_SME2
10 101 UNALLOCATED-
10 11x UNALLOCATED-
!= 10 UNALLOCATED-

SME2 multi-vec int down convert four registers

The encodings in this section are decoded from SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
11000001szop110011111000ZnNUZd
Decode fields Instruction Details Feature
op N U
0 0 0 SQCVT (four registers)FEAT_SME2
0 0 1 UQCVT (four registers)FEAT_SME2
0 1 0 SQCVTNFEAT_SME2
0 1 1 UQCVTNFEAT_SME2
1 1 UNALLOCATED-
1 0 0 SQCVTU (four registers)FEAT_SME2
1 1 0 SQCVTUNFEAT_SME2

SME2 multi-vec unpack four registers

The encodings in this section are decoded from SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
11000001size110101111000Zn0Zd0U
Decode fields Instruction Details Feature
U
0 SUNPKFEAT_SME2
1 UUNPKFEAT_SME2

SME2 multi-vec ZIP four registers

The encodings in this section are decoded from SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
11000001size110110111000Zn00Zdop0
Decode fields Instruction Details Feature
op
0 ZIP (four registers)FEAT_SME2
1 UZP (four registers)FEAT_SME2

SME2 multi-vec FRINT four registers

The encodings in this section are decoded from SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
11000001size111opc111000Zn00Zd00
Decode fields Instruction Details Feature
size opc
10 000 FRINTNFEAT_SME2
10 001 FRINTPFEAT_SME2
10 010 FRINTMFEAT_SME2
10 011 UNALLOCATED-
10 100 FRINTAFEAT_SME2
10 101 UNALLOCATED-
10 11x UNALLOCATED-
!= 10 UNALLOCATED-

SME2 Multi-vector - FP Multiply

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
110000011op0111001op10op20
Decode fieldsInstruction details
op0op1op2
01 0 0 SME2 multi-vec FP multiply (four registers)
01 0 1 UNALLOCATED
01 1 UNALLOCATED
11 UNALLOCATED
x0 SME2 multi-vec FP multiply (two registers)

SME2 multi-vec FP multiply (four registers)

The encodings in this section are decoded from SME2 Multi-vector - FP Multiply.

313029282726252423222120191817161514131211109876543210
11000001size1Zm01111001Zn00Zd00
Decode fields Instruction Details Feature
size
00 BFMUL (multiple vectors)FEAT_SME2 && FEAT_SVE_BFSCALE
!= 00 FMUL (multiple vectors)FEAT_SME2p2

SME2 multi-vec FP multiply (two registers)

The encodings in this section are decoded from SME2 Multi-vector - FP Multiply.

313029282726252423222120191817161514131211109876543210
11000001size1Zm0111001Zn0Zd0
Decode fields Instruction Details Feature
size
00 BFMUL (multiple vectors)FEAT_SME2 && FEAT_SVE_BFSCALE
!= 00 FMUL (multiple vectors)FEAT_SME2p2

SME2 Multiple and Single Vector - FP multiply

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
110000011op0111010op10op20
Decode fieldsInstruction details
op0op1op2
0 SME2 multiple and single vector FP multiply (two registers)
1 0 0 SME2 multiple and single vector FP multiply (four registers)
1 0 1 UNALLOCATED
1 1 UNALLOCATED

SME2 multiple and single vector FP multiply (two registers)

The encodings in this section are decoded from SME2 Multiple and Single Vector - FP multiply.

313029282726252423222120191817161514131211109876543210
11000001size1Zm0111010Zn0Zd0
Decode fields Instruction Details Feature
size
00 BFMUL (multiple and single vector)FEAT_SME2 && FEAT_SVE_BFSCALE
!= 00 FMUL (multiple and single vector)FEAT_SME2p2

SME2 multiple and single vector FP multiply (four registers)

The encodings in this section are decoded from SME2 Multiple and Single Vector - FP multiply.

313029282726252423222120191817161514131211109876543210
11000001size1Zm1111010Zn00Zd00
Decode fields Instruction Details Feature
size
00 BFMUL (multiple and single vector)FEAT_SME2 && FEAT_SVE_BFSCALE
!= 00 FMUL (multiple and single vector)FEAT_SME2p2

SME Memory

The encodings in this section are decoded from SME encodings.

313029282726252423222120191817161514131211109876543210
1110000op0op1op2op3op4
Decode fieldsInstruction detailsFeature
op0op1op2op3op4
0xx0 0xx SME load array vector (elements)-
0xx1 0xx SME store array vector (elements)-
100x 00000 0 xx000 0xx SME save and restore array-
100x 1 00000 000 SME2 lookup table load/store-
100x 1 00000 001 UNALLOCATED-
100x 1 00000 01x UNALLOCATED-
100x 1 01000 0xx UNALLOCATED-
100x 1 1x000 0xx UNALLOCATED-
100x xx001 0xx UNALLOCATED-
100x xx01x 0xx UNALLOCATED-
100x xx1xx 0xx UNALLOCATED-
100x != 00000 0 xx000 0xx UNALLOCATED-
101x 0xx UNALLOCATED-
110x 0xx UNALLOCATED-
1110 0xx LD1QFEAT_SME
1111 0xx ST1QFEAT_SME
1xx UNALLOCATED-

SME load array vector (elements)

The encodings in this section are decoded from SME Memory.

313029282726252423222120191817161514131211109876543210
11100000msz0RmVRsPgRn0opc
Decode fields Instruction Details Feature
msz
00 LD1B (scalar plus scalar, tile slice)FEAT_SME
01 LD1H (scalar plus scalar, tile slice)FEAT_SME
10 LD1W (scalar plus scalar, tile slice)FEAT_SME
11 LD1D (scalar plus scalar, tile slice)FEAT_SME

SME store array vector (elements)

The encodings in this section are decoded from SME Memory.

313029282726252423222120191817161514131211109876543210
11100000msz1RmVRsPgRn0opc
Decode fields Instruction Details Feature
msz
00 ST1B (scalar plus scalar, tile slice)FEAT_SME
01 ST1H (scalar plus scalar, tile slice)FEAT_SME
10 ST1W (scalar plus scalar, tile slice)FEAT_SME
11 ST1D (scalar plus scalar, tile slice)FEAT_SME

SME save and restore array

The encodings in this section are decoded from SME Memory.

313029282726252423222120191817161514131211109876543210
1110000100op000000Rv000Rn0imm4
Decode fields Instruction Details Feature
op
0 LDR (array vector)FEAT_SME
1 STR (array vector)FEAT_SME

SME2 lookup table load/store

The encodings in this section are decoded from SME Memory.

313029282726252423222120191817161514131211109876543210
1110000100opc100000Rn000opc2
Decode fields Instruction Details Feature
opc opc2
x0xxxx UNALLOCATED-
x10xxx UNALLOCATED-
x110xx UNALLOCATED-
x1110x UNALLOCATED-
x11110 UNALLOCATED-
x11111 != 00 UNALLOCATED-
011111 00 LDR (table)FEAT_SME2
111111 00 STR (table)FEAT_SME2

SVE encodings

The encodings in this section are decoded from A64 instruction set encoding.

313029282726252423222120191817161514131211109876543210
op00010op1op2op3
Decode fieldsInstruction detailsFeature
op0op1op2op3
000 0xx0xxxx 000xxx SVE Integer Binary Arithmetic - Predicated-
000 0xx0xxxx 001xxx SVE Integer Reduction-
000 0xx0xxxx 100xxx SVE Bitwise Shift - Predicated-
000 0xx0xxxx 101xxx SVE Integer Unary Arithmetic - Predicated-
000 0xx0xxxx x1xxxx SVE Integer Multiply-Add - Predicated-
000 0xx1xxxx 001xxx SVE Bitwise Logical - Unpredicated-
000 0xx1xxxx 0100xx SVE Index Generation-
000 0xx1xxxx 0101xx SVE Stack Allocation-
000 0xx1xxxx 011xxx SVE2 Integer Multiply - Unpredicated-
000 0xx1xxxx 100xxx SVE Bitwise Shift - Unpredicated-
000 0xx1xxxx 1011xx SVE Integer Misc - Unpredicated-
000 0xx1xxxx 11xxxx SVE Element Count-
000 10x1xxxx 000xxx SVE Permute Vector - Extract-
000 11x1xxxx 000xxx SVE Permute Vector - Segments-
000 1xx00xxx SVE Bitwise Immediate-
000 1xx01xxx SVE Integer Wide Immediate - Predicated-
000 1xx1xxxx 001001 SVE Permute Vector - One Source Quadwords-
000 1xx1xxxx 001110 SVE Permute Vector - Unpredicated-
000 1xx1xxxx 001111 UNALLOCATED-
000 1xx1xxxx 010xxx SVE Permute Predicate-
000 1xx1xxxx 10xxxx SVE Permute Vector - Predicated-
001 0xx0xxxx SVE Integer Compare - Vectors-
001 1xx00xxx 11xxxx SVE Propagate Break-
001 1xx01xxx 01xxxx SVE Partition Break-
001 1xx01xxx 11xxxx SVE Predicate Misc-
001 1xx100xx 10xxxx SVE Predicate Count-
001 1xx101xx 1000xx SVE Inc/Dec by Predicate Count-
001 1xx101xx 1001xx SVE Write FFR-
001 1xx101xx 101xxx UNALLOCATED-
001 1xx11xxx 10xxxx UNALLOCATED-
001 1xx1xxxx 00xxxx SVE Integer Compare - Scalars-
001 1xx1xxxx 01xxxx 1 SVE Scalar Integer Compare - Predicate-as-counter-
001 1xx1xxxx 11xxxx SVE Integer Wide Immediate - Unpredicated-
010 0x10xxxx 11001x UNALLOCATED-
010 0xx0xxxx 0xxxxx SVE Integer Multiply-Add - Unpredicated-
010 0xx0xxxx 10xxxx SVE2 Integer - Predicated-
010 0xx1xxxx SVE Multiply - Indexed-
010 1xx0xxxx 0xxxxx SVE2 Widening Integer Arithmetic-
010 1xx0xxxx 10xxxx SVE Misc-
010 1xx0xxxx 11xxxx SVE2 Accumulate-
010 1xx1xxxx 0xxxxx SVE2 Narrowing-
010 1xx1xxxx 101xxx SVE2 Histogram Computation (Segment) and Lookup Table-
010 1xx1xxxx 111xxx SVE2 Crypto Extensions-
011 01x1xxxx 111000 UNALLOCATED-
011 0x01xxxx 0111xx UNALLOCATED-
011 0x01xxxx 10xx10 SVE2 FP8 widening multiply-add-
011 0x01xxxx 10xx11 UNALLOCATED-
011 0x01xxxx 11x1xx UNALLOCATED-
011 0x11xxxx 10xx1x UNALLOCATED-
011 0x11xxxx x1x1xx UNALLOCATED-
011 0xx00001 100xxx UNALLOCATED-
011 0xx0010x 100xxx UNALLOCATED-
011 0xx00x0x 11xxxx UNALLOCATED-
011 0xx00x1x 1xxxxx UNALLOCATED-
011 0xx010xx 11xxxx UNALLOCATED-
011 0xx011xx 1xxxxx SVE2 floating-point unary operations - zeroing predicated-
011 0xx1xxxx 001011 UNALLOCATED-
011 0xx1xxxx 0011xx UNALLOCATED-
011 0xx1xxxx 01x0xx SVE floating-point widening multiply-add - indexed-
011 0xx1xxxx 10x00x SVE floating-point widening multiply-add-
011 0xx1xxxx 10x10x UNALLOCATED-
011 0xx1xxxx 11101x UNALLOCATED-
011 1xx001xx 0010xx UNALLOCATED-
011 1xx001xx 0011xx SVE floating-point unary operations - unpredicated-
011 1xx010xx 001xxx SVE floating-point compare - with zero-
011 1xx011xx 001xxx SVE floating-point accumulating reduction-
011 1xx0xxxx 100xxx SVE floating-point arithmetic - predicated-
011 1xx0xxxx 101xxx SVE floating-point unary operations - merging predicated-
011 1xx1xxxx SVE floating-point multiply-add-
100 SVE Memory - 32-bit Gather and Unsized Contiguous-
101 SVE Memory - Contiguous Load-
110 SVE Memory - 64-bit Gather-
111 001xxx SVE Memory - Non-temporal and Quadword Scatter Store-
111 011xxx SVE Memory - Non-temporal and Multi-register Contiguous Store-
111 0x0xxx SVE Memory - Contiguous Store and Unsized Contiguous-
111 101xxx SVE Memory - Scatter-
111 111xxx SVE Memory - Contiguous Store with Immediate Offset-
111 1x0xxx SVE Memory - Scatter with Optional Sign Extend-
000 0xx1xxxx 000xxx SVE integer add/subtract vectors (unpredicated)-
000 0xx1xxxx 1010xx SVE address generation-
000 1xx1xxxx 001000 DUP (indexed)FEAT_SVE || FEAT_SME
000 1xx1xxxx 00101x SVE table lookup (three sources)-
000 1xx1xxxx 001100 TBL — SVEFEAT_SVE || FEAT_SME
000 1xx1xxxx 001101 TBXQFEAT_SVE2p1 || FEAT_SME2p1
000 1xx1xxxx 011xxx SVE permute vector elements-
000 1xx1xxxx 11xxxx SEL (vectors)FEAT_SVE || FEAT_SME
001 0xx1xxxx SVE integer compare with unsigned immediate-
001 1xx00xxx 01xxxx SVE predicate logical operations-
001 1xx0xxxx x0xxxx SVE integer compare with signed immediate-
001 1xx1xxxx 01xxxx 0 SVE broadcast predicate element-
010 0000xxxx 11001x SVE two-way dot product-
010 0100xxxx 11001x SVE two-way dot product (indexed)-
010 0xx0xxxx 11000x SVE integer clamp-
010 0xx0xxxx 1101xx SVE2 multiply-add (checked pointer)-
010 0xx0xxxx 111xxx SVE permute vector elements (quadwords)-
010 1xx1xxxx 100xxx SVE2 character match-
010 1xx1xxxx 110xxx HISTCNTFEAT_SVE2
011 00x1xxxx 111000 SVE2 FP8 matrix multiply-accumulate-
011 0x01xxxx 0101xx SVE2 FP8 multiply-add long (indexed)-
011 0xx00000 100xxx FCADDFEAT_SVE || FEAT_SME
011 0xx0000x 101xxx SVE floating-point convert (top, predicated)-
011 0xx0010x 101xxx SVE floating-point convert precision odd elements-
011 0xx010xx 100xxx SVE2 floating-point pairwise operations-
011 0xx010xx 101xxx SVE floating-point recursive reduction (quadwords)-
011 0xx0xxxx 0xxxxx FCMLA (vectors)FEAT_SVE || FEAT_SME
011 0xx1xxxx 0000xx SVE floating-point multiply-add (indexed)-
011 0xx1xxxx 0001xx SVE floating-point complex multiply-add (indexed)-
011 0xx1xxxx 001001 SVE FP clamp-
011 0xx1xxxx 0010x0 SVE floating-point multiply (indexed)-
011 0xx1xxxx 1100xx SVE2 FP8 multiply-add long long (indexed)-
011 0xx1xxxx 111001 SVE floating-point matrix multiply accumulate-
011 1xx000xx 001xxx SVE floating-point recursive reduction-
011 1xx0xxxx 000xxx SVE floating-point arithmetic (unpredicated)-
011 1xx0xxxx x1xxxx SVE floating-point compare vectors-

SVE Integer Binary Arithmetic - Predicated

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
000001000op0000
Decode fieldsInstruction details
op0
00x SVE integer add/subtract vectors (predicated)
01x SVE integer min/max/difference (predicated)
100 SVE integer multiply vectors (predicated)
101 SVE integer divide vectors (predicated)
11x SVE bitwise logical operations (predicated)

SVE integer add/subtract vectors (predicated)

The encodings in this section are decoded from SVE Integer Binary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size000opc000PgZmZdn
Decode fields Instruction Details Feature
size opc
000 ADD (vectors, predicated)FEAT_SVE || FEAT_SME
001 SUB (vectors, predicated)FEAT_SVE || FEAT_SME
010 UNALLOCATED-
011 SUBR (vectors)FEAT_SVE || FEAT_SME
11 100 ADDPT (predicated)FEAT_SVE && FEAT_CPA
11 101 SUBPT (predicated)FEAT_SVE && FEAT_CPA
11 11x UNALLOCATED-
!= 11 1xx UNALLOCATED-

SVE integer min/max/difference (predicated)

The encodings in this section are decoded from SVE Integer Binary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size001opcU000PgZmZdn
Decode fields Instruction Details Feature
opc U
00 0 SMAX (vectors)FEAT_SVE || FEAT_SME
00 1 UMAX (vectors)FEAT_SVE || FEAT_SME
01 0 SMIN (vectors)FEAT_SVE || FEAT_SME
01 1 UMIN (vectors)FEAT_SVE || FEAT_SME
10 0 SABDFEAT_SVE || FEAT_SME
10 1 UABDFEAT_SVE || FEAT_SME
11 UNALLOCATED-

SVE integer multiply vectors (predicated)

The encodings in this section are decoded from SVE Integer Binary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size0100HU000PgZmZdn
Decode fields Instruction Details Feature
H U
0 0 MUL (vectors, predicated)FEAT_SVE || FEAT_SME
0 1 UNALLOCATED-
1 0 SMULH (predicated)FEAT_SVE || FEAT_SME
1 1 UMULH (predicated)FEAT_SVE || FEAT_SME

SVE integer divide vectors (predicated)

The encodings in this section are decoded from SVE Integer Binary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size0101RU000PgZmZdn
Decode fields Instruction Details Feature
R U
0 0 SDIVFEAT_SVE || FEAT_SME
0 1 UDIVFEAT_SVE || FEAT_SME
1 0 SDIVRFEAT_SVE || FEAT_SME
1 1 UDIVRFEAT_SVE || FEAT_SME

SVE bitwise logical operations (predicated)

The encodings in this section are decoded from SVE Integer Binary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size011opc000PgZmZdn
Decode fields Instruction Details Feature
opc
000 ORR (vectors, predicated)FEAT_SVE || FEAT_SME
001 EOR (vectors, predicated)FEAT_SVE || FEAT_SME
010 AND (vectors, predicated)FEAT_SVE || FEAT_SME
011 BIC (vectors, predicated)FEAT_SVE || FEAT_SME
1xx UNALLOCATED-

SVE Integer Reduction

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
000001000op0001
Decode fieldsInstruction details
op0
000 SVE integer add reduction (predicated)
001 SVE integer add reduction (quadwords)
010 SVE integer min/max reduction (predicated)
011 SVE integer min/max reduction (quadwords)
10x SVE constructive prefix (predicated)
110 SVE bitwise logical reduction (predicated)
111 SVE bitwise logical reduction (quadwords)

SVE integer add reduction (predicated)

The encodings in this section are decoded from SVE Integer Reduction.

313029282726252423222120191817161514131211109876543210
000001000000opU001PgZnVd
Decode fields Instruction Details Feature
op U
0 0 SADDVFEAT_SVE || FEAT_SME
0 1 UADDVFEAT_SVE || FEAT_SME
1 UNALLOCATED-

SVE integer add reduction (quadwords)

The encodings in this section are decoded from SVE Integer Reduction.

313029282726252423222120191817161514131211109876543210
000001000001opU001PgZnVd
Decode fields Instruction Details Feature
op U
0 0 UNALLOCATED-
0 1 ADDQVFEAT_SVE2p1 || FEAT_SME2p1
1 UNALLOCATED-

SVE integer min/max reduction (predicated)

The encodings in this section are decoded from SVE Integer Reduction.

313029282726252423222120191817161514131211109876543210
000001000010opU001PgZnVd
Decode fields Instruction Details Feature
op U
0 0 SMAXVFEAT_SVE || FEAT_SME
0 1 UMAXVFEAT_SVE || FEAT_SME
1 0 SMINVFEAT_SVE || FEAT_SME
1 1 UMINVFEAT_SVE || FEAT_SME

SVE integer min/max reduction (quadwords)

The encodings in this section are decoded from SVE Integer Reduction.

313029282726252423222120191817161514131211109876543210
000001000011opU001PgZnVd
Decode fields Instruction Details Feature
op U
0 0 SMAXQVFEAT_SVE2p1 || FEAT_SME2p1
0 1 UMAXQVFEAT_SVE2p1 || FEAT_SME2p1
1 0 SMINQVFEAT_SVE2p1 || FEAT_SME2p1
1 1 UMINQVFEAT_SVE2p1 || FEAT_SME2p1

SVE constructive prefix (predicated)

The encodings in this section are decoded from SVE Integer Reduction.

313029282726252423222120191817161514131211109876543210
00000100010opcM001PgZnZd
Decode fields Instruction Details Feature
opc
00 MOVPRFX (predicated)FEAT_SVE || FEAT_SME
!= 00 UNALLOCATED-

SVE bitwise logical reduction (predicated)

The encodings in this section are decoded from SVE Integer Reduction.

313029282726252423222120191817161514131211109876543210
000001000110opc001PgZnVd
Decode fields Instruction Details Feature
opc
00 ORVFEAT_SVE || FEAT_SME
01 EORVFEAT_SVE || FEAT_SME
10 ANDVFEAT_SVE || FEAT_SME
11 UNALLOCATED-

SVE bitwise logical reduction (quadwords)

The encodings in this section are decoded from SVE Integer Reduction.

313029282726252423222120191817161514131211109876543210
000001000111opc001PgZnVd
Decode fields Instruction Details Feature
opc
00 ORQVFEAT_SVE2p1 || FEAT_SME2p1
01 EORQVFEAT_SVE2p1 || FEAT_SME2p1
10 ANDQVFEAT_SVE2p1 || FEAT_SME2p1
11 UNALLOCATED-

SVE Bitwise Shift - Predicated

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
000001000op0100
Decode fieldsInstruction details
op0
0x SVE bitwise shift by immediate (predicated)
10 SVE bitwise shift by vector (predicated)
11 SVE bitwise shift by wide elements (predicated)

SVE bitwise shift by immediate (predicated)

The encodings in this section are decoded from SVE Bitwise Shift - Predicated.

313029282726252423222120191817161514131211109876543210
00000100tszh00opcLU100Pgtszlimm3Zdn
Decode fields Instruction Details Feature
opc L U
00 0 0 ASR (immediate, predicated)FEAT_SVE || FEAT_SME
00 0 1 LSR (immediate, predicated)FEAT_SVE || FEAT_SME
00 1 0 UNALLOCATED-
00 1 1 LSL (immediate, predicated)FEAT_SVE || FEAT_SME
01 0 0 ASRDFEAT_SVE || FEAT_SME
01 0 1 UNALLOCATED-
01 1 0 SQSHL (immediate)FEAT_SVE2 || FEAT_SME
01 1 1 UQSHL (immediate)FEAT_SVE2 || FEAT_SME
10 UNALLOCATED-
11 0 0 SRSHRFEAT_SVE2 || FEAT_SME
11 0 1 URSHRFEAT_SVE2 || FEAT_SME
11 1 0 UNALLOCATED-
11 1 1 SQSHLUFEAT_SVE2 || FEAT_SME

SVE bitwise shift by vector (predicated)

The encodings in this section are decoded from SVE Bitwise Shift - Predicated.

313029282726252423222120191817161514131211109876543210
00000100010RLU100PgZmZdn
Decode fields Instruction Details Feature
R L U
1 0 UNALLOCATED-
0 0 0 ASR (vectors)FEAT_SVE || FEAT_SME
0 0 1 LSR (vectors)FEAT_SVE || FEAT_SME
0 1 1 LSL (vectors)FEAT_SVE || FEAT_SME
1 0 0 ASRRFEAT_SVE || FEAT_SME
1 0 1 LSRRFEAT_SVE || FEAT_SME
1 1 1 LSLRFEAT_SVE || FEAT_SME

SVE bitwise shift by wide elements (predicated)

The encodings in this section are decoded from SVE Bitwise Shift - Predicated.

313029282726252423222120191817161514131211109876543210
00000100011RLU100PgZmZdn
Decode fields Instruction Details Feature
R L U
0 0 0 ASR (wide elements, predicated)FEAT_SVE || FEAT_SME
0 0 1 LSR (wide elements, predicated)FEAT_SVE || FEAT_SME
0 1 0 UNALLOCATED-
0 1 1 LSL (wide elements, predicated)FEAT_SVE || FEAT_SME
1 UNALLOCATED-

SVE Integer Unary Arithmetic - Predicated

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
000001000op0101
Decode fieldsInstruction details
op0
x0 SVE integer unary operations (predicated)
x1 SVE bitwise unary operations (predicated)

SVE integer unary operations (predicated)

The encodings in this section are decoded from SVE Integer Unary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size0M0opc101PgZnZd
Decode fields Instruction Details Feature
M opc
0 000 SXTB, SXTH, SXTW — Byte, zeroingFEAT_SVE2p2 || FEAT_SME2p2
0 001 UXTB, UXTH, UXTW — Byte, zeroingFEAT_SVE2p2 || FEAT_SME2p2
0 010 SXTB, SXTH, SXTW — Halfword, zeroingFEAT_SVE2p2 || FEAT_SME2p2
0 011 UXTB, UXTH, UXTW — Halfword, zeroingFEAT_SVE2p2 || FEAT_SME2p2
0 100 SXTB, SXTH, SXTW — Word, zeroingFEAT_SVE2p2 || FEAT_SME2p2
0 101 UXTB, UXTH, UXTW — Word, zeroingFEAT_SVE2p2 || FEAT_SME2p2
0 110 ABS — ZeroingFEAT_SVE2p2 || FEAT_SME2p2
0 111 NEG — ZeroingFEAT_SVE2p2 || FEAT_SME2p2
1 000 SXTB, SXTH, SXTW — Byte, mergingFEAT_SVE || FEAT_SME
1 001 UXTB, UXTH, UXTW — Byte, mergingFEAT_SVE || FEAT_SME
1 010 SXTB, SXTH, SXTW — Halfword, mergingFEAT_SVE || FEAT_SME
1 011 UXTB, UXTH, UXTW — Halfword, mergingFEAT_SVE || FEAT_SME
1 100 SXTB, SXTH, SXTW — Word, mergingFEAT_SVE || FEAT_SME
1 101 UXTB, UXTH, UXTW — Word, mergingFEAT_SVE || FEAT_SME
1 110 ABS — MergingFEAT_SVE || FEAT_SME
1 111 NEG — MergingFEAT_SVE || FEAT_SME

SVE bitwise unary operations (predicated)

The encodings in this section are decoded from SVE Integer Unary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size0M1opc101PgZnZd
Decode fields Instruction Details Feature
M opc
111 UNALLOCATED-
0 000 CLS — ZeroingFEAT_SVE2p2 || FEAT_SME2p2
0 001 CLZ — ZeroingFEAT_SVE2p2 || FEAT_SME2p2
0 010 CNT — ZeroingFEAT_SVE2p2 || FEAT_SME2p2
0 011 CNOT — ZeroingFEAT_SVE2p2 || FEAT_SME2p2
0 100 FABS — ZeroingFEAT_SVE2p2 || FEAT_SME2p2
0 101 FNEG — ZeroingFEAT_SVE2p2 || FEAT_SME2p2
0 110 NOT (vector) — ZeroingFEAT_SVE2p2 || FEAT_SME2p2
1 000 CLS — MergingFEAT_SVE || FEAT_SME
1 001 CLZ — MergingFEAT_SVE || FEAT_SME
1 010 CNT — MergingFEAT_SVE || FEAT_SME
1 011 CNOT — MergingFEAT_SVE || FEAT_SME
1 100 FABS — MergingFEAT_SVE || FEAT_SME
1 101 FNEG — MergingFEAT_SVE || FEAT_SME
1 110 NOT (vector) — MergingFEAT_SVE || FEAT_SME

SVE Integer Multiply-Add - Predicated

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
000001000op01
Decode fieldsInstruction details
op0
0 SVE integer multiply-accumulate writing addend (predicated)
1 SVE integer multiply-add writing multiplicand (predicated)

SVE integer multiply-accumulate writing addend (predicated)

The encodings in this section are decoded from SVE Integer Multiply-Add - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size0Zm01opPgZnZda
Decode fields Instruction Details Feature
op
0 MLA (vectors)FEAT_SVE || FEAT_SME
1 MLS (vectors)FEAT_SVE || FEAT_SME

SVE integer multiply-add writing multiplicand (predicated)

The encodings in this section are decoded from SVE Integer Multiply-Add - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size0Zm11opPgZaZdn
Decode fields Instruction Details Feature
op
0 MADFEAT_SVE || FEAT_SME
1 MSBFEAT_SVE || FEAT_SME

SVE Bitwise Logical - Unpredicated

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
000001001001op0
Decode fieldsInstruction detailsFeature
op0
0xx UNALLOCATED-
100 SVE bitwise logical operations (unpredicated)-
101 XARFEAT_SVE2 || FEAT_SME
11x SVE2 bitwise ternary operations-

SVE bitwise logical operations (unpredicated)

The encodings in this section are decoded from SVE Bitwise Logical - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100opc1Zm001100ZnZd
Decode fields Instruction Details Feature
opc
00 AND (vectors, unpredicated)FEAT_SVE || FEAT_SME
01 ORR (vectors, unpredicated)FEAT_SVE || FEAT_SME
10 EOR (vectors, unpredicated)FEAT_SVE || FEAT_SME
11 BIC (vectors, unpredicated)FEAT_SVE || FEAT_SME

SVE2 bitwise ternary operations

The encodings in this section are decoded from SVE Bitwise Logical - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100opc1Zm00111o2ZkZdn
Decode fields Instruction Details Feature
opc o2
00 0 EOR3FEAT_SVE2 || FEAT_SME
00 1 BSLFEAT_SVE2 || FEAT_SME
01 0 BCAXFEAT_SVE2 || FEAT_SME
01 1 BSL1NFEAT_SVE2 || FEAT_SME
1x 0 UNALLOCATED-
10 1 BSL2NFEAT_SVE2 || FEAT_SME
11 1 NBSLFEAT_SVE2 || FEAT_SME

SVE Index Generation

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
0000010010100op0
Decode fieldsInstruction detailsFeature
op0
00 INDEX (immediates)FEAT_SVE || FEAT_SME
01 INDEX (scalar, immediate)FEAT_SVE || FEAT_SME
10 INDEX (immediate, scalar)FEAT_SVE || FEAT_SME
11 INDEX (scalars)FEAT_SVE || FEAT_SME

SVE Stack Allocation

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
00000100op010101op1
Decode fieldsInstruction details
op0op1
0 0 SVE stack frame adjustment
0 1 Streaming SVE stack frame adjustment
1 0 SVE stack frame size
1 1 Streaming SVE stack frame size

SVE stack frame adjustment

The encodings in this section are decoded from SVE Stack Allocation.

313029282726252423222120191817161514131211109876543210
000001000op1Rn01010imm6Rd
Decode fields Instruction Details Feature
op
0 ADDVLFEAT_SVE || FEAT_SME
1 ADDPLFEAT_SVE || FEAT_SME

Streaming SVE stack frame adjustment

The encodings in this section are decoded from SVE Stack Allocation.

313029282726252423222120191817161514131211109876543210
000001000op1Rn01011imm6Rd
Decode fields Instruction Details Feature
op
0 ADDSVLFEAT_SME
1 ADDSPLFEAT_SME

SVE stack frame size

The encodings in this section are decoded from SVE Stack Allocation.

313029282726252423222120191817161514131211109876543210
000001001op1opc201010imm6Rd
Decode fields Instruction Details Feature
op opc2
0 11111 RDVLFEAT_SVE || FEAT_SME
0 != 11111 UNALLOCATED-
1 UNALLOCATED-

Streaming SVE stack frame size

The encodings in this section are decoded from SVE Stack Allocation.

313029282726252423222120191817161514131211109876543210
000001001op1opc201011imm6Rd
Decode fields Instruction Details Feature
op opc2
0 11111 RDSVLFEAT_SME
0 != 11111 UNALLOCATED-
1 UNALLOCATED-

SVE2 Integer Multiply - Unpredicated

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
000001001011op0
Decode fieldsInstruction details
op0
0x SVE2 integer multiply vectors (unpredicated)
10 SVE2 signed saturating doubling multiply high (unpredicated)
11 UNALLOCATED

SVE2 integer multiply vectors (unpredicated)

The encodings in this section are decoded from SVE2 Integer Multiply - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100size1Zm0110opcZnZd
Decode fields Instruction Details Feature
size opc
00 MUL (vectors, unpredicated)FEAT_SVE2 || FEAT_SME
10 SMULH (unpredicated)FEAT_SVE2 || FEAT_SME
11 UMULH (unpredicated)FEAT_SVE2 || FEAT_SME
00 01 PMULFEAT_SVE2 || FEAT_SME
!= 00 01 UNALLOCATED-

SVE2 signed saturating doubling multiply high (unpredicated)

The encodings in this section are decoded from SVE2 Integer Multiply - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100size1Zm01110RZnZd
Decode fields Instruction Details Feature
R
0 SQDMULH (vectors)FEAT_SVE2 || FEAT_SME
1 SQRDMULH (vectors)FEAT_SVE2 || FEAT_SME

SVE Bitwise Shift - Unpredicated

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
000001001100op0
Decode fieldsInstruction details
op0
0 SVE bitwise shift by wide elements (unpredicated)
1 SVE bitwise shift by immediate (unpredicated)

SVE bitwise shift by wide elements (unpredicated)

The encodings in this section are decoded from SVE Bitwise Shift - Unpredicated.

313029282726252423222120191817161514131211109876543210
000001001Zm1000opcZnZd
Decode fields Instruction Details Feature
opc
00 ASR (wide elements, unpredicated)FEAT_SVE || FEAT_SME
01 LSR (wide elements, unpredicated)FEAT_SVE || FEAT_SME
10 UNALLOCATED-
11 LSL (wide elements, unpredicated)FEAT_SVE || FEAT_SME

SVE bitwise shift by immediate (unpredicated)

The encodings in this section are decoded from SVE Bitwise Shift - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100tszh1tszlimm31001opcZnZd
Decode fields Instruction Details Feature
opc
00 ASR (immediate, unpredicated)FEAT_SVE || FEAT_SME
01 LSR (immediate, unpredicated)FEAT_SVE || FEAT_SME
10 UNALLOCATED-
11 LSL (immediate, unpredicated)FEAT_SVE || FEAT_SME

SVE Integer Misc - Unpredicated

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
0000010011011op0
Decode fieldsInstruction details
op0
0x SVE floating-point trig select coefficient
10 SVE floating-point exponential accelerator
11 SVE constructive prefix (unpredicated)

SVE floating-point trig select coefficient

The encodings in this section are decoded from SVE Integer Misc - Unpredicated.

313029282726252423222120191817161514131211109876543210
000001001Zm10110opZnZd
Decode fields Instruction Details Feature
op
0 FTSSELFEAT_SVE
1 UNALLOCATED-

SVE floating-point exponential accelerator

The encodings in this section are decoded from SVE Integer Misc - Unpredicated.

313029282726252423222120191817161514131211109876543210
000001001opc101110ZnZd
Decode fields Instruction Details Feature
opc
00000 FEXPAFEAT_SVE || FEAT_SME2p2
!= 00000 UNALLOCATED-

SVE constructive prefix (unpredicated)

The encodings in this section are decoded from SVE Integer Misc - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100opc1opc2101111ZnZd
Decode fields Instruction Details Feature
opc opc2
00 00000 MOVPRFX (unpredicated)FEAT_SVE || FEAT_SME
00 != 00000 UNALLOCATED-
!= 00 UNALLOCATED-

SVE Element Count

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
000001001op011op1
Decode fieldsInstruction details
op0op1
0 00x SVE saturating inc/dec vector by element count
0 100 SVE element count
0 101 UNALLOCATED
1 000 SVE inc/dec vector by element count
1 100 SVE inc/dec register by element count
1 x01 UNALLOCATED
01x UNALLOCATED
11x SVE saturating inc/dec register by element count

SVE saturating inc/dec vector by element count

The encodings in this section are decoded from SVE Element Count.

313029282726252423222120191817161514131211109876543210
00000100size10imm41100DUpatternZdn
Decode fields Instruction Details Feature
size D U
00 UNALLOCATED-
01 0 0 SQINCH (vector)FEAT_SVE || FEAT_SME
01 0 1 UQINCH (vector)FEAT_SVE || FEAT_SME
01 1 0 SQDECH (vector)FEAT_SVE || FEAT_SME
01 1 1 UQDECH (vector)FEAT_SVE || FEAT_SME
10 0 0 SQINCW (vector)FEAT_SVE || FEAT_SME
10 0 1 UQINCW (vector)FEAT_SVE || FEAT_SME
10 1 0 SQDECW (vector)FEAT_SVE || FEAT_SME
10 1 1 UQDECW (vector)FEAT_SVE || FEAT_SME
11 0 0 SQINCD (vector)FEAT_SVE || FEAT_SME
11 0 1 UQINCD (vector)FEAT_SVE || FEAT_SME
11 1 0 SQDECD (vector)FEAT_SVE || FEAT_SME
11 1 1 UQDECD (vector)FEAT_SVE || FEAT_SME

SVE element count

The encodings in this section are decoded from SVE Element Count.

313029282726252423222120191817161514131211109876543210
00000100size10imm411100oppatternRd
Decode fields Instruction Details Feature
size op
1 UNALLOCATED-
00 0 CNTB, CNTD, CNTH, CNTW — ByteFEAT_SVE || FEAT_SME
01 0 CNTB, CNTD, CNTH, CNTW — HalfwordFEAT_SVE || FEAT_SME
10 0 CNTB, CNTD, CNTH, CNTW — WordFEAT_SVE || FEAT_SME
11 0 CNTB, CNTD, CNTH, CNTW — DoublewordFEAT_SVE || FEAT_SME

SVE inc/dec vector by element count

The encodings in this section are decoded from SVE Element Count.

313029282726252423222120191817161514131211109876543210
00000100size11imm411000DpatternZdn
Decode fields Instruction Details Feature
size D
00 UNALLOCATED-
01 0 INCD, INCH, INCW (vector) — HalfwordFEAT_SVE || FEAT_SME
01 1 DECD, DECH, DECW (vector) — HalfwordFEAT_SVE || FEAT_SME
10 0 INCD, INCH, INCW (vector) — WordFEAT_SVE || FEAT_SME
10 1 DECD, DECH, DECW (vector) — WordFEAT_SVE || FEAT_SME
11 0 INCD, INCH, INCW (vector) — DoublewordFEAT_SVE || FEAT_SME
11 1 DECD, DECH, DECW (vector) — DoublewordFEAT_SVE || FEAT_SME

SVE inc/dec register by element count

The encodings in this section are decoded from SVE Element Count.

313029282726252423222120191817161514131211109876543210
00000100size11imm411100DpatternRdn
Decode fields Instruction Details Feature
size D
00 0 INCB, INCD, INCH, INCW (scalar) — ByteFEAT_SVE || FEAT_SME
00 1 DECB, DECD, DECH, DECW (scalar) — ByteFEAT_SVE || FEAT_SME
01 0 INCB, INCD, INCH, INCW (scalar) — HalfwordFEAT_SVE || FEAT_SME
01 1 DECB, DECD, DECH, DECW (scalar) — HalfwordFEAT_SVE || FEAT_SME
10 0 INCB, INCD, INCH, INCW (scalar) — WordFEAT_SVE || FEAT_SME
10 1 DECB, DECD, DECH, DECW (scalar) — WordFEAT_SVE || FEAT_SME
11 0 INCB, INCD, INCH, INCW (scalar) — DoublewordFEAT_SVE || FEAT_SME
11 1 DECB, DECD, DECH, DECW (scalar) — DoublewordFEAT_SVE || FEAT_SME

SVE saturating inc/dec register by element count

The encodings in this section are decoded from SVE Element Count.

313029282726252423222120191817161514131211109876543210
00000100size1sfimm41111DUpatternRdn
Decode fields Instruction Details Feature
size sf D U
00 0 0 0 SQINCB — 32-bitFEAT_SVE || FEAT_SME
00 0 0 1 UQINCB — 32-bitFEAT_SVE || FEAT_SME
00 0 1 0 SQDECB — 32-bitFEAT_SVE || FEAT_SME
00 0 1 1 UQDECB — 32-bitFEAT_SVE || FEAT_SME
00 1 0 0 SQINCB — 64-bitFEAT_SVE || FEAT_SME
00 1 0 1 UQINCB — 64-bitFEAT_SVE || FEAT_SME
00 1 1 0 SQDECB — 64-bitFEAT_SVE || FEAT_SME
00 1 1 1 UQDECB — 64-bitFEAT_SVE || FEAT_SME
01 0 0 0 SQINCH (scalar) — 32-bitFEAT_SVE || FEAT_SME
01 0 0 1 UQINCH (scalar) — 32-bitFEAT_SVE || FEAT_SME
01 0 1 0 SQDECH (scalar) — 32-bitFEAT_SVE || FEAT_SME
01 0 1 1 UQDECH (scalar) — 32-bitFEAT_SVE || FEAT_SME
01 1 0 0 SQINCH (scalar) — 64-bitFEAT_SVE || FEAT_SME
01 1 0 1 UQINCH (scalar) — 64-bitFEAT_SVE || FEAT_SME
01 1 1 0 SQDECH (scalar) — 64-bitFEAT_SVE || FEAT_SME
01 1 1 1 UQDECH (scalar) — 64-bitFEAT_SVE || FEAT_SME
10 0 0 0 SQINCW (scalar) — 32-bitFEAT_SVE || FEAT_SME
10 0 0 1 UQINCW (scalar) — 32-bitFEAT_SVE || FEAT_SME
10 0 1 0 SQDECW (scalar) — 32-bitFEAT_SVE || FEAT_SME
10 0 1 1 UQDECW (scalar) — 32-bitFEAT_SVE || FEAT_SME
10 1 0 0 SQINCW (scalar) — 64-bitFEAT_SVE || FEAT_SME
10 1 0 1 UQINCW (scalar) — 64-bitFEAT_SVE || FEAT_SME
10 1 1 0 SQDECW (scalar) — 64-bitFEAT_SVE || FEAT_SME
10 1 1 1 UQDECW (scalar) — 64-bitFEAT_SVE || FEAT_SME
11 0 0 0 SQINCD (scalar) — 32-bitFEAT_SVE || FEAT_SME
11 0 0 1 UQINCD (scalar) — 32-bitFEAT_SVE || FEAT_SME
11 0 1 0 SQDECD (scalar) — 32-bitFEAT_SVE || FEAT_SME
11 0 1 1 UQDECD (scalar) — 32-bitFEAT_SVE || FEAT_SME
11 1 0 0 SQINCD (scalar) — 64-bitFEAT_SVE || FEAT_SME
11 1 0 1 UQINCD (scalar) — 64-bitFEAT_SVE || FEAT_SME
11 1 1 0 SQDECD (scalar) — 64-bitFEAT_SVE || FEAT_SME
11 1 1 1 UQDECD (scalar) — 64-bitFEAT_SVE || FEAT_SME

SVE Permute Vector - Extract

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
000001010op01000
Decode fieldsInstruction detailsFeature
op0
0 EXT — DestructiveFEAT_SVE || FEAT_SME
1 EXT — ConstructiveFEAT_SVE2 || FEAT_SME

SVE Permute Vector - Segments

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
000001011op01000
Decode fieldsInstruction details
op0
0 SVE permute vector segments
1 UNALLOCATED

SVE permute vector segments

The encodings in this section are decoded from SVE Permute Vector - Segments.

313029282726252423222120191817161514131211109876543210
00000101101Zm000opcHZnZd
Decode fields Instruction Details Feature
opc H
00 0 ZIP1, ZIP2 (vectors) — Low halves (quadwords)FEAT_F64MM
00 1 ZIP1, ZIP2 (vectors) — High halves (quadwords)FEAT_F64MM
01 0 UZP1, UZP2 (vectors) — Even (quadwords)FEAT_F64MM
01 1 UZP1, UZP2 (vectors) — Odd (quadwords)FEAT_F64MM
10 UNALLOCATED-
11 0 TRN1, TRN2 (vectors) — Even (quadwords)FEAT_F64MM
11 1 TRN1, TRN2 (vectors) — Odd (quadwords)FEAT_F64MM

SVE Bitwise Immediate

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
00000101op000op1
Decode fieldsInstruction detailsFeature
op0op1
11 00 DUPMFEAT_SVE || FEAT_SME
!= 00 UNALLOCATED-
!= 11 00 SVE bitwise logical with immediate (unpredicated)-

SVE bitwise logical with immediate (unpredicated)

The encodings in this section are decoded from SVE Bitwise Immediate.

313029282726252423222120191817161514131211109876543210
00000101!= 110000imm13Zdn
opc

The following constraints also apply to this encoding: opc != '11'

Decode fields Instruction Details Feature
opc
00 ORR (immediate)FEAT_SVE || FEAT_SME
01 EOR (immediate)FEAT_SVE || FEAT_SME
10 AND (immediate)FEAT_SVE || FEAT_SME

SVE Integer Wide Immediate - Predicated

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
0000010101op0
Decode fieldsInstruction detailsFeature
op0
0xx SVE copy integer immediate (predicated)-
10x UNALLOCATED-
110 FCPYFEAT_SVE || FEAT_SME
111 UNALLOCATED-

SVE copy integer immediate (predicated)

The encodings in this section are decoded from SVE Integer Wide Immediate - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size01Pg0Mshimm8Zd
Decode fields Instruction Details Feature
M
0 CPY (immediate, zeroing)FEAT_SVE || FEAT_SME
1 CPY (immediate, merging)FEAT_SVE || FEAT_SME

SVE Permute Vector - One Source Quadwords

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
00000101op01op1001001
Decode fieldsInstruction detailsFeature
op0op1
00 DUPQFEAT_SVE2p1 || FEAT_SME2p1
01 0 EXTQFEAT_SVE2p1 || FEAT_SME2p1
01 1 UNALLOCATED-
1x UNALLOCATED-

SVE Permute Vector - Unpredicated

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
000001011op0op1001110op2op3
Decode fieldsInstruction detailsFeature
op0op1op2op3
00 000 DUP (scalar)FEAT_SVE || FEAT_SME
00 100 INSR (scalar)FEAT_SVE || FEAT_SME
00 x01 UNALLOCATED-
00 x1x UNALLOCATED-
01 xx0 0 SVE move predicate from vector-
01 xx0 1 UNALLOCATED-
01 xx1 0 SVE move predicate into vector-
01 xx1 1 UNALLOCATED-
10 0xx SVE unpack vector elements-
10 100 INSR (SIMD&FP scalar)FEAT_SVE || FEAT_SME
10 101 UNALLOCATED-
10 11x UNALLOCATED-
11 000 REV (vector)FEAT_SVE || FEAT_SME
11 != 000 UNALLOCATED-

SVE move predicate from vector

The encodings in this section are decoded from SVE Permute Vector - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000101opc101opc20001110Zn0Pd
Decode fields Instruction Details Feature
opc opc2
00 00 UNALLOCATED-
00 01 PMOV (to predicate) — ByteFEAT_SVE2p1 || FEAT_SME2p1
00 1x PMOV (to predicate) — HalfwordFEAT_SVE2p1 || FEAT_SME2p1
01 PMOV (to predicate) — WordFEAT_SVE2p1 || FEAT_SME2p1
1x PMOV (to predicate) — DoublewordFEAT_SVE2p1 || FEAT_SME2p1

SVE move predicate into vector

The encodings in this section are decoded from SVE Permute Vector - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000101opc101opc210011100PnZd
Decode fields Instruction Details Feature
opc opc2
00 00 UNALLOCATED-
00 01 PMOV (to vector) — ByteFEAT_SVE2p1 || FEAT_SME2p1
00 1x PMOV (to vector) — HalfwordFEAT_SVE2p1 || FEAT_SME2p1
01 PMOV (to vector) — WordFEAT_SVE2p1 || FEAT_SME2p1
1x PMOV (to vector) — DoublewordFEAT_SVE2p1 || FEAT_SME2p1

SVE unpack vector elements

The encodings in this section are decoded from SVE Permute Vector - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000101size1100UH001110ZnZd
Decode fields Instruction Details Feature
U H
0 0 SUNPKHI, SUNPKLO — Low halfFEAT_SVE || FEAT_SME
0 1 SUNPKHI, SUNPKLO — High halfFEAT_SVE || FEAT_SME
1 0 UUNPKHI, UUNPKLO — Low halfFEAT_SVE || FEAT_SME
1 1 UUNPKHI, UUNPKLO — High halfFEAT_SVE || FEAT_SME

SVE Permute Predicate

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
00000101op01op1010op2op3
Decode fieldsInstruction detailsFeature
op0op1op2op3
00 1000x 0000 0 SVE unpack predicate elements-
0xxxx xxx0 0 SVE permute predicate elements-
10100 0000 0 REV (predicate)FEAT_SVE || FEAT_SME
10101 0000 0 UNALLOCATED-
10x0x 0010 0 UNALLOCATED-
10x0x 01x0 0 UNALLOCATED-
10x0x 1xx0 0 UNALLOCATED-
10x1x xxx0 0 UNALLOCATED-
11xxx xxx0 0 UNALLOCATED-
xxx0 1 UNALLOCATED-
xxx1 UNALLOCATED-
!= 00 1000x 0000 0 UNALLOCATED-

SVE unpack predicate elements

The encodings in this section are decoded from SVE Permute Predicate.

313029282726252423222120191817161514131211109876543210
000001010011000H0100000Pn0Pd
Decode fields Instruction Details Feature
H
0 PUNPKHI, PUNPKLO — Low halfFEAT_SVE || FEAT_SME
1 PUNPKHI, PUNPKLO — High halfFEAT_SVE || FEAT_SME

SVE permute predicate elements

The encodings in this section are decoded from SVE Permute Predicate.

313029282726252423222120191817161514131211109876543210
00000101size10Pm010opcH0Pn0Pd
Decode fields Instruction Details Feature
opc H
00 0 ZIP1, ZIP2 (predicates) — Low halvesFEAT_SVE || FEAT_SME
00 1 ZIP1, ZIP2 (predicates) — High halvesFEAT_SVE || FEAT_SME
01 0 UZP1, UZP2 (predicates) — EvenFEAT_SVE || FEAT_SME
01 1 UZP1, UZP2 (predicates) — OddFEAT_SVE || FEAT_SME
10 0 TRN1, TRN2 (predicates) — EvenFEAT_SVE || FEAT_SME
10 1 TRN1, TRN2 (predicates) — OddFEAT_SVE || FEAT_SME
11 UNALLOCATED-

SVE Permute Vector - Predicated

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
000001011op0op1op210op3
Decode fieldsInstruction detailsFeature
op0op1op2op3
0 000 0 0 CPY (SIMD&FP scalar)FEAT_SVE || FEAT_SME
0 000 1 0 SVE compress active elements-
0 000 1 SVE extract element to general register-
0 001 1 1 UNALLOCATED-
0 001 0 SVE extract element to SIMD&FP scalar register-
0 01x SVE reverse within elements-
0 100 0 1 CPY (scalar)FEAT_SVE || FEAT_SME
0 100 0 SVE conditionally broadcast element to vector-
0 101 0 SVE conditionally extract element to SIMD&FP scalar-
0 110 0 0 SPLICE — DestructiveFEAT_SVE || FEAT_SME
0 110 0 1 UNALLOCATED-
0 110 1 0 SPLICE — ConstructiveFEAT_SVE2 || FEAT_SME
0 111 0 SVE reverse doublewords-
0 111 1 0 UNALLOCATED-
0 1xx 1 1 UNALLOCATED-
0 x01 0 1 UNALLOCATED-
1 000 0 0 UNALLOCATED-
1 000 1 0 EXPANDFEAT_SVE2p2 || FEAT_SME2p2
1 000 1 SVE conditionally extract element to general register-
1 != 000 UNALLOCATED-

SVE compress active elements

The encodings in this section are decoded from SVE Permute Vector - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size100001100PgZnZd
Decode fields Instruction Details Feature
size
0x COMPACT — Byte and halfwordFEAT_SVE2p2 || FEAT_SME2p2
1x COMPACT — Word and doublewordFEAT_SVE || FEAT_SME2p2

SVE extract element to general register

The encodings in this section are decoded from SVE Permute Vector - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size10000B101PgZnRd
Decode fields Instruction Details Feature
B
0 LASTA (scalar)FEAT_SVE || FEAT_SME
1 LASTB (scalar)FEAT_SVE || FEAT_SME

SVE extract element to SIMD&FP scalar register

The encodings in this section are decoded from SVE Permute Vector - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size10001B100PgZnVd
Decode fields Instruction Details Feature
B
0 LASTA (SIMD&FP scalar)FEAT_SVE || FEAT_SME
1 LASTB (SIMD&FP scalar)FEAT_SVE || FEAT_SME

SVE reverse within elements

The encodings in this section are decoded from SVE Permute Vector - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size1001opc10ZPgZnZd
Decode fields Instruction Details Feature
opc Z
00 0 REVB, REVH, REVW — Byte, mergingFEAT_SVE || FEAT_SME
00 1 REVB, REVH, REVW — Byte, zeroingFEAT_SVE2p2 || FEAT_SME2p2
01 0 REVB, REVH, REVW — Halfword, mergingFEAT_SVE || FEAT_SME
01 1 REVB, REVH, REVW — Halfword, zeroingFEAT_SVE2p2 || FEAT_SME2p2
10 0 REVB, REVH, REVW — Word, mergingFEAT_SVE || FEAT_SME
10 1 REVB, REVH, REVW — Word, zeroingFEAT_SVE2p2 || FEAT_SME2p2
11 0 RBIT — MergingFEAT_SVE || FEAT_SME
11 1 RBIT — ZeroingFEAT_SVE2p2 || FEAT_SME2p2

SVE conditionally broadcast element to vector

The encodings in this section are decoded from SVE Permute Vector - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size10100B100PgZmZdn
Decode fields Instruction Details Feature
B
0 CLASTA (vectors)FEAT_SVE || FEAT_SME
1 CLASTB (vectors)FEAT_SVE || FEAT_SME

SVE conditionally extract element to SIMD&FP scalar

The encodings in this section are decoded from SVE Permute Vector - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size10101B100PgZmVdn
Decode fields Instruction Details Feature
B
0 CLASTA (SIMD&FP scalar)FEAT_SVE || FEAT_SME
1 CLASTB (SIMD&FP scalar)FEAT_SVE || FEAT_SME

SVE reverse doublewords

The encodings in this section are decoded from SVE Permute Vector - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size10111010ZPgZnZd
Decode fields Instruction Details Feature
size Z
00 0 REVD — MergingFEAT_SME || FEAT_SVE2p1
00 1 REVD — ZeroingFEAT_SVE2p2 || FEAT_SME2p2
!= 00 UNALLOCATED-

SVE conditionally extract element to general register

The encodings in this section are decoded from SVE Permute Vector - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size11000B101PgZmRdn
Decode fields Instruction Details Feature
B
0 CLASTA (scalar)FEAT_SVE || FEAT_SME
1 CLASTB (scalar)FEAT_SVE || FEAT_SME

SVE Integer Compare - Vectors

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
001001000op0
Decode fieldsInstruction details
op0
0 SVE integer compare vectors
1 SVE integer compare with wide elements

SVE integer compare vectors

The encodings in this section are decoded from SVE Integer Compare - Vectors.

313029282726252423222120191817161514131211109876543210
00100100size0Zmop0o2PgZnnePd
Decode fields Instruction Details Feature
op o2 ne
0 0 0 CMP<cc> (vectors) — Higher or sameFEAT_SVE || FEAT_SME
0 0 1 CMP<cc> (vectors) — HigherFEAT_SVE || FEAT_SME
0 1 0 CMP<cc> (wide elements) — EqualFEAT_SVE || FEAT_SME
0 1 1 CMP<cc> (wide elements) — Not equalFEAT_SVE || FEAT_SME
1 0 0 CMP<cc> (vectors) — Greater than or equalFEAT_SVE || FEAT_SME
1 0 1 CMP<cc> (vectors) — Greater thanFEAT_SVE || FEAT_SME
1 1 0 CMP<cc> (vectors) — EqualFEAT_SVE || FEAT_SME
1 1 1 CMP<cc> (vectors) — Not equalFEAT_SVE || FEAT_SME

SVE integer compare with wide elements

The encodings in this section are decoded from SVE Integer Compare - Vectors.

313029282726252423222120191817161514131211109876543210
00100100size0ZmU1ltPgZnnePd
Decode fields Instruction Details Feature
U lt ne
0 0 0 CMP<cc> (wide elements) — Greater than or equalFEAT_SVE || FEAT_SME
0 0 1 CMP<cc> (wide elements) — Greater thanFEAT_SVE || FEAT_SME
0 1 0 CMP<cc> (wide elements) — Less thanFEAT_SVE || FEAT_SME
0 1 1 CMP<cc> (wide elements) — Less than or equalFEAT_SVE || FEAT_SME
1 0 0 CMP<cc> (wide elements) — Higher or sameFEAT_SVE || FEAT_SME
1 0 1 CMP<cc> (wide elements) — HigherFEAT_SVE || FEAT_SME
1 1 0 CMP<cc> (wide elements) — LowerFEAT_SVE || FEAT_SME
1 1 1 CMP<cc> (wide elements) — Lower or sameFEAT_SVE || FEAT_SME

SVE Propagate Break

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
001001010011op0
Decode fieldsInstruction details
op0
0 SVE propagate break from previous partition
1 UNALLOCATED

SVE propagate break from previous partition

The encodings in this section are decoded from SVE Propagate Break.

313029282726252423222120191817161514131211109876543210
00100101opS00Pm11Pg0PnBPd
Decode fields Instruction Details Feature
op S B
0 0 0 BRKPAFEAT_SVE || FEAT_SME
0 0 1 BRKPBFEAT_SVE || FEAT_SME
0 1 0 BRKPASFEAT_SVE || FEAT_SME
0 1 1 BRKPBSFEAT_SVE || FEAT_SME
1 UNALLOCATED-

SVE Partition Break

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
00100101op001op101op2op3
Decode fieldsInstruction details
op0op1op2op3
0 1000 0 0 SVE propagate break to next partition
0 1000 0 1 UNALLOCATED
1 1000 0 UNALLOCATED
0000 0 SVE partition break condition
x000 1 UNALLOCATED
x001 UNALLOCATED
x01x UNALLOCATED
x1xx UNALLOCATED

SVE propagate break to next partition

The encodings in this section are decoded from SVE Partition Break.

313029282726252423222120191817161514131211109876543210
001001010S01100001Pg0Pn0Pdm
Decode fields Instruction Details Feature
S
0 BRKNFEAT_SVE || FEAT_SME
1 BRKNSFEAT_SVE || FEAT_SME

SVE partition break condition

The encodings in this section are decoded from SVE Partition Break.

313029282726252423222120191817161514131211109876543210
00100101BS01000001Pg0PnMPd
Decode fields Instruction Details Feature
B S M
1 1 UNALLOCATED-
0 0 BRKAFEAT_SVE || FEAT_SME
0 1 0 BRKASFEAT_SVE || FEAT_SME
1 0 BRKBFEAT_SVE || FEAT_SME
1 1 0 BRKBSFEAT_SVE || FEAT_SME

SVE Predicate Misc

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
0010010101op011op1op2op3op4
Decode fieldsInstruction detailsFeature
op0op1op2op3op4
0000 x0 0 SVE predicate test-
0000 x1 0 UNALLOCATED-
0001 0 UNALLOCATED-
1000 000 00 0 SVE predicate first active-
1000 000 10 0 UNALLOCATED-
1000 100 10 0000 0 SVE predicate zero-
1000 100 10 != 0000 0 UNALLOCATED-
1000 110 00 0 SVE predicate read from FFR (predicated)-
1001 000 00 0 UNALLOCATED-
1001 000 10 0 PNEXTFEAT_SVE || FEAT_SME
1001 100 10 0 UNALLOCATED-
1001 110 00 0000 0 SVE predicate read from FFR (unpredicated)-
1001 110 00 != 0000 0 UNALLOCATED-
100x 010 x0 0 UNALLOCATED-
100x 0x0 x1 0 UNALLOCATED-
100x 100 0x 0 SVE predicate initialize-
100x 100 11 0 UNALLOCATED-
100x 110 != 00 0 UNALLOCATED-
100x xx1 0 UNALLOCATED-
x00x 1 UNALLOCATED-
x01x UNALLOCATED-
x1xx UNALLOCATED-

SVE predicate test

The encodings in this section are decoded from SVE Predicate Misc.

313029282726252423222120191817161514131211109876543210
00100101opS01000011Pg0Pn0opc2
Decode fields Instruction Details Feature
op S opc2
0 0 UNALLOCATED-
0 1 0000 PTESTFEAT_SVE || FEAT_SME
0 1 != 0000 UNALLOCATED-
1 UNALLOCATED-

SVE predicate first active

The encodings in this section are decoded from SVE Predicate Misc.

313029282726252423222120191817161514131211109876543210
00100101opS0110001100000Pg0Pdn
Decode fields Instruction Details Feature
op S
0 0 UNALLOCATED-
0 1 PFIRSTFEAT_SVE || FEAT_SME
1 UNALLOCATED-

SVE predicate zero

The encodings in this section are decoded from SVE Predicate Misc.

313029282726252423222120191817161514131211109876543210
00100101opS011000111001000000Pd
Decode fields Instruction Details Feature
op S
0 0 PFALSEFEAT_SVE || FEAT_SME
0 1 UNALLOCATED-
1 UNALLOCATED-

SVE predicate read from FFR (predicated)

The encodings in this section are decoded from SVE Predicate Misc.

313029282726252423222120191817161514131211109876543210
00100101opS0110001111000Pg0Pd
Decode fields Instruction Details Feature
op S
0 0 RDFFR (predicated)FEAT_SVE
0 1 RDFFRSFEAT_SVE
1 UNALLOCATED-

SVE predicate read from FFR (unpredicated)

The encodings in this section are decoded from SVE Predicate Misc.

313029282726252423222120191817161514131211109876543210
00100101opS011001111100000000Pd
Decode fields Instruction Details Feature
op S
0 0 RDFFR (unpredicated)FEAT_SVE
0 1 UNALLOCATED-
1 UNALLOCATED-

SVE predicate initialize

The encodings in this section are decoded from SVE Predicate Misc.

313029282726252423222120191817161514131211109876543210
00100101size01100S111000pattern0Pd
Decode fields Instruction Details Feature
S
0 PTRUE (predicate)FEAT_SVE || FEAT_SME
1 PTRUESFEAT_SVE || FEAT_SME

SVE Predicate Count

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
0010010110010op0op1
Decode fieldsInstruction details
op0op1
000 1 SVE predicate count (predicate-as-counter)
0 SVE predicate count
!= 000 1 UNALLOCATED

SVE predicate count (predicate-as-counter)

The encodings in this section are decoded from SVE Predicate Count.

313029282726252423222120191817161514131211109876543210
00100101size100opc10000vl1PNnRd
Decode fields Instruction Details Feature
opc
000 CNTP (predicate as counter)FEAT_SME2 || FEAT_SVE2p1
!= 000 UNALLOCATED-

SVE predicate count

The encodings in this section are decoded from SVE Predicate Count.

313029282726252423222120191817161514131211109876543210
00100101size100opc10Pg0PnRd
Decode fields Instruction Details Feature
opc
000 CNTP (predicate)FEAT_SVE || FEAT_SME
001 FIRSTPFEAT_SVE2p2 || FEAT_SME2p2
010 LASTPFEAT_SVE2p2 || FEAT_SME2p2
011 UNALLOCATED-
1xx UNALLOCATED-

SVE Inc/Dec by Predicate Count

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
00100101101op01000op1
Decode fieldsInstruction details
op0op1
0 0 SVE saturating inc/dec vector by predicate count
0 1 SVE saturating inc/dec register by predicate count
1 0 SVE inc/dec vector by predicate count
1 1 SVE inc/dec register by predicate count

SVE saturating inc/dec vector by predicate count

The encodings in this section are decoded from SVE Inc/Dec by Predicate Count.

313029282726252423222120191817161514131211109876543210
00100101size1010DU10000opcPmZdn
Decode fields Instruction Details Feature
D U opc
!= 00 UNALLOCATED-
0 0 00 SQINCP (vector)FEAT_SVE || FEAT_SME
0 1 00 UQINCP (vector)FEAT_SVE || FEAT_SME
1 0 00 SQDECP (vector)FEAT_SVE || FEAT_SME
1 1 00 UQDECP (vector)FEAT_SVE || FEAT_SME

SVE saturating inc/dec register by predicate count

The encodings in this section are decoded from SVE Inc/Dec by Predicate Count.

313029282726252423222120191817161514131211109876543210
00100101size1010DU10001sfopPmRdn
Decode fields Instruction Details Feature
D U sf op
1 UNALLOCATED-
0 0 0 0 SQINCP (scalar) — 32-bitFEAT_SVE || FEAT_SME
0 0 1 0 SQINCP (scalar) — 64-bitFEAT_SVE || FEAT_SME
0 1 0 0 UQINCP (scalar) — 32-bitFEAT_SVE || FEAT_SME
0 1 1 0 UQINCP (scalar) — 64-bitFEAT_SVE || FEAT_SME
1 0 0 0 SQDECP (scalar) — 32-bitFEAT_SVE || FEAT_SME
1 0 1 0 SQDECP (scalar) — 64-bitFEAT_SVE || FEAT_SME
1 1 0 0 UQDECP (scalar) — 32-bitFEAT_SVE || FEAT_SME
1 1 1 0 UQDECP (scalar) — 64-bitFEAT_SVE || FEAT_SME

SVE inc/dec vector by predicate count

The encodings in this section are decoded from SVE Inc/Dec by Predicate Count.

313029282726252423222120191817161514131211109876543210
00100101size1011opD10000opc2PmZdn
Decode fields Instruction Details Feature
op D opc2
0 != 00 UNALLOCATED-
0 0 00 INCP (vector)FEAT_SVE || FEAT_SME
0 1 00 DECP (vector)FEAT_SVE || FEAT_SME
1 UNALLOCATED-

SVE inc/dec register by predicate count

The encodings in this section are decoded from SVE Inc/Dec by Predicate Count.

313029282726252423222120191817161514131211109876543210
00100101size1011opD10001opc2PmRdn
Decode fields Instruction Details Feature
op D opc2
0 != 00 UNALLOCATED-
0 0 00 INCP (scalar)FEAT_SVE || FEAT_SME
0 1 00 DECP (scalar)FEAT_SVE || FEAT_SME
1 UNALLOCATED-

SVE Write FFR

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
00100101101op0op11001op2op3op4
Decode fieldsInstruction details
op0op1op2op3op4
0 00 000 00000 SVE FFR write from predicate
1 00 000 0000 00000 SVE FFR initialise
1 00 000 != 0000 00000 UNALLOCATED
00 000 != 00000 UNALLOCATED
00 != 000 UNALLOCATED
!= 00 UNALLOCATED

SVE FFR write from predicate

The encodings in this section are decoded from SVE Write FFR.

313029282726252423222120191817161514131211109876543210
00100101opc1010001001000Pn00000
Decode fields Instruction Details Feature
opc
00 WRFFRFEAT_SVE
!= 00 UNALLOCATED-

SVE FFR initialise

The encodings in this section are decoded from SVE Write FFR.

313029282726252423222120191817161514131211109876543210
00100101opc1011001001000000000000
Decode fields Instruction Details Feature
opc
00 SETFFRFEAT_SVE
!= 00 UNALLOCATED-

SVE Integer Compare - Scalars

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
00100101100op0op1op2
Decode fieldsInstruction details
op0op1op2
0x SVE integer compare scalar count and limit
10 00 0000 SVE conditionally terminate scalars
10 00 != 0000 UNALLOCATED
11 00 SVE pointer conflict compare
1x != 00 UNALLOCATED

SVE integer compare scalar count and limit

The encodings in this section are decoded from SVE Integer Compare - Scalars.

313029282726252423222120191817161514131211109876543210
00100101size1Rm000sfUltRneqPd
Decode fields Instruction Details Feature
U lt eq
0 0 0 WHILEGE (predicate)FEAT_SVE2 || FEAT_SME
0 0 1 WHILEGT (predicate)FEAT_SVE2 || FEAT_SME
0 1 0 WHILELT (predicate)FEAT_SVE || FEAT_SME
0 1 1 WHILELE (predicate)FEAT_SVE || FEAT_SME
1 0 0 WHILEHS (predicate)FEAT_SVE2 || FEAT_SME
1 0 1 WHILEHI (predicate)FEAT_SVE2 || FEAT_SME
1 1 0 WHILELO (predicate)FEAT_SVE || FEAT_SME
1 1 1 WHILELS (predicate)FEAT_SVE || FEAT_SME

SVE conditionally terminate scalars

The encodings in this section are decoded from SVE Integer Compare - Scalars.

313029282726252423222120191817161514131211109876543210
00100101opsz1Rm001000Rnne0000
Decode fields Instruction Details Feature
op ne
0 UNALLOCATED-
1 0 CTERMEQ, CTERMNE — EqualFEAT_SVE || FEAT_SME
1 1 CTERMEQ, CTERMNE — Not equalFEAT_SVE || FEAT_SME

SVE pointer conflict compare

The encodings in this section are decoded from SVE Integer Compare - Scalars.

313029282726252423222120191817161514131211109876543210
00100101size1Rm001100RnrwPd
Decode fields Instruction Details Feature
rw
0 WHILEWRFEAT_SVE2 || FEAT_SME
1 WHILERWFEAT_SVE2 || FEAT_SME

SVE Scalar Integer Compare - Predicate-as-counter

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
001001011op001op1op21op3
Decode fieldsInstruction detailsFeature
op0op1op2op3
00000 110 SVE extract mask predicate from predicate-as-counter-
00000 111 000000 0 PTRUE (predicate as counter)FEAT_SME2 || FEAT_SVE2p1
00000 111 000000 1 UNALLOCATED-
00000 111 != 000000 UNALLOCATED-
01x SVE integer compare scalar count and limit (predicate pair)-
x0x SVE integer compare scalar count and limit (predicate-as-counter)-
!= 00000 11x UNALLOCATED-

SVE extract mask predicate from predicate-as-counter

The encodings in this section are decoded from SVE Scalar Integer Compare - Predicate-as-counter.

313029282726252423222120191817161514131211109876543210
00100101size10000001110opcPNn1Pd
Decode fields Instruction Details Feature
opc
0xx PEXT (predicate)FEAT_SME2 || FEAT_SVE2p1
10x PEXT (predicate pair)FEAT_SME2 || FEAT_SVE2p1
11x UNALLOCATED-

SVE integer compare scalar count and limit (predicate pair)

The encodings in this section are decoded from SVE Scalar Integer Compare - Predicate-as-counter.

313029282726252423222120191817161514131211109876543210
00100101size1Rm0101UltRn1Pdeq
Decode fields Instruction Details Feature
U lt eq
0 0 0 WHILEGE (predicate pair)FEAT_SME2 || FEAT_SVE2p1
0 0 1 WHILEGT (predicate pair)FEAT_SME2 || FEAT_SVE2p1
0 1 0 WHILELT (predicate pair)FEAT_SME2 || FEAT_SVE2p1
0 1 1 WHILELE (predicate pair)FEAT_SME2 || FEAT_SVE2p1
1 0 0 WHILEHS (predicate pair)FEAT_SME2 || FEAT_SVE2p1
1 0 1 WHILEHI (predicate pair)FEAT_SME2 || FEAT_SVE2p1
1 1 0 WHILELO (predicate pair)FEAT_SME2 || FEAT_SVE2p1
1 1 1 WHILELS (predicate pair)FEAT_SME2 || FEAT_SVE2p1

SVE integer compare scalar count and limit (predicate-as-counter)

The encodings in this section are decoded from SVE Scalar Integer Compare - Predicate-as-counter.

313029282726252423222120191817161514131211109876543210
00100101size1Rm01vl0UltRn1eqPNd
Decode fields Instruction Details Feature
U lt eq
0 0 0 WHILEGE (predicate as counter)FEAT_SME2 || FEAT_SVE2p1
0 0 1 WHILEGT (predicate as counter)FEAT_SME2 || FEAT_SVE2p1
0 1 0 WHILELT (predicate as counter)FEAT_SME2 || FEAT_SVE2p1
0 1 1 WHILELE (predicate as counter)FEAT_SME2 || FEAT_SVE2p1
1 0 0 WHILEHS (predicate as counter)FEAT_SME2 || FEAT_SVE2p1
1 0 1 WHILEHI (predicate as counter)FEAT_SME2 || FEAT_SVE2p1
1 1 0 WHILELO (predicate as counter)FEAT_SME2 || FEAT_SVE2p1
1 1 1 WHILELS (predicate as counter)FEAT_SME2 || FEAT_SVE2p1

SVE Integer Wide Immediate - Unpredicated

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
001001011op0op111
Decode fieldsInstruction details
op0op1
00 SVE integer add/subtract immediate (unpredicated)
01 SVE integer min/max immediate (unpredicated)
10 SVE integer multiply immediate (unpredicated)
11 0 SVE broadcast integer immediate (unpredicated)
11 1 SVE broadcast floating-point immediate (unpredicated)

SVE integer add/subtract immediate (unpredicated)

The encodings in this section are decoded from SVE Integer Wide Immediate - Unpredicated.

313029282726252423222120191817161514131211109876543210
00100101size100opc11shimm8Zdn
Decode fields Instruction Details Feature
opc
000 ADD (immediate)FEAT_SVE || FEAT_SME
001 SUB (immediate)FEAT_SVE || FEAT_SME
010 UNALLOCATED-
011 SUBR (immediate)FEAT_SVE || FEAT_SME
100 SQADD (immediate)FEAT_SVE || FEAT_SME
101 UQADD (immediate)FEAT_SVE || FEAT_SME
110 SQSUB (immediate)FEAT_SVE || FEAT_SME
111 UQSUB (immediate)FEAT_SVE || FEAT_SME

SVE integer min/max immediate (unpredicated)

The encodings in this section are decoded from SVE Integer Wide Immediate - Unpredicated.

313029282726252423222120191817161514131211109876543210
00100101size101opc11o2imm8Zdn
Decode fields Instruction Details Feature
opc o2
0xx 1 UNALLOCATED-
000 0 SMAX (immediate)FEAT_SVE || FEAT_SME
001 0 UMAX (immediate)FEAT_SVE || FEAT_SME
010 0 SMIN (immediate)FEAT_SVE || FEAT_SME
011 0 UMIN (immediate)FEAT_SVE || FEAT_SME
1xx UNALLOCATED-

SVE integer multiply immediate (unpredicated)

The encodings in this section are decoded from SVE Integer Wide Immediate - Unpredicated.

313029282726252423222120191817161514131211109876543210
00100101size110opc11o2imm8Zdn
Decode fields Instruction Details Feature
opc o2
000 0 MUL (immediate)FEAT_SVE || FEAT_SME
000 1 UNALLOCATED-
!= 000 UNALLOCATED-

SVE broadcast integer immediate (unpredicated)

The encodings in this section are decoded from SVE Integer Wide Immediate - Unpredicated.

313029282726252423222120191817161514131211109876543210
00100101size111opc011shimm8Zd
Decode fields Instruction Details Feature
opc
00 DUP (immediate)FEAT_SVE || FEAT_SME
!= 00 UNALLOCATED-

SVE broadcast floating-point immediate (unpredicated)

The encodings in this section are decoded from SVE Integer Wide Immediate - Unpredicated.

313029282726252423222120191817161514131211109876543210
00100101size111opc111o2imm8Zd
Decode fields Instruction Details Feature
opc o2
00 0 FDUPFEAT_SVE || FEAT_SME
00 1 UNALLOCATED-
!= 00 UNALLOCATED-

SVE Integer Multiply-Add - Unpredicated

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
0100010000op0
Decode fieldsInstruction detailsFeature
op0
0000x SVE integer dot product (unpredicated)-
0001x SVE2 saturating multiply-add interleaved long-
001xx CDOT (vectors)FEAT_SVE2 || FEAT_SME
01xxx SVE2 complex integer multiply-add-
10xxx SVE2 integer multiply-add long-
110xx SVE2 saturating multiply-add long-
1110x SVE2 saturating multiply-add high-
11110 SVE mixed sign dot product-
11111 UNALLOCATED-

SVE integer dot product (unpredicated)

The encodings in this section are decoded from SVE Integer Multiply-Add - Unpredicated.

313029282726252423222120191817161514131211109876543210
01000100size0Zm00000UZnZda
Decode fields Instruction Details Feature
U
0 SDOT (4-way, vectors)FEAT_SVE || FEAT_SME
1 UDOT (4-way, vectors)FEAT_SVE || FEAT_SME

SVE2 saturating multiply-add interleaved long

The encodings in this section are decoded from SVE Integer Multiply-Add - Unpredicated.

313029282726252423222120191817161514131211109876543210
01000100size0Zm00001SZnZda
Decode fields Instruction Details Feature
S
0 SQDMLALBTFEAT_SVE2 || FEAT_SME
1 SQDMLSLBTFEAT_SVE2 || FEAT_SME

SVE2 complex integer multiply-add

The encodings in this section are decoded from SVE Integer Multiply-Add - Unpredicated.

313029282726252423222120191817161514131211109876543210
01000100size0Zm001oprotZnZda
Decode fields Instruction Details Feature
op
0 CMLA (vectors)FEAT_SVE2 || FEAT_SME
1 SQRDCMLAH (vectors)FEAT_SVE2 || FEAT_SME

SVE2 integer multiply-add long

The encodings in this section are decoded from SVE Integer Multiply-Add - Unpredicated.

313029282726252423222120191817161514131211109876543210
01000100size0Zm010SUTZnZda
Decode fields Instruction Details Feature
S U T
0 0 0 SMLALB (vectors)FEAT_SVE2 || FEAT_SME
0 0 1 SMLALT (vectors)FEAT_SVE2 || FEAT_SME
0 1 0 UMLALB (vectors)FEAT_SVE2 || FEAT_SME
0 1 1 UMLALT (vectors)FEAT_SVE2 || FEAT_SME
1 0 0 SMLSLB (vectors)FEAT_SVE2 || FEAT_SME
1 0 1 SMLSLT (vectors)FEAT_SVE2 || FEAT_SME
1 1 0 UMLSLB (vectors)FEAT_SVE2 || FEAT_SME
1 1 1 UMLSLT (vectors)FEAT_SVE2 || FEAT_SME

SVE2 saturating multiply-add long

The encodings in this section are decoded from SVE Integer Multiply-Add - Unpredicated.

313029282726252423222120191817161514131211109876543210
01000100size0Zm0110STZnZda
Decode fields Instruction Details Feature
S T
0 0 SQDMLALB (vectors)FEAT_SVE2 || FEAT_SME
0 1 SQDMLALT (vectors)FEAT_SVE2 || FEAT_SME
1 0 SQDMLSLB (vectors)FEAT_SVE2 || FEAT_SME
1 1 SQDMLSLT (vectors)FEAT_SVE2 || FEAT_SME

SVE2 saturating multiply-add high

The encodings in this section are decoded from SVE Integer Multiply-Add - Unpredicated.

313029282726252423222120191817161514131211109876543210
01000100size0Zm01110SZnZda
Decode fields Instruction Details Feature
S
0 SQRDMLAH (vectors)FEAT_SVE2 || FEAT_SME
1 SQRDMLSH (vectors)FEAT_SVE2 || FEAT_SME

SVE mixed sign dot product

The encodings in this section are decoded from SVE Integer Multiply-Add - Unpredicated.

313029282726252423222120191817161514131211109876543210
01000100size0Zm011110ZnZda
Decode fields Instruction Details Feature
size
10 USDOT (vectors)(FEAT_SVE && FEAT_I8MM) || (FEAT_SME && FEAT_I8MM)
!= 10 UNALLOCATED-

SVE2 Integer - Predicated

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
010001000op010op1
Decode fieldsInstruction details
op0op1
0010 1 SVE2 integer pairwise add and accumulate long
0011 1 UNALLOCATED
011x 1 UNALLOCATED
0x0x 1 SVE2 integer unary operations (predicated)
0xxx 0 SVE2 saturating/rounding bitwise shift left (predicated)
10xx 0 SVE2 integer halving add/subtract (predicated)
10xx 1 SVE2 integer pairwise arithmetic
11xx 0 SVE2 saturating add/subtract
11xx 1 UNALLOCATED

SVE2 integer pairwise add and accumulate long

The encodings in this section are decoded from SVE2 Integer - Predicated.

313029282726252423222120191817161514131211109876543210
01000100size00010U101PgZnZda
Decode fields Instruction Details Feature
U
0 SADALPFEAT_SVE2 || FEAT_SME
1 UADALPFEAT_SVE2 || FEAT_SME

SVE2 integer unary operations (predicated)

The encodings in this section are decoded from SVE2 Integer - Predicated.

313029282726252423222120191817161514131211109876543210
01000100size00Q0Zop101PgZnZd
Decode fields Instruction Details Feature
Q Z op
0 0 0 URECPE — MergingFEAT_SVE2 || FEAT_SME
0 0 1 URSQRTE — MergingFEAT_SVE2 || FEAT_SME
0 1 0 URECPE — ZeroingFEAT_SVE2p2 || FEAT_SME2p2
0 1 1 URSQRTE — ZeroingFEAT_SVE2p2 || FEAT_SME2p2
1 0 0 SQABS — MergingFEAT_SVE2 || FEAT_SME
1 0 1 SQNEG — MergingFEAT_SVE2 || FEAT_SME
1 1 0 SQABS — ZeroingFEAT_SVE2p2 || FEAT_SME2p2
1 1 1 SQNEG — ZeroingFEAT_SVE2p2 || FEAT_SME2p2

SVE2 saturating/rounding bitwise shift left (predicated)

The encodings in this section are decoded from SVE2 Integer - Predicated.

313029282726252423222120191817161514131211109876543210
01000100size00QRNU100PgZmZdn
Decode fields Instruction Details Feature
Q R N U
0 0 UNALLOCATED-
0 0 1 0 SRSHLFEAT_SVE2 || FEAT_SME
0 0 1 1 URSHLFEAT_SVE2 || FEAT_SME
0 1 1 0 SRSHLRFEAT_SVE2 || FEAT_SME
0 1 1 1 URSHLRFEAT_SVE2 || FEAT_SME
1 0 0 0 SQSHL (vectors)FEAT_SVE2 || FEAT_SME
1 0 0 1 UQSHL (vectors)FEAT_SVE2 || FEAT_SME
1 0 1 0 SQRSHLFEAT_SVE2 || FEAT_SME
1 0 1 1 UQRSHLFEAT_SVE2 || FEAT_SME
1 1 0 0 SQSHLRFEAT_SVE2 || FEAT_SME
1 1 0 1 UQSHLRFEAT_SVE2 || FEAT_SME
1 1 1 0 SQRSHLRFEAT_SVE2 || FEAT_SME
1 1 1 1 UQRSHLRFEAT_SVE2 || FEAT_SME

SVE2 integer halving add/subtract (predicated)

The encodings in this section are decoded from SVE2 Integer - Predicated.

313029282726252423222120191817161514131211109876543210
01000100size010RSU100PgZmZdn
Decode fields Instruction Details Feature
R S U
0 0 0 SHADDFEAT_SVE2 || FEAT_SME
0 0 1 UHADDFEAT_SVE2 || FEAT_SME
0 1 0 SHSUBFEAT_SVE2 || FEAT_SME
0 1 1 UHSUBFEAT_SVE2 || FEAT_SME
1 0 0 SRHADDFEAT_SVE2 || FEAT_SME
1 0 1 URHADDFEAT_SVE2 || FEAT_SME
1 1 0 SHSUBRFEAT_SVE2 || FEAT_SME
1 1 1 UHSUBRFEAT_SVE2 || FEAT_SME

SVE2 integer pairwise arithmetic

The encodings in this section are decoded from SVE2 Integer - Predicated.

313029282726252423222120191817161514131211109876543210
01000100size010opcU101PgZmZdn
Decode fields Instruction Details Feature
opc U
00 0 UNALLOCATED-
00 1 ADDPFEAT_SVE2 || FEAT_SME
01 UNALLOCATED-
10 0 SMAXPFEAT_SVE2 || FEAT_SME
10 1 UMAXPFEAT_SVE2 || FEAT_SME
11 0 SMINPFEAT_SVE2 || FEAT_SME
11 1 UMINPFEAT_SVE2 || FEAT_SME

SVE2 saturating add/subtract

The encodings in this section are decoded from SVE2 Integer - Predicated.

313029282726252423222120191817161514131211109876543210
01000100size011opSU100PgZmZdn
Decode fields Instruction Details Feature
op S U
0 0 0 SQADD (vectors, predicated)FEAT_SVE2 || FEAT_SME
0 0 1 UQADD (vectors, predicated)FEAT_SVE2 || FEAT_SME
0 1 0 SQSUB (vectors, predicated)FEAT_SVE2 || FEAT_SME
0 1 1 UQSUB (vectors, predicated)FEAT_SVE2 || FEAT_SME
1 0 0 SUQADDFEAT_SVE2 || FEAT_SME
1 0 1 USQADDFEAT_SVE2 || FEAT_SME
1 1 0 SQSUBRFEAT_SVE2 || FEAT_SME
1 1 1 UQSUBRFEAT_SVE2 || FEAT_SME

SVE Multiply - Indexed

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
010001001op0
Decode fieldsInstruction details
op0
00000x SVE integer dot product (indexed)
00001x SVE2 integer multiply-add (indexed)
00010x SVE2 saturating multiply-add high (indexed)
00011x SVE mixed sign dot product (indexed)
001xxx SVE2 saturating multiply-add (indexed)
0100xx SVE2 complex integer dot product (indexed)
0101xx UNALLOCATED
0110xx SVE2 complex integer multiply-add (indexed)
0111xx SVE2 complex saturating multiply-add (indexed)
10xxxx SVE2 integer multiply-add long (indexed)
110xxx SVE2 integer multiply long (indexed)
1110xx SVE2 saturating multiply (indexed)
11110x SVE2 saturating multiply high (indexed)
111110 SVE2 integer multiply (indexed)
111111 UNALLOCATED

SVE integer dot product (indexed)

The encodings in this section are decoded from SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc00000UZnZda
Decode fields Instruction Details Feature
size U
0x UNALLOCATED-
10 0 SDOT (4-way, indexed) — 32-bitFEAT_SVE || FEAT_SME
10 1 UDOT (4-way, indexed) — 32-bitFEAT_SVE || FEAT_SME
11 0 SDOT (4-way, indexed) — 64-bitFEAT_SVE || FEAT_SME
11 1 UDOT (4-way, indexed) — 64-bitFEAT_SVE || FEAT_SME

SVE2 integer multiply-add (indexed)

The encodings in this section are decoded from SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc00001SZnZda
Decode fields Instruction Details Feature
size S
0x 0 MLA (indexed) — 16-bitFEAT_SVE2 || FEAT_SME
0x 1 MLS (indexed) — 16-bitFEAT_SVE2 || FEAT_SME
10 0 MLA (indexed) — 32-bitFEAT_SVE2 || FEAT_SME
10 1 MLS (indexed) — 32-bitFEAT_SVE2 || FEAT_SME
11 0 MLA (indexed) — 64-bitFEAT_SVE2 || FEAT_SME
11 1 MLS (indexed) — 64-bitFEAT_SVE2 || FEAT_SME

SVE2 saturating multiply-add high (indexed)

The encodings in this section are decoded from SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc00010SZnZda
Decode fields Instruction Details Feature
size S
0x 0 SQRDMLAH (indexed) — 16-bitFEAT_SVE2 || FEAT_SME
0x 1 SQRDMLSH (indexed) — 16-bitFEAT_SVE2 || FEAT_SME
10 0 SQRDMLAH (indexed) — 32-bitFEAT_SVE2 || FEAT_SME
10 1 SQRDMLSH (indexed) — 32-bitFEAT_SVE2 || FEAT_SME
11 0 SQRDMLAH (indexed) — 64-bitFEAT_SVE2 || FEAT_SME
11 1 SQRDMLSH (indexed) — 64-bitFEAT_SVE2 || FEAT_SME

SVE mixed sign dot product (indexed)

The encodings in this section are decoded from SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc00011UZnZda
Decode fields Instruction Details Feature
size U
10 0 USDOT (indexed)(FEAT_SVE && FEAT_I8MM) || (FEAT_SME && FEAT_I8MM)
10 1 SUDOT(FEAT_SVE && FEAT_I8MM) || (FEAT_SME && FEAT_I8MM)
!= 10 UNALLOCATED-

SVE2 saturating multiply-add (indexed)

The encodings in this section are decoded from SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc001SilTZnZda
Decode fields Instruction Details Feature
size S T
0x UNALLOCATED-
10 0 0 SQDMLALB (indexed) — 32-bitFEAT_SVE2 || FEAT_SME
10 0 1 SQDMLALT (indexed) — 32-bitFEAT_SVE2 || FEAT_SME
10 1 0 SQDMLSLB (indexed) — 32-bitFEAT_SVE2 || FEAT_SME
10 1 1 SQDMLSLT (indexed) — 32-bitFEAT_SVE2 || FEAT_SME
11 0 0 SQDMLALB (indexed) — 64-bitFEAT_SVE2 || FEAT_SME
11 0 1 SQDMLALT (indexed) — 64-bitFEAT_SVE2 || FEAT_SME
11 1 0 SQDMLSLB (indexed) — 64-bitFEAT_SVE2 || FEAT_SME
11 1 1 SQDMLSLT (indexed) — 64-bitFEAT_SVE2 || FEAT_SME

SVE2 complex integer dot product (indexed)

The encodings in this section are decoded from SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc0100rotZnZda
Decode fields Instruction Details Feature
size
0x UNALLOCATED-
10 CDOT (indexed) — 32-bitFEAT_SVE2 || FEAT_SME
11 CDOT (indexed) — 64-bitFEAT_SVE2 || FEAT_SME

SVE2 complex integer multiply-add (indexed)

The encodings in this section are decoded from SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc0110rotZnZda
Decode fields Instruction Details Feature
size
0x UNALLOCATED-
10 CMLA (indexed) — 16-bitFEAT_SVE2 || FEAT_SME
11 CMLA (indexed) — 32-bitFEAT_SVE2 || FEAT_SME

SVE2 complex saturating multiply-add (indexed)

The encodings in this section are decoded from SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc0111rotZnZda
Decode fields Instruction Details Feature
size
0x UNALLOCATED-
10 SQRDCMLAH (indexed) — 16-bitFEAT_SVE2 || FEAT_SME
11 SQRDCMLAH (indexed) — 32-bitFEAT_SVE2 || FEAT_SME

SVE2 integer multiply-add long (indexed)

The encodings in this section are decoded from SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc10SUilTZnZda
Decode fields Instruction Details Feature
size S U T
0x UNALLOCATED-
10 0 0 0 SMLALB (indexed) — 32-bitFEAT_SVE2 || FEAT_SME
10 0 0 1 SMLALT (indexed) — 32-bitFEAT_SVE2 || FEAT_SME
10 0 1 0 UMLALB (indexed) — 32-bitFEAT_SVE2 || FEAT_SME
10 0 1 1 UMLALT (indexed) — 32-bitFEAT_SVE2 || FEAT_SME
10 1 0 0 SMLSLB (indexed) — 32-bitFEAT_SVE2 || FEAT_SME
10 1 0 1 SMLSLT (indexed) — 32-bitFEAT_SVE2 || FEAT_SME
10 1 1 0 UMLSLB (indexed) — 32-bitFEAT_SVE2 || FEAT_SME
10 1 1 1 UMLSLT (indexed) — 32-bitFEAT_SVE2 || FEAT_SME
11 0 0 0 SMLALB (indexed) — 64-bitFEAT_SVE2 || FEAT_SME
11 0 0 1 SMLALT (indexed) — 64-bitFEAT_SVE2 || FEAT_SME
11 0 1 0 UMLALB (indexed) — 64-bitFEAT_SVE2 || FEAT_SME
11 0 1 1 UMLALT (indexed) — 64-bitFEAT_SVE2 || FEAT_SME
11 1 0 0 SMLSLB (indexed) — 64-bitFEAT_SVE2 || FEAT_SME
11 1 0 1 SMLSLT (indexed) — 64-bitFEAT_SVE2 || FEAT_SME
11 1 1 0 UMLSLB (indexed) — 64-bitFEAT_SVE2 || FEAT_SME
11 1 1 1 UMLSLT (indexed) — 64-bitFEAT_SVE2 || FEAT_SME

SVE2 integer multiply long (indexed)

The encodings in this section are decoded from SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc110UilTZnZd
Decode fields Instruction Details Feature
size U T
0x UNALLOCATED-
10 0 0 SMULLB (indexed) — 32-bitFEAT_SVE2 || FEAT_SME
10 0 1 SMULLT (indexed) — 32-bitFEAT_SVE2 || FEAT_SME
10 1 0 UMULLB (indexed) — 32-bitFEAT_SVE2 || FEAT_SME
10 1 1 UMULLT (indexed) — 32-bitFEAT_SVE2 || FEAT_SME
11 0 0 SMULLB (indexed) — 64-bitFEAT_SVE2 || FEAT_SME
11 0 1 SMULLT (indexed) — 64-bitFEAT_SVE2 || FEAT_SME
11 1 0 UMULLB (indexed) — 64-bitFEAT_SVE2 || FEAT_SME
11 1 1 UMULLT (indexed) — 64-bitFEAT_SVE2 || FEAT_SME

SVE2 saturating multiply (indexed)

The encodings in this section are decoded from SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc1110ilTZnZd
Decode fields Instruction Details Feature
size T
0x UNALLOCATED-
10 0 SQDMULLB (indexed) — 32-bitFEAT_SVE2 || FEAT_SME
10 1 SQDMULLT (indexed) — 32-bitFEAT_SVE2 || FEAT_SME
11 0 SQDMULLB (indexed) — 64-bitFEAT_SVE2 || FEAT_SME
11 1 SQDMULLT (indexed) — 64-bitFEAT_SVE2 || FEAT_SME

SVE2 saturating multiply high (indexed)

The encodings in this section are decoded from SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc11110RZnZd
Decode fields Instruction Details Feature
size R
0x 0 SQDMULH (indexed) — 16-bitFEAT_SVE2 || FEAT_SME
0x 1 SQRDMULH (indexed) — 16-bitFEAT_SVE2 || FEAT_SME
10 0 SQDMULH (indexed) — 32-bitFEAT_SVE2 || FEAT_SME
10 1 SQRDMULH (indexed) — 32-bitFEAT_SVE2 || FEAT_SME
11 0 SQDMULH (indexed) — 64-bitFEAT_SVE2 || FEAT_SME
11 1 SQRDMULH (indexed) — 64-bitFEAT_SVE2 || FEAT_SME

SVE2 integer multiply (indexed)

The encodings in this section are decoded from SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc111110ZnZd
Decode fields Instruction Details Feature
size
0x MUL (indexed) — 16-bitFEAT_SVE2 || FEAT_SME
10 MUL (indexed) — 32-bitFEAT_SVE2 || FEAT_SME
11 MUL (indexed) — 64-bitFEAT_SVE2 || FEAT_SME

SVE2 Widening Integer Arithmetic

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
0100010100op0
Decode fieldsInstruction details
op0
0x SVE2 integer add/subtract long
10 SVE2 integer add/subtract wide
11 SVE2 integer multiply long

SVE2 integer add/subtract long

The encodings in this section are decoded from SVE2 Widening Integer Arithmetic.

313029282726252423222120191817161514131211109876543210
01000101size0Zm00opSUTZnZd
Decode fields Instruction Details Feature
op S U T
0 0 0 0 SADDLBFEAT_SVE2 || FEAT_SME
0 0 0 1 SADDLTFEAT_SVE2 || FEAT_SME
0 0 1 0 UADDLBFEAT_SVE2 || FEAT_SME
0 0 1 1 UADDLTFEAT_SVE2 || FEAT_SME
0 1 0 0 SSUBLBFEAT_SVE2 || FEAT_SME
0 1 0 1 SSUBLTFEAT_SVE2 || FEAT_SME
0 1 1 0 USUBLBFEAT_SVE2 || FEAT_SME
0 1 1 1 USUBLTFEAT_SVE2 || FEAT_SME
1 0 UNALLOCATED-
1 1 0 0 SABDLBFEAT_SVE2 || FEAT_SME
1 1 0 1 SABDLTFEAT_SVE2 || FEAT_SME
1 1 1 0 UABDLBFEAT_SVE2 || FEAT_SME
1 1 1 1 UABDLTFEAT_SVE2 || FEAT_SME

SVE2 integer add/subtract wide

The encodings in this section are decoded from SVE2 Widening Integer Arithmetic.

313029282726252423222120191817161514131211109876543210
01000101size0Zm010SUTZnZd
Decode fields Instruction Details Feature
S U T
0 0 0 SADDWBFEAT_SVE2 || FEAT_SME
0 0 1 SADDWTFEAT_SVE2 || FEAT_SME
0 1 0 UADDWBFEAT_SVE2 || FEAT_SME
0 1 1 UADDWTFEAT_SVE2 || FEAT_SME
1 0 0 SSUBWBFEAT_SVE2 || FEAT_SME
1 0 1 SSUBWTFEAT_SVE2 || FEAT_SME
1 1 0 USUBWBFEAT_SVE2 || FEAT_SME
1 1 1 USUBWTFEAT_SVE2 || FEAT_SME

SVE2 integer multiply long

The encodings in this section are decoded from SVE2 Widening Integer Arithmetic.

313029282726252423222120191817161514131211109876543210
01000101size0Zm011opUTZnZd
Decode fields Instruction Details Feature
size op U T
0 0 0 SQDMULLB (vectors)FEAT_SVE2 || FEAT_SME
0 0 1 SQDMULLT (vectors)FEAT_SVE2 || FEAT_SME
1 0 0 SMULLB (vectors)FEAT_SVE2 || FEAT_SME
1 0 1 SMULLT (vectors)FEAT_SVE2 || FEAT_SME
1 1 0 UMULLB (vectors)FEAT_SVE2 || FEAT_SME
1 1 1 UMULLT (vectors)FEAT_SVE2 || FEAT_SME
00 0 1 0 PMULLB — 128-bit elementFEAT_SVE_PMULL128
00 0 1 1 PMULLT — 128-bit elementFEAT_SVE_PMULL128
!= 00 0 1 0 PMULLB — 16-bit or 64-bit elementsFEAT_SVE2 || FEAT_SME
!= 00 0 1 1 PMULLT — 16-bit or 64-bit elementsFEAT_SVE2 || FEAT_SME

SVE Misc

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01000101op0010op1
Decode fieldsInstruction details
op0op1
0 10xx SVE2 bitwise shift left long
1 10xx UNALLOCATED
00xx SVE2 integer add/subtract interleaved long
010x SVE2 bitwise exclusive-OR interleaved
0110 SVE integer matrix multiply accumulate
0111 UNALLOCATED
11xx SVE2 bitwise permute

SVE2 bitwise shift left long

The encodings in this section are decoded from SVE Misc.

313029282726252423222120191817161514131211109876543210
010001010tszh0tszlimm31010UTZnZd
Decode fields Instruction Details Feature
U T
0 0 SSHLLBFEAT_SVE2 || FEAT_SME
0 1 SSHLLTFEAT_SVE2 || FEAT_SME
1 0 USHLLBFEAT_SVE2 || FEAT_SME
1 1 USHLLTFEAT_SVE2 || FEAT_SME

SVE2 integer add/subtract interleaved long

The encodings in this section are decoded from SVE Misc.

313029282726252423222120191817161514131211109876543210
01000101size0Zm1000StbZnZd
Decode fields Instruction Details Feature
S tb
0 0 SADDLBTFEAT_SVE2 || FEAT_SME
0 1 UNALLOCATED-
1 0 SSUBLBTFEAT_SVE2 || FEAT_SME
1 1 SSUBLTBFEAT_SVE2 || FEAT_SME

SVE2 bitwise exclusive-OR interleaved

The encodings in this section are decoded from SVE Misc.

313029282726252423222120191817161514131211109876543210
01000101size0Zm10010tbZnZd
Decode fields Instruction Details Feature
tb
0 EORBTFEAT_SVE2 || FEAT_SME
1 EORTBFEAT_SVE2 || FEAT_SME

SVE integer matrix multiply accumulate

The encodings in this section are decoded from SVE Misc.

313029282726252423222120191817161514131211109876543210
01000101uns0Zm100110ZnZd
Decode fields Instruction Details Feature
uns
00 SMMLAFEAT_SVE && FEAT_I8MM
01 UNALLOCATED-
10 USMMLAFEAT_SVE && FEAT_I8MM
11 UMMLAFEAT_SVE && FEAT_I8MM

SVE2 bitwise permute

The encodings in this section are decoded from SVE Misc.

313029282726252423222120191817161514131211109876543210
01000101size0Zm1011opcZnZd
Decode fields Instruction Details Feature
opc
00 BEXTFEAT_SVE_BitPerm
01 BDEPFEAT_SVE_BitPerm
10 BGRPFEAT_SVE_BitPerm
11 UNALLOCATED-

SVE2 Accumulate

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
010001010op011op1
Decode fieldsInstruction details
op0op1
0000 011 SVE2 complex integer add
00x SVE2 integer absolute difference and accumulate long
010 SVE2 integer add/subtract long with carry
10x SVE2 bitwise shift right and accumulate
110 SVE2 bitwise shift and insert
111 SVE2 integer absolute difference and accumulate
!= 0000 011 UNALLOCATED

SVE2 complex integer add

The encodings in this section are decoded from SVE2 Accumulate.

313029282726252423222120191817161514131211109876543210
01000101size00000op11011rotZmZdn
Decode fields Instruction Details Feature
op
0 CADDFEAT_SVE2 || FEAT_SME
1 SQCADDFEAT_SVE2 || FEAT_SME

SVE2 integer absolute difference and accumulate long

The encodings in this section are decoded from SVE2 Accumulate.

313029282726252423222120191817161514131211109876543210
01000101size0Zm1100UTZnZda
Decode fields Instruction Details Feature
U T
0 0 SABALBFEAT_SVE2 || FEAT_SME
0 1 SABALTFEAT_SVE2 || FEAT_SME
1 0 UABALBFEAT_SVE2 || FEAT_SME
1 1 UABALTFEAT_SVE2 || FEAT_SME

SVE2 integer add/subtract long with carry

The encodings in this section are decoded from SVE2 Accumulate.

313029282726252423222120191817161514131211109876543210
01000101size0Zm11010TZnZda
Decode fields Instruction Details Feature
size T
0x 0 ADCLBFEAT_SVE2 || FEAT_SME
0x 1 ADCLTFEAT_SVE2 || FEAT_SME
1x 0 SBCLBFEAT_SVE2 || FEAT_SME
1x 1 SBCLTFEAT_SVE2 || FEAT_SME

SVE2 bitwise shift right and accumulate

The encodings in this section are decoded from SVE2 Accumulate.

313029282726252423222120191817161514131211109876543210
01000101tszh0tszlimm31110RUZnZda
Decode fields Instruction Details Feature
R U
0 0 SSRAFEAT_SVE2 || FEAT_SME
0 1 USRAFEAT_SVE2 || FEAT_SME
1 0 SRSRAFEAT_SVE2 || FEAT_SME
1 1 URSRAFEAT_SVE2 || FEAT_SME

SVE2 bitwise shift and insert

The encodings in this section are decoded from SVE2 Accumulate.

313029282726252423222120191817161514131211109876543210
01000101tszh0tszlimm311110opZnZd
Decode fields Instruction Details Feature
op
0 SRIFEAT_SVE2 || FEAT_SME
1 SLIFEAT_SVE2 || FEAT_SME

SVE2 integer absolute difference and accumulate

The encodings in this section are decoded from SVE2 Accumulate.

313029282726252423222120191817161514131211109876543210
01000101size0Zm11111UZnZda
Decode fields Instruction Details Feature
U
0 SABAFEAT_SVE2 || FEAT_SME
1 UABAFEAT_SVE2 || FEAT_SME

SVE2 Narrowing

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01000101op01op1op20op3op4op5
Decode fieldsInstruction details
op0op1op2op3op4op5
0 00 0 10 SVE2 saturating extract narrow
0 00 1 10 0 0 SME2 multi-vec extract narrow
0 00 1 10 0 1 UNALLOCATED
0 00 1 10 1 UNALLOCATED
0 0x SVE2 bitwise shift right narrow
0 != 00 10 UNALLOCATED
1 0x 0 0 SME2 multi-vec shift narrow
1 0x 0 1 UNALLOCATED
1 0x 1 UNALLOCATED
1 10 UNALLOCATED
11 SVE2 integer add/subtract narrow high part

SVE2 saturating extract narrow

The encodings in this section are decoded from SVE2 Narrowing.

313029282726252423222120191817161514131211109876543210
010001010tszh1tszl000010opcTZnZd
Decode fields Instruction Details Feature
opc T
00 0 SQXTNBFEAT_SVE2 || FEAT_SME
00 1 SQXTNTFEAT_SVE2 || FEAT_SME
01 0 UQXTNBFEAT_SVE2 || FEAT_SME
01 1 UQXTNTFEAT_SVE2 || FEAT_SME
10 0 SQXTUNBFEAT_SVE2 || FEAT_SME
10 1 SQXTUNTFEAT_SVE2 || FEAT_SME
11 UNALLOCATED-

SME2 multi-vec extract narrow

The encodings in this section are decoded from SVE2 Narrowing.

313029282726252423222120191817161514131211109876543210
010001010tszh1tszl001010opc0Zn0Zd
Decode fields Instruction Details Feature
tszh tszl opc
0 10 00 SQCVTNFEAT_SME2 || FEAT_SVE2p1
0 10 01 UQCVTNFEAT_SME2 || FEAT_SVE2p1
0 10 10 SQCVTUNFEAT_SME2 || FEAT_SVE2p1
0 10 11 UNALLOCATED-
0 != 10 UNALLOCATED-
1 UNALLOCATED-

SVE2 bitwise shift right narrow

The encodings in this section are decoded from SVE2 Narrowing.

313029282726252423222120191817161514131211109876543210
010001010tszh1tszlimm300opURTZnZd
Decode fields Instruction Details Feature
op U R T
0 0 0 0 SQSHRUNBFEAT_SVE2 || FEAT_SME
0 0 0 1 SQSHRUNTFEAT_SVE2 || FEAT_SME
0 0 1 0 SQRSHRUNBFEAT_SVE2 || FEAT_SME
0 0 1 1 SQRSHRUNTFEAT_SVE2 || FEAT_SME
0 1 0 0 SHRNBFEAT_SVE2 || FEAT_SME
0 1 0 1 SHRNTFEAT_SVE2 || FEAT_SME
0 1 1 0 RSHRNBFEAT_SVE2 || FEAT_SME
0 1 1 1 RSHRNTFEAT_SVE2 || FEAT_SME
1 0 0 0 SQSHRNBFEAT_SVE2 || FEAT_SME
1 0 0 1 SQSHRNTFEAT_SVE2 || FEAT_SME
1 0 1 0 SQRSHRNBFEAT_SVE2 || FEAT_SME
1 0 1 1 SQRSHRNTFEAT_SVE2 || FEAT_SME
1 1 0 0 UQSHRNBFEAT_SVE2 || FEAT_SME
1 1 0 1 UQSHRNTFEAT_SVE2 || FEAT_SME
1 1 1 0 UQRSHRNBFEAT_SVE2 || FEAT_SME
1 1 1 1 UQRSHRNTFEAT_SVE2 || FEAT_SME

SME2 multi-vec shift narrow

The encodings in this section are decoded from SVE2 Narrowing.

313029282726252423222120191817161514131211109876543210
010001011tszh1tszlimm400opUR0Zn0Zd
Decode fields Instruction Details Feature
tszh tszl op U R
0 0 UNALLOCATED-
0 1 0 UNALLOCATED-
0 1 0 0 1 SQRSHRUNFEAT_SME2 || FEAT_SVE2p1
0 1 0 1 1 UNALLOCATED-
0 1 1 0 1 SQRSHRNFEAT_SME2 || FEAT_SVE2p1
0 1 1 1 1 UQRSHRNFEAT_SME2 || FEAT_SVE2p1
1 UNALLOCATED-

SVE2 integer add/subtract narrow high part

The encodings in this section are decoded from SVE2 Narrowing.

313029282726252423222120191817161514131211109876543210
01000101size1Zm011SRTZnZd
Decode fields Instruction Details Feature
S R T
0 0 0 ADDHNBFEAT_SVE2 || FEAT_SME
0 0 1 ADDHNTFEAT_SVE2 || FEAT_SME
0 1 0 RADDHNBFEAT_SVE2 || FEAT_SME
0 1 1 RADDHNTFEAT_SVE2 || FEAT_SME
1 0 0 SUBHNBFEAT_SVE2 || FEAT_SME
1 0 1 SUBHNTFEAT_SVE2 || FEAT_SME
1 1 0 RSUBHNBFEAT_SVE2 || FEAT_SME
1 1 1 RSUBHNTFEAT_SVE2 || FEAT_SME

SVE2 Histogram Computation (Segment) and Lookup Table

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01000101op01101op1
Decode fieldsInstruction detailsFeature
op0op1
0 0x1 UNALLOCATED-
1 001 LUTI4 — Byte, single register table(FEAT_SVE2 && FEAT_LUT) || (FEAT_SME2 && FEAT_LUT)
1 011 UNALLOCATED-
000 HISTSEGFEAT_SVE2
100 LUTI2 — Byte(FEAT_SVE2 && FEAT_LUT) || (FEAT_SME2 && FEAT_LUT)
1x1 SVE2 lookup table with 4-bit indices and 16-bit element size-
x10 LUTI2 — Halfword(FEAT_SVE2 && FEAT_LUT) || (FEAT_SME2 && FEAT_LUT)

SVE2 lookup table with 4-bit indices and 16-bit element size

The encodings in this section are decoded from SVE2 Histogram Computation (Segment) and Lookup Table.

313029282726252423222120191817161514131211109876543210
01000101i21Zm1011op1ZnZd
Decode fields Instruction Details Feature
op
0 LUTI4 — Halfword, two register table(FEAT_SVE2 && FEAT_LUT) || (FEAT_SME2 && FEAT_LUT)
1 LUTI4 — Halfword, single register table(FEAT_SVE2 && FEAT_LUT) || (FEAT_SME2 && FEAT_LUT)

SVE2 Crypto Extensions

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
010001011op0op1111op2op3op4
Decode fieldsInstruction details
op0op1op2op3op4
000 00 00x 00000 SVE2 crypto unary operations
000 00 00x != 00000 UNALLOCATED
000 01 00x UNALLOCATED
000 1x 00x SVE2 crypto destructive binary operations
xx0 1x 01x SVE2 multi-vector AES single round (two registers)
xx1 1x 01x SVE2 multi-vector AES single round (four registers)
00 01x UNALLOCATED
01 01x UNALLOCATED
10x SVE2 crypto constructive binary operations
110 0 SVE2 Multi-vector polynomial multiply long
111 0 SVE2 Multi-vector polynomial multiply long and accumulate vectors
11x 1 UNALLOCATED
!= 000 00x UNALLOCATED

SVE2 crypto unary operations

The encodings in this section are decoded from SVE2 Crypto Extensions.

313029282726252423222120191817161514131211109876543210
01000101size10000011100op00000Zdn
Decode fields Instruction Details Feature
size op
00 0 AESMCFEAT_SVE_AES
00 1 AESIMCFEAT_SVE_AES
!= 00 UNALLOCATED-

SVE2 crypto destructive binary operations

The encodings in this section are decoded from SVE2 Crypto Extensions.

313029282726252423222120191817161514131211109876543210
01000101size10001op11100o2ZmZdn
Decode fields Instruction Details Feature
size op o2
00 0 0 AESE (vectors)FEAT_SVE_AES
00 0 1 AESD (vectors)FEAT_SVE_AES
00 1 0 SM4EFEAT_SVE_SM4
00 1 1 UNALLOCATED-
!= 00 UNALLOCATED-

SVE2 multi-vector AES single round (two registers)

The encodings in this section are decoded from SVE2 Crypto Extensions.

313029282726252423222120191817161514131211109876543210
01000101size1i201op11101o2ZmZdno3
Decode fields Instruction Details Feature
size op o2 o3
00 1 UNALLOCATED-
00 0 0 0 AESE (indexed)FEAT_SVE_AES2
00 0 1 0 AESD (indexed)FEAT_SVE_AES2
00 1 0 0 AESEMCFEAT_SVE_AES2
00 1 1 0 AESDIMCFEAT_SVE_AES2
!= 00 UNALLOCATED-

SVE2 multi-vector AES single round (four registers)

The encodings in this section are decoded from SVE2 Crypto Extensions.

313029282726252423222120191817161514131211109876543210
01000101size1i211op11101o2ZmZdnopc3
Decode fields Instruction Details Feature
size op o2 opc3
00 != 00 UNALLOCATED-
00 0 0 00 AESE (indexed)FEAT_SVE_AES2
00 0 1 00 AESD (indexed)FEAT_SVE_AES2
00 1 0 00 AESEMCFEAT_SVE_AES2
00 1 1 00 AESDIMCFEAT_SVE_AES2
!= 00 UNALLOCATED-

SVE2 crypto constructive binary operations

The encodings in this section are decoded from SVE2 Crypto Extensions.

313029282726252423222120191817161514131211109876543210
01000101size1Zm11110opZnZd
Decode fields Instruction Details Feature
size op
00 0 SM4EKEYFEAT_SVE_SM4
00 1 RAX1FEAT_SVE_SHA3
!= 00 UNALLOCATED-

SVE2 Multi-vector polynomial multiply long

The encodings in this section are decoded from SVE2 Crypto Extensions.

313029282726252423222120191817161514131211109876543210
01000101size1Zm111110ZnZd0
Decode fields Instruction Details Feature
size
00 PMULLFEAT_SVE_AES2
!= 00 UNALLOCATED-

SVE2 Multi-vector polynomial multiply long and accumulate vectors

The encodings in this section are decoded from SVE2 Crypto Extensions.

313029282726252423222120191817161514131211109876543210
01000101size1Zm111111ZnZda0
Decode fields Instruction Details Feature
size
00 PMLALFEAT_SVE_AES2
!= 00 UNALLOCATED-

SVE2 FP8 widening multiply-add

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100op00110op110
Decode fieldsInstruction details
op0op1
0 SVE2 FP8 multiply-add long long
1 0 SVE2 FP8 multiply-add long
1 1 UNALLOCATED

SVE2 FP8 multiply-add long long

The encodings in this section are decoded from SVE2 FP8 widening multiply-add.

313029282726252423222120191817161514131211109876543210
01100100001Zm10TT10ZnZda
Decode fields Instruction Details Feature
TT
00 FMLALLBB (vectors)FEAT_SSVE_FP8FMA || (FEAT_SVE2 && FEAT_FP8FMA)
01 FMLALLBT (vectors)FEAT_SSVE_FP8FMA || (FEAT_SVE2 && FEAT_FP8FMA)
10 FMLALLTB (vectors)FEAT_SSVE_FP8FMA || (FEAT_SVE2 && FEAT_FP8FMA)
11 FMLALLTT (vectors)FEAT_SSVE_FP8FMA || (FEAT_SVE2 && FEAT_FP8FMA)

SVE2 FP8 multiply-add long

The encodings in this section are decoded from SVE2 FP8 widening multiply-add.

313029282726252423222120191817161514131211109876543210
01100100101Zm100T10ZnZda
Decode fields Instruction Details Feature
T
0 FMLALB (vectors, FP8 to FP16)FEAT_SSVE_FP8FMA || (FEAT_SVE2 && FEAT_FP8FMA)
1 FMLALT (vectors, FP8 to FP16)FEAT_SSVE_FP8FMA || (FEAT_SVE2 && FEAT_FP8FMA)

SVE2 floating-point unary operations - zeroing predicated

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100011op01
Decode fieldsInstruction details
op0
00x Floating-point round to integral value (predicated)
010 Floating-point convert (predicated)
011 Floating-point square root (predicated)
10x Floating-point round and convert from integer (predicated)
11x Floating-point log and convert to integer

Floating-point round to integral value (predicated)

The encodings in this section are decoded from SVE2 floating-point unary operations - zeroing predicated.

313029282726252423222120191817161514131211109876543210
01100100size01100op1opc2PgZnZd
Decode fields Instruction Details Feature
op opc2
0 00 FRINT<r> — Nearest with ties to even, zeroingFEAT_SVE2p2 || FEAT_SME2p2
0 01 FRINT<r> — Toward plus infinity, zeroingFEAT_SVE2p2 || FEAT_SME2p2
0 10 FRINT<r> — Toward minus infinity, zeroingFEAT_SVE2p2 || FEAT_SME2p2
0 11 FRINT<r> — Toward zero, zeroingFEAT_SVE2p2 || FEAT_SME2p2
1 00 FRINT<r> — Nearest with ties to away, zeroingFEAT_SVE2p2 || FEAT_SME2p2
1 01 UNALLOCATED-
1 10 FRINT<r> — Current mode signalling inexact, zeroingFEAT_SVE2p2 || FEAT_SME2p2
1 11 FRINT<r> — Current mode, zeroingFEAT_SVE2p2 || FEAT_SME2p2

Floating-point convert (predicated)

The encodings in this section are decoded from SVE2 floating-point unary operations - zeroing predicated.

313029282726252423222120191817161514131211109876543210
01100100opc0110101opc2PgZnZd
Decode fields Instruction Details Feature
opc opc2
x0 11 UNALLOCATED-
00 0x UNALLOCATED-
00 10 FCVTXFEAT_SVE2p2 || FEAT_SME2p2
01 UNALLOCATED-
10 00 FCVT — Single-precision to half-precision, zeroingFEAT_SVE2p2 || FEAT_SME2p2
10 01 FCVT — Half-precision to single-precision, zeroingFEAT_SVE2p2 || FEAT_SME2p2
10 10 BFCVTFEAT_SVE2p2 || FEAT_SME2p2
11 00 FCVT — Double-precision to half-precision, zeroingFEAT_SVE2p2 || FEAT_SME2p2
11 01 FCVT — Half-precision to double-precision, zeroingFEAT_SVE2p2 || FEAT_SME2p2
11 10 FCVT — Double-precision to single-precision, zeroingFEAT_SVE2p2 || FEAT_SME2p2
11 11 FCVT — Single-precision to double-precision, zeroingFEAT_SVE2p2 || FEAT_SME2p2

Floating-point square root (predicated)

The encodings in this section are decoded from SVE2 floating-point unary operations - zeroing predicated.

313029282726252423222120191817161514131211109876543210
01100100size0110111opcPgZnZd
Decode fields Instruction Details Feature
opc
00 FRECPXFEAT_SVE2p2 || FEAT_SME2p2
01 FSQRTFEAT_SVE2p2 || FEAT_SME2p2
1x UNALLOCATED-

Floating-point round and convert from integer (predicated)

The encodings in this section are decoded from SVE2 floating-point unary operations - zeroing predicated.

313029282726252423222120191817161514131211109876543210
01100100opc01110o21o3UPgZnZd
Decode fields Instruction Details Feature
opc o2 o3 U
00 0 0 FRINT32ZFEAT_SVE2p2 || FEAT_SME2p2
00 0 1 FRINT32XFEAT_SVE2p2 || FEAT_SME2p2
00 1 0 FRINT64ZFEAT_SVE2p2 || FEAT_SME2p2
00 1 1 FRINT64XFEAT_SVE2p2 || FEAT_SME2p2
01 0 0 UNALLOCATED-
01 0 1 0 SCVTF — 16-bit to half-precision, zeroingFEAT_SVE2p2 || FEAT_SME2p2
01 0 1 1 UCVTF — 16-bit to half-precision, zeroingFEAT_SVE2p2 || FEAT_SME2p2
01 1 0 0 SCVTF — 32-bit to half-precision, zeroingFEAT_SVE2p2 || FEAT_SME2p2
01 1 0 1 UCVTF — 32-bit to half-precision, zeroingFEAT_SVE2p2 || FEAT_SME2p2
01 1 1 0 SCVTF — 64-bit to half-precision, zeroingFEAT_SVE2p2 || FEAT_SME2p2
01 1 1 1 UCVTF — 64-bit to half-precision, zeroingFEAT_SVE2p2 || FEAT_SME2p2
10 0 UNALLOCATED-
10 1 0 0 SCVTF — 32-bit to single-precision, zeroingFEAT_SVE2p2 || FEAT_SME2p2
10 1 0 1 UCVTF — 32-bit to single-precision, zeroingFEAT_SVE2p2 || FEAT_SME2p2
10 1 1 UNALLOCATED-
11 0 0 0 SCVTF — 32-bit to double-precision, zeroingFEAT_SVE2p2 || FEAT_SME2p2
11 0 0 1 UCVTF — 32-bit to double-precision, zeroingFEAT_SVE2p2 || FEAT_SME2p2
11 0 1 UNALLOCATED-
11 1 0 0 SCVTF — 64-bit to single-precision, zeroingFEAT_SVE2p2 || FEAT_SME2p2
11 1 0 1 UCVTF — 64-bit to single-precision, zeroingFEAT_SVE2p2 || FEAT_SME2p2
11 1 1 0 SCVTF — 64-bit to double-precision, zeroingFEAT_SVE2p2 || FEAT_SME2p2
11 1 1 1 UCVTF — 64-bit to double-precision, zeroingFEAT_SVE2p2 || FEAT_SME2p2

Floating-point log and convert to integer

The encodings in this section are decoded from SVE2 floating-point unary operations - zeroing predicated.

313029282726252423222120191817161514131211109876543210
01100100opc01111o21o3UPgZnZd
Decode fields Instruction Details Feature
opc o2 o3 U
00 0 FLOGBFEAT_SVE2p2 || FEAT_SME2p2
00 1 UNALLOCATED-
01 0 0 UNALLOCATED-
01 0 1 0 FCVTZS — Half-precision to 16-bit, zeroingFEAT_SVE2p2 || FEAT_SME2p2
01 0 1 1 FCVTZU — Half-precision to 16-bit, zeroingFEAT_SVE2p2 || FEAT_SME2p2
01 1 0 0 FCVTZS — Half-precision to 32-bit, zeroingFEAT_SVE2p2 || FEAT_SME2p2
01 1 0 1 FCVTZU — Half-precision to 32-bit, zeroingFEAT_SVE2p2 || FEAT_SME2p2
01 1 1 0 FCVTZS — Half-precision to 64-bit, zeroingFEAT_SVE2p2 || FEAT_SME2p2
01 1 1 1 FCVTZU — Half-precision to 64-bit, zeroingFEAT_SVE2p2 || FEAT_SME2p2
10 0 UNALLOCATED-
10 1 0 0 FCVTZS — Single-precision to 32-bit, zeroingFEAT_SVE2p2 || FEAT_SME2p2
10 1 0 1 FCVTZU — Single-precision to 32-bit, zeroingFEAT_SVE2p2 || FEAT_SME2p2
10 1 1 UNALLOCATED-
11 0 0 0 FCVTZS — Double-precision to 32-bit, zeroingFEAT_SVE2p2 || FEAT_SME2p2
11 0 0 1 FCVTZU — Double-precision to 32-bit, zeroingFEAT_SVE2p2 || FEAT_SME2p2
11 0 1 UNALLOCATED-
11 1 0 0 FCVTZS — Single-precision to 64-bit, zeroingFEAT_SVE2p2 || FEAT_SME2p2
11 1 0 1 FCVTZU — Single-precision to 64-bit, zeroingFEAT_SVE2p2 || FEAT_SME2p2
11 1 1 0 FCVTZS — Double-precision to 64-bit, zeroingFEAT_SVE2p2 || FEAT_SME2p2
11 1 1 1 FCVTZU — Double-precision to 64-bit, zeroingFEAT_SVE2p2 || FEAT_SME2p2

SVE floating-point widening multiply-add - indexed

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100op0101op10
Decode fieldsInstruction details
op0op1
0 0 SVE BFloat16 floating-point dot product (indexed)
0 1 UNALLOCATED
1 SVE floating-point multiply-add long (indexed)

SVE BFloat16 floating-point dot product (indexed)

The encodings in this section are decoded from SVE floating-point widening multiply-add - indexed.

313029282726252423222120191817161514131211109876543210
011001000op1i2Zm0100opc2ZnZda
Decode fields Instruction Details Feature
op opc2
0 x1 FDOT (2-way, indexed, FP8 to FP16)FEAT_SSVE_FP8DOT2 || (FEAT_SVE2 && FEAT_FP8DOT2)
0 00 FDOT (2-way, indexed, FP16 to FP32)FEAT_SME2 || FEAT_SVE2p1
0 10 UNALLOCATED-
1 00 BFDOT (indexed)(FEAT_SVE && FEAT_BF16) || (FEAT_SME && FEAT_BF16)
1 01 FDOT (4-way, indexed)FEAT_SSVE_FP8DOT4 || (FEAT_SVE2 && FEAT_FP8DOT4)
1 1x UNALLOCATED-

SVE floating-point multiply-add long (indexed)

The encodings in this section are decoded from SVE floating-point widening multiply-add - indexed.

313029282726252423222120191817161514131211109876543210
011001001o21i3hZm01op0i3lTZnZda
Decode fields Instruction Details Feature
o2 op T
0 0 0 FMLALB (indexed, FP16 to FP32)FEAT_SVE2 || FEAT_SME
0 0 1 FMLALT (indexed, FP16 to FP32)FEAT_SVE2 || FEAT_SME
0 1 0 FMLSLB (indexed)FEAT_SVE2 || FEAT_SME
0 1 1 FMLSLT (indexed)FEAT_SVE2 || FEAT_SME
1 0 0 BFMLALB (indexed)(FEAT_SVE && FEAT_BF16) || (FEAT_SME && FEAT_BF16)
1 0 1 BFMLALT (indexed)(FEAT_SVE && FEAT_BF16) || (FEAT_SME && FEAT_BF16)
1 1 0 BFMLSLB (indexed)FEAT_SME2 || FEAT_SVE2p1
1 1 1 BFMLSLT (indexed)FEAT_SME2 || FEAT_SVE2p1

SVE floating-point widening multiply-add

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100op0110op100
Decode fieldsInstruction details
op0op1
0 0 SVE BFloat16 floating-point dot product
0 1 UNALLOCATED
1 SVE floating-point multiply-add long

SVE BFloat16 floating-point dot product

The encodings in this section are decoded from SVE floating-point widening multiply-add.

313029282726252423222120191817161514131211109876543210
011001000op1Zm10000o2ZnZda
Decode fields Instruction Details Feature
op o2
0 0 FDOT (2-way, vectors, FP16 to FP32)FEAT_SME2 || FEAT_SVE2p1
0 1 FDOT (2-way, vectors, FP8 to FP16)FEAT_SSVE_FP8DOT2 || (FEAT_SVE2 && FEAT_FP8DOT2)
1 0 BFDOT (vectors)(FEAT_SVE && FEAT_BF16) || (FEAT_SME && FEAT_BF16)
1 1 FDOT (4-way, vectors)FEAT_SSVE_FP8DOT4 || (FEAT_SVE2 && FEAT_FP8DOT4)

SVE floating-point multiply-add long

The encodings in this section are decoded from SVE floating-point widening multiply-add.

313029282726252423222120191817161514131211109876543210
011001001o21Zm10op00TZnZda
Decode fields Instruction Details Feature
o2 op T
0 0 0 FMLALB (vectors, FP16 to FP32)FEAT_SVE2 || FEAT_SME
0 0 1 FMLALT (vectors, FP16 to FP32)FEAT_SVE2 || FEAT_SME
0 1 0 FMLSLB (vectors)FEAT_SVE2 || FEAT_SME
0 1 1 FMLSLT (vectors)FEAT_SVE2 || FEAT_SME
1 0 0 BFMLALB (vectors)(FEAT_SVE && FEAT_BF16) || (FEAT_SME && FEAT_BF16)
1 0 1 BFMLALT (vectors)(FEAT_SVE && FEAT_BF16) || (FEAT_SME && FEAT_BF16)
1 1 0 BFMLSLB (vectors)FEAT_SME2 || FEAT_SVE2p1
1 1 1 BFMLSLT (vectors)FEAT_SME2 || FEAT_SVE2p1

SVE floating-point unary operations - unpredicated

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01100101op0001op10011op2op3
Decode fieldsInstruction details
op0op1op2op3
00 00x SVE2 FP8 upconverts
00 010 0 SVE2 FP8 downconverts
00 010 1 UNALLOCATED
00 011 UNALLOCATED
10x UNALLOCATED
11x 00 SVE floating-point reciprocal estimate (unpredicated)
11x != 00 UNALLOCATED
!= 00 0xx UNALLOCATED

SVE2 FP8 upconverts

The encodings in this section are decoded from SVE floating-point unary operations - unpredicated.

313029282726252423222120191817161514131211109876543210
011001010000100L0011opcZnZd
Decode fields Instruction Details Feature
L opc
0 00 F1CVT, F2CVT — F1CVT(FEAT_SVE2 && FEAT_FP8) || (FEAT_SME2 && FEAT_FP8)
0 01 F1CVT, F2CVT — F2CVT(FEAT_SVE2 && FEAT_FP8) || (FEAT_SME2 && FEAT_FP8)
0 10 BF1CVT, BF2CVT — BF1CVT(FEAT_SVE2 && FEAT_FP8) || (FEAT_SME2 && FEAT_FP8)
0 11 BF1CVT, BF2CVT — BF2CVT(FEAT_SVE2 && FEAT_FP8) || (FEAT_SME2 && FEAT_FP8)
1 00 F1CVTLT, F2CVTLT — F1CVTLT(FEAT_SVE2 && FEAT_FP8) || (FEAT_SME2 && FEAT_FP8)
1 01 F1CVTLT, F2CVTLT — F2CVTLT(FEAT_SVE2 && FEAT_FP8) || (FEAT_SME2 && FEAT_FP8)
1 10 BF1CVTLT, BF2CVTLT — BF1CVTLT(FEAT_SVE2 && FEAT_FP8) || (FEAT_SME2 && FEAT_FP8)
1 11 BF1CVTLT, BF2CVTLT — BF2CVTLT(FEAT_SVE2 && FEAT_FP8) || (FEAT_SME2 && FEAT_FP8)

SVE2 FP8 downconverts

The encodings in this section are decoded from SVE floating-point unary operations - unpredicated.

313029282726252423222120191817161514131211109876543210
01100101000010100011opcZn0Zd
Decode fields Instruction Details Feature
opc
00 FCVTN(FEAT_SVE2 && FEAT_FP8) || (FEAT_SME2 && FEAT_FP8)
01 FCVTNB(FEAT_SVE2 && FEAT_FP8) || (FEAT_SME2 && FEAT_FP8)
10 BFCVTN(FEAT_SVE2 && FEAT_FP8) || (FEAT_SME2 && FEAT_FP8)
11 FCVTNT (unpredicated)(FEAT_SVE2 && FEAT_FP8) || (FEAT_SME2 && FEAT_FP8)

SVE floating-point reciprocal estimate (unpredicated)

The encodings in this section are decoded from SVE floating-point unary operations - unpredicated.

313029282726252423222120191817161514131211109876543210
01100101size00111op001100ZnZd
Decode fields Instruction Details Feature
op
0 FRECPEFEAT_SVE || FEAT_SME
1 FRSQRTEFEAT_SVE || FEAT_SME

SVE floating-point compare - with zero

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01100101010op0001
Decode fieldsInstruction details
op0
0 SVE floating-point compare with zero
1 UNALLOCATED

SVE floating-point compare with zero

The encodings in this section are decoded from SVE floating-point compare - with zero.

313029282726252423222120191817161514131211109876543210
01100101size0100eqlt001PgZnnePd
Decode fields Instruction Details Feature
eq lt ne
0 0 0 FCM<cc> (zero) — Greater than or equalFEAT_SVE || FEAT_SME
0 0 1 FCM<cc> (zero) — Greater thanFEAT_SVE || FEAT_SME
0 1 0 FCM<cc> (zero) — Less thanFEAT_SVE || FEAT_SME
0 1 1 FCM<cc> (zero) — Less than or equalFEAT_SVE || FEAT_SME
1 1 UNALLOCATED-
1 0 0 FCM<cc> (zero) — EqualFEAT_SVE || FEAT_SME
1 1 0 FCM<cc> (zero) — Not equalFEAT_SVE || FEAT_SME

SVE floating-point accumulating reduction

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01100101011op0001
Decode fieldsInstruction details
op0
0 SVE floating-point serial reduction (predicated)
1 UNALLOCATED

SVE floating-point serial reduction (predicated)

The encodings in this section are decoded from SVE floating-point accumulating reduction.

313029282726252423222120191817161514131211109876543210
01100101size0110opc001PgZmVdn
Decode fields Instruction Details Feature
opc
00 FADDAFEAT_SVE
!= 00 UNALLOCATED-

SVE floating-point arithmetic - predicated

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
011001010op0100op1op2
Decode fieldsInstruction detailsFeature
op0op1op2
0x SVE floating-point arithmetic (predicated)-
10 000 FTMADFEAT_SVE
10 != 000 UNALLOCATED-
11 0000 SVE floating-point arithmetic with immediate (predicated)-
11 != 0000 UNALLOCATED-

SVE floating-point arithmetic (predicated)

The encodings in this section are decoded from SVE floating-point arithmetic - predicated.

313029282726252423222120191817161514131211109876543210
01100101size00opc100PgZmZdn
Decode fields Instruction Details Feature
size opc
0011 FSUBR (vectors)FEAT_SVE || FEAT_SME
1000 FABDFEAT_SVE || FEAT_SME
1010 FMULXFEAT_SVE || FEAT_SME
1011 UNALLOCATED-
1100 FDIVRFEAT_SVE || FEAT_SME
1101 FDIVFEAT_SVE || FEAT_SME
1110 FAMAX(FEAT_SVE2 && FEAT_FAMINMAX) || (FEAT_SME2 && FEAT_FAMINMAX)
1111 FAMIN(FEAT_SVE2 && FEAT_FAMINMAX) || (FEAT_SME2 && FEAT_FAMINMAX)
00 0000 BFADD (predicated)FEAT_SVE_B16B16
00 0001 BFSUB (predicated)FEAT_SVE_B16B16
00 0010 BFMUL (vectors, predicated)FEAT_SVE_B16B16
00 0100 BFMAXNMFEAT_SVE_B16B16
00 0101 BFMINNMFEAT_SVE_B16B16
00 0110 BFMAXFEAT_SVE_B16B16
00 0111 BFMINFEAT_SVE_B16B16
00 1001 BFSCALEFEAT_SVE_BFSCALE
!= 00 0000 FADD (vectors, predicated)FEAT_SVE || FEAT_SME
!= 00 0001 FSUB (vectors, predicated)FEAT_SVE || FEAT_SME
!= 00 0010 FMUL (vectors, predicated)FEAT_SVE || FEAT_SME
!= 00 0100 FMAXNM (vectors)FEAT_SVE || FEAT_SME
!= 00 0101 FMINNM (vectors)FEAT_SVE || FEAT_SME
!= 00 0110 FMAX (vectors)FEAT_SVE || FEAT_SME
!= 00 0111 FMIN (vectors)FEAT_SVE || FEAT_SME
!= 00 1001 FSCALEFEAT_SVE || FEAT_SME

SVE floating-point arithmetic with immediate (predicated)

The encodings in this section are decoded from SVE floating-point arithmetic - predicated.

313029282726252423222120191817161514131211109876543210
01100101size011opc100Pg0000i1Zdn
Decode fields Instruction Details Feature
opc
000 FADD (immediate)FEAT_SVE || FEAT_SME
001 FSUB (immediate)FEAT_SVE || FEAT_SME
010 FMUL (immediate)FEAT_SVE || FEAT_SME
011 FSUBR (immediate)FEAT_SVE || FEAT_SME
100 FMAXNM (immediate)FEAT_SVE || FEAT_SME
101 FMINNM (immediate)FEAT_SVE || FEAT_SME
110 FMAX (immediate)FEAT_SVE || FEAT_SME
111 FMIN (immediate)FEAT_SVE || FEAT_SME

SVE floating-point unary operations - merging predicated

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
011001010op0101
Decode fieldsInstruction details
op0
00x SVE floating-point round to integral value
010 SVE floating-point convert precision
011 SVE floating-point unary operations
10x SVE integer convert to floating-point
11x SVE floating-point convert to integer

SVE floating-point round to integral value

The encodings in this section are decoded from SVE floating-point unary operations - merging predicated.

313029282726252423222120191817161514131211109876543210
01100101size000opc101PgZnZd
Decode fields Instruction Details Feature
opc
000 FRINT<r> — Nearest with ties to even, mergingFEAT_SVE || FEAT_SME
001 FRINT<r> — Toward plus infinity, mergingFEAT_SVE || FEAT_SME
010 FRINT<r> — Toward minus infinity, mergingFEAT_SVE || FEAT_SME
011 FRINT<r> — Toward zero, mergingFEAT_SVE || FEAT_SME
100 FRINT<r> — Nearest with ties to away, mergingFEAT_SVE || FEAT_SME
101 UNALLOCATED-
110 FRINT<r> — Current mode signalling inexact, mergingFEAT_SVE || FEAT_SME
111 FRINT<r> — Current mode, mergingFEAT_SVE || FEAT_SME

SVE floating-point convert precision

The encodings in this section are decoded from SVE floating-point unary operations - merging predicated.

313029282726252423222120191817161514131211109876543210
01100101opc0010opc2101PgZnZd
Decode fields Instruction Details Feature
opc opc2
x0 11 UNALLOCATED-
00 0x UNALLOCATED-
00 10 FCVTXFEAT_SVE2 || FEAT_SME
01 UNALLOCATED-
10 00 FCVT — Single-precision to half-precision, mergingFEAT_SVE || FEAT_SME
10 01 FCVT — Half-precision to single-precision, mergingFEAT_SVE || FEAT_SME
10 10 BFCVT(FEAT_SVE && FEAT_BF16) || (FEAT_SME && FEAT_BF16)
11 00 FCVT — Double-precision to half-precision, mergingFEAT_SVE || FEAT_SME
11 01 FCVT — Half-precision to double-precision, mergingFEAT_SVE || FEAT_SME
11 10 FCVT — Double-precision to single-precision, mergingFEAT_SVE || FEAT_SME
11 11 FCVT — Single-precision to double-precision, mergingFEAT_SVE || FEAT_SME

SVE floating-point unary operations

The encodings in this section are decoded from SVE floating-point unary operations - merging predicated.

313029282726252423222120191817161514131211109876543210
01100101size0011opc101PgZnZd
Decode fields Instruction Details Feature
opc
00 FRECPXFEAT_SVE || FEAT_SME
01 FSQRTFEAT_SVE || FEAT_SME
1x UNALLOCATED-

SVE integer convert to floating-point

The encodings in this section are decoded from SVE floating-point unary operations - merging predicated.

313029282726252423222120191817161514131211109876543210
01100101opc010opc2U101PgZnZd
Decode fields Instruction Details Feature
opc opc2 U
00 0x 0 FRINT32ZFEAT_SVE2p2 || FEAT_SME2p2
00 0x 1 FRINT32XFEAT_SVE2p2 || FEAT_SME2p2
00 1x 0 FRINT64ZFEAT_SVE2p2 || FEAT_SME2p2
00 1x 1 FRINT64XFEAT_SVE2p2 || FEAT_SME2p2
01 00 UNALLOCATED-
01 01 0 SCVTF — 16-bit to half-precision, mergingFEAT_SVE || FEAT_SME
01 01 1 UCVTF — 16-bit to half-precision, mergingFEAT_SVE || FEAT_SME
01 10 0 SCVTF — 32-bit to half-precision, mergingFEAT_SVE || FEAT_SME
01 10 1 UCVTF — 32-bit to half-precision, mergingFEAT_SVE || FEAT_SME
01 11 0 SCVTF — 64-bit to half-precision, mergingFEAT_SVE || FEAT_SME
01 11 1 UCVTF — 64-bit to half-precision, mergingFEAT_SVE || FEAT_SME
10 10 0 SCVTF — 32-bit to single-precision, mergingFEAT_SVE || FEAT_SME
10 10 1 UCVTF — 32-bit to single-precision, mergingFEAT_SVE || FEAT_SME
10 != 10 UNALLOCATED-
11 00 0 SCVTF — 32-bit to double-precision, mergingFEAT_SVE || FEAT_SME
11 00 1 UCVTF — 32-bit to double-precision, mergingFEAT_SVE || FEAT_SME
11 01 UNALLOCATED-
11 10 0 SCVTF — 64-bit to single-precision, mergingFEAT_SVE || FEAT_SME
11 10 1 UCVTF — 64-bit to single-precision, mergingFEAT_SVE || FEAT_SME
11 11 0 SCVTF — 64-bit to double-precision, mergingFEAT_SVE || FEAT_SME
11 11 1 UCVTF — 64-bit to double-precision, mergingFEAT_SVE || FEAT_SME

SVE floating-point convert to integer

The encodings in this section are decoded from SVE floating-point unary operations - merging predicated.

313029282726252423222120191817161514131211109876543210
01100101opc011opc2U101PgZnZd
Decode fields Instruction Details Feature
opc opc2 U
00 0 FLOGBFEAT_SVE2 || FEAT_SME
00 1 UNALLOCATED-
01 00 UNALLOCATED-
01 01 0 FCVTZS — Half-precision to 16-bit, mergingFEAT_SVE || FEAT_SME
01 01 1 FCVTZU — Half-precision to 16-bit, mergingFEAT_SVE || FEAT_SME
01 10 0 FCVTZS — Half-precision to 32-bit, mergingFEAT_SVE || FEAT_SME
01 10 1 FCVTZU — Half-precision to 32-bit, mergingFEAT_SVE || FEAT_SME
01 11 0 FCVTZS — Half-precision to 64-bit, mergingFEAT_SVE || FEAT_SME
01 11 1 FCVTZU — Half-precision to 64-bit, mergingFEAT_SVE || FEAT_SME
10 10 0 FCVTZS — Single-precision to 32-bit, mergingFEAT_SVE || FEAT_SME
10 10 1 FCVTZU — Single-precision to 32-bit, mergingFEAT_SVE || FEAT_SME
10 != 10 UNALLOCATED-
11 00 0 FCVTZS — Double-precision to 32-bit, mergingFEAT_SVE || FEAT_SME
11 00 1 FCVTZU — Double-precision to 32-bit, mergingFEAT_SVE || FEAT_SME
11 01 UNALLOCATED-
11 10 0 FCVTZS — Single-precision to 64-bit, mergingFEAT_SVE || FEAT_SME
11 10 1 FCVTZU — Single-precision to 64-bit, mergingFEAT_SVE || FEAT_SME
11 11 0 FCVTZS — Double-precision to 64-bit, mergingFEAT_SVE || FEAT_SME
11 11 1 FCVTZU — Double-precision to 64-bit, mergingFEAT_SVE || FEAT_SME

SVE floating-point multiply-add

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
011001011op0
Decode fieldsInstruction details
op0
0 SVE floating-point multiply-accumulate writing addend
1 SVE floating-point multiply-accumulate writing multiplicand

SVE floating-point multiply-accumulate writing addend

The encodings in this section are decoded from SVE floating-point multiply-add.

313029282726252423222120191817161514131211109876543210
01100101size1Zm0opcPgZnZda
Decode fields Instruction Details Feature
size opc
00 00 BFMLA (vectors)FEAT_SVE_B16B16
00 01 BFMLS (vectors)FEAT_SVE_B16B16
00 1x UNALLOCATED-
!= 00 00 FMLA (vectors)FEAT_SVE || FEAT_SME
!= 00 01 FMLS (vectors)FEAT_SVE || FEAT_SME
!= 00 10 FNMLAFEAT_SVE || FEAT_SME
!= 00 11 FNMLSFEAT_SVE || FEAT_SME

SVE floating-point multiply-accumulate writing multiplicand

The encodings in this section are decoded from SVE floating-point multiply-add.

313029282726252423222120191817161514131211109876543210
01100101size1Za1opcPgZmZdn
Decode fields Instruction Details Feature
opc
00 FMADFEAT_SVE || FEAT_SME
01 FMSBFEAT_SVE || FEAT_SME
10 FNMADFEAT_SVE || FEAT_SME
11 FNMSBFEAT_SVE || FEAT_SME

SVE Memory - 32-bit Gather and Unsized Contiguous

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
1000010op0op1op2op3
Decode fieldsInstruction detailsFeature
op0op1op2op3
00 x1 0xx 0 SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)-
00 x1 0xx 1 UNALLOCATED-
01 x1 0xx SVE 32-bit gather load halfwords (scalar plus 32-bit scaled offsets)-
10 x1 0xx SVE 32-bit gather load words (scalar plus 32-bit scaled offsets)-
11 0x 000 0 LDR (predicate)FEAT_SVE || FEAT_SME
11 0x 000 1 UNALLOCATED-
11 0x 010 LDR (vector)FEAT_SVE || FEAT_SME
11 0x 0x1 UNALLOCATED-
11 1x 0xx 0 SVE contiguous prefetch (scalar plus immediate)-
11 1x 0xx 1 UNALLOCATED-
00 10x SVE2 32-bit gather non-temporal load (vector plus scalar)-
00 110 0 SVE contiguous prefetch (scalar plus scalar)-
00 111 0 SVE 32-bit gather prefetch (vector plus immediate)-
00 11x 1 UNALLOCATED-
01 1xx SVE 32-bit gather load (vector plus immediate)-
1x 1xx SVE load and broadcast element-
!= 11 x0 0xx SVE 32-bit gather load (scalar plus 32-bit unscaled offsets)-

SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)

The encodings in this section are decoded from SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
100001000xs1Zm0mszPgRn0prfop
Decode fields Instruction Details Feature
msz
00 PRFB (scalar plus vector)FEAT_SVE
01 PRFH (scalar plus vector)FEAT_SVE
10 PRFW (scalar plus vector)FEAT_SVE
11 PRFD (scalar plus vector)FEAT_SVE

SVE 32-bit gather load halfwords (scalar plus 32-bit scaled offsets)

The encodings in this section are decoded from SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
100001001xs1Zm0UffPgRnZt
Decode fields Instruction Details Feature
U ff
0 0 LD1SH (scalar plus vector)FEAT_SVE
0 1 LDFF1SH (scalar plus vector)FEAT_SVE
1 0 LD1H (scalar plus vector)FEAT_SVE
1 1 LDFF1H (scalar plus vector)FEAT_SVE

SVE 32-bit gather load words (scalar plus 32-bit scaled offsets)

The encodings in this section are decoded from SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
100001010xs1Zm0UffPgRnZt
Decode fields Instruction Details Feature
U ff
0 UNALLOCATED-
1 0 LD1W (scalar plus vector)FEAT_SVE
1 1 LDFF1W (scalar plus vector)FEAT_SVE

SVE contiguous prefetch (scalar plus immediate)

The encodings in this section are decoded from SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1000010111imm60mszPgRn0prfop
Decode fields Instruction Details Feature
msz
00 PRFB (scalar plus immediate)FEAT_SVE || FEAT_SME
01 PRFH (scalar plus immediate)FEAT_SVE || FEAT_SME
10 PRFW (scalar plus immediate)FEAT_SVE || FEAT_SME
11 PRFD (scalar plus immediate)FEAT_SVE || FEAT_SME

SVE2 32-bit gather non-temporal load (vector plus scalar)

The encodings in this section are decoded from SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1000010msz00Rm10UPgZnZt
Decode fields Instruction Details Feature
msz U
00 0 LDNT1SBFEAT_SVE2
00 1 LDNT1B (vector plus scalar)FEAT_SVE2
01 0 LDNT1SHFEAT_SVE2
01 1 LDNT1H (vector plus scalar)FEAT_SVE2
10 0 UNALLOCATED-
10 1 LDNT1W (vector plus scalar)FEAT_SVE2
11 UNALLOCATED-

SVE contiguous prefetch (scalar plus scalar)

The encodings in this section are decoded from SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1000010msz00Rm110PgRn0prfop
Decode fields Instruction Details Feature
msz Rm
11111 UNALLOCATED-
00 != 11111 PRFB (scalar plus scalar)FEAT_SVE || FEAT_SME
01 != 11111 PRFH (scalar plus scalar)FEAT_SVE || FEAT_SME
10 != 11111 PRFW (scalar plus scalar)FEAT_SVE || FEAT_SME
11 != 11111 PRFD (scalar plus scalar)FEAT_SVE || FEAT_SME

SVE 32-bit gather prefetch (vector plus immediate)

The encodings in this section are decoded from SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1000010msz00imm5111PgZn0prfop
Decode fields Instruction Details Feature
msz
00 PRFB (vector plus immediate)FEAT_SVE
01 PRFH (vector plus immediate)FEAT_SVE
10 PRFW (vector plus immediate)FEAT_SVE
11 PRFD (vector plus immediate)FEAT_SVE

SVE 32-bit gather load (vector plus immediate)

The encodings in this section are decoded from SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1000010msz01imm51UffPgZnZt
Decode fields Instruction Details Feature
msz U ff
00 0 0 LD1SB (vector plus immediate)FEAT_SVE
00 0 1 LDFF1SB (vector plus immediate)FEAT_SVE
00 1 0 LD1B (vector plus immediate)FEAT_SVE
00 1 1 LDFF1B (vector plus immediate)FEAT_SVE
01 0 0 LD1SH (vector plus immediate)FEAT_SVE
01 0 1 LDFF1SH (vector plus immediate)FEAT_SVE
01 1 0 LD1H (vector plus immediate)FEAT_SVE
01 1 1 LDFF1H (vector plus immediate)FEAT_SVE
10 0 UNALLOCATED-
10 1 0 LD1W (vector plus immediate)FEAT_SVE
10 1 1 LDFF1W (vector plus immediate)FEAT_SVE
11 UNALLOCATED-

SVE load and broadcast element

The encodings in this section are decoded from SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1000010dtypeh1imm61dtypelPgRnZt
Decode fields Instruction Details Feature
dtypeh dtypel
00 00 LD1RB — 8-bit elementFEAT_SVE || FEAT_SME
00 01 LD1RB — 16-bit elementFEAT_SVE || FEAT_SME
00 10 LD1RB — 32-bit elementFEAT_SVE || FEAT_SME
00 11 LD1RB — 64-bit elementFEAT_SVE || FEAT_SME
01 00 LD1RSWFEAT_SVE || FEAT_SME
01 01 LD1RH — 16-bit elementFEAT_SVE || FEAT_SME
01 10 LD1RH — 32-bit elementFEAT_SVE || FEAT_SME
01 11 LD1RH — 64-bit elementFEAT_SVE || FEAT_SME
10 00 LD1RSH — 64-bit elementFEAT_SVE || FEAT_SME
10 01 LD1RSH — 32-bit elementFEAT_SVE || FEAT_SME
10 10 LD1RW — 32-bit elementFEAT_SVE || FEAT_SME
10 11 LD1RW — 64-bit elementFEAT_SVE || FEAT_SME
11 00 LD1RSB — 64-bit elementFEAT_SVE || FEAT_SME
11 01 LD1RSB — 32-bit elementFEAT_SVE || FEAT_SME
11 10 LD1RSB — 16-bit elementFEAT_SVE || FEAT_SME
11 11 LD1RDFEAT_SVE || FEAT_SME

SVE 32-bit gather load (scalar plus 32-bit unscaled offsets)

The encodings in this section are decoded from SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1000010!= 11xs0Zm0UffPgRnZt
opc

The following constraints also apply to this encoding: opc != '11'

Decode fields Instruction Details Feature
opc U ff
00 0 0 LD1SB (scalar plus vector)FEAT_SVE
00 0 1 LDFF1SB (scalar plus vector)FEAT_SVE
00 1 0 LD1B (scalar plus vector)FEAT_SVE
00 1 1 LDFF1B (scalar plus vector)FEAT_SVE
01 0 0 LD1SH (scalar plus vector)FEAT_SVE
01 0 1 LDFF1SH (scalar plus vector)FEAT_SVE
01 1 0 LD1H (scalar plus vector)FEAT_SVE
01 1 1 LDFF1H (scalar plus vector)FEAT_SVE
10 0 UNALLOCATED-
10 1 0 LD1W (scalar plus vector)FEAT_SVE
10 1 1 LDFF1W (scalar plus vector)FEAT_SVE

SVE Memory - Contiguous Load

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
1010010op0op1op2
Decode fieldsInstruction details
op0op1op2
00 0 111 SVE contiguous non-temporal load (scalar plus immediate)
00 1 001 SVE contiguous load (quadwords, scalar plus immediate)
00 1 111 SVE load multiple structures (quadwords, scalar plus immediate)
00 100 SVE contiguous load (quadwords, scalar plus scalar)
00 110 SVE contiguous non-temporal load (scalar plus scalar)
01 100 SVE load multiple structures (quadwords, scalar plus scalar)
1x 100 UNALLOCATED
0 001 SVE load and broadcast quadword (scalar plus immediate)
0 101 SVE contiguous load (scalar plus immediate)
1 101 SVE contiguous non-fault load (scalar plus immediate)
000 SVE load and broadcast quadword (scalar plus scalar)
010 SVE contiguous load (scalar plus scalar)
011 SVE contiguous first-fault load (scalar plus scalar)
!= 00 0 111 SVE load multiple structures (scalar plus immediate)
!= 00 1 001 UNALLOCATED
!= 00 1 111 UNALLOCATED
!= 00 110 SVE load multiple structures (scalar plus scalar)

SVE contiguous non-temporal load (scalar plus immediate)

The encodings in this section are decoded from SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010msz000imm4111PgRnZt
Decode fields Instruction Details Feature
msz
00 LDNT1B (scalar plus immediate, single register)FEAT_SVE || FEAT_SME
01 LDNT1H (scalar plus immediate, single register)FEAT_SVE || FEAT_SME
10 LDNT1W (scalar plus immediate, single register)FEAT_SVE || FEAT_SME
11 LDNT1D (scalar plus immediate, single register)FEAT_SVE || FEAT_SME

SVE contiguous load (quadwords, scalar plus immediate)

The encodings in this section are decoded from SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010dtype001imm4001PgRnZt
Decode fields Instruction Details Feature
dtype
0x UNALLOCATED-
10 LD1W (scalar plus immediate, single register)FEAT_SVE2p1
11 LD1D (scalar plus immediate, single register)FEAT_SVE2p1

SVE load multiple structures (quadwords, scalar plus immediate)

The encodings in this section are decoded from SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010num001imm4111PgRnZt
Decode fields Instruction Details Feature
num
00 UNALLOCATED-
01 LD2Q (scalar plus immediate)FEAT_SVE2p1 || FEAT_SME2p1
10 LD3Q (scalar plus immediate)FEAT_SVE2p1 || FEAT_SME2p1
11 LD4Q (scalar plus immediate)FEAT_SVE2p1 || FEAT_SME2p1

SVE contiguous load (quadwords, scalar plus scalar)

The encodings in this section are decoded from SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010dtype00Rm100PgRnZt
Decode fields Instruction Details Feature
dtype Rm
0x UNALLOCATED-
1x 11111 UNALLOCATED-
10 != 11111 LD1W (scalar plus scalar, single register)FEAT_SVE2p1
11 != 11111 LD1D (scalar plus scalar, single register)FEAT_SVE2p1

SVE contiguous non-temporal load (scalar plus scalar)

The encodings in this section are decoded from SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010msz00Rm110PgRnZt
Decode fields Instruction Details Feature
msz Rm
11111 UNALLOCATED-
00 != 11111 LDNT1B (scalar plus scalar, single register)FEAT_SVE || FEAT_SME
01 != 11111 LDNT1H (scalar plus scalar, single register)FEAT_SVE || FEAT_SME
10 != 11111 LDNT1W (scalar plus scalar, single register)FEAT_SVE || FEAT_SME
11 != 11111 LDNT1D (scalar plus scalar, single register)FEAT_SVE || FEAT_SME

SVE load multiple structures (quadwords, scalar plus scalar)

The encodings in this section are decoded from SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010num01Rm100PgRnZt
Decode fields Instruction Details Feature
num Rm
00 UNALLOCATED-
01 != 11111 LD2Q (scalar plus scalar)FEAT_SVE2p1 || FEAT_SME2p1
10 != 11111 LD3Q (scalar plus scalar)FEAT_SVE2p1 || FEAT_SME2p1
11 != 11111 LD4Q (scalar plus scalar)FEAT_SVE2p1 || FEAT_SME2p1
!= 00 11111 UNALLOCATED-

SVE load and broadcast quadword (scalar plus immediate)

The encodings in this section are decoded from SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010mszssz0imm4001PgRnZt
Decode fields Instruction Details Feature
msz ssz
1x UNALLOCATED-
00 00 LD1RQB (scalar plus immediate)FEAT_SVE || FEAT_SME
00 01 LD1ROB (scalar plus immediate)FEAT_F64MM
01 00 LD1RQH (scalar plus immediate)FEAT_SVE || FEAT_SME
01 01 LD1ROH (scalar plus immediate)FEAT_F64MM
10 00 LD1RQW (scalar plus immediate)FEAT_SVE || FEAT_SME
10 01 LD1ROW (scalar plus immediate)FEAT_F64MM
11 00 LD1RQD (scalar plus immediate)FEAT_SVE || FEAT_SME
11 01 LD1ROD (scalar plus immediate)FEAT_F64MM

SVE contiguous load (scalar plus immediate)

The encodings in this section are decoded from SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010dtype0imm4101PgRnZt
Decode fields Instruction Details Feature
dtype
0000 LD1B (scalar plus immediate, single register) — 8-bit elementFEAT_SVE || FEAT_SME
0001 LD1B (scalar plus immediate, single register) — 16-bit elementFEAT_SVE || FEAT_SME
0010 LD1B (scalar plus immediate, single register) — 32-bit elementFEAT_SVE || FEAT_SME
0011 LD1B (scalar plus immediate, single register) — 64-bit elementFEAT_SVE || FEAT_SME
0100 LD1SW (scalar plus immediate)FEAT_SVE || FEAT_SME
0101 LD1H (scalar plus immediate, single register) — 16-bit elementFEAT_SVE || FEAT_SME
0110 LD1H (scalar plus immediate, single register) — 32-bit elementFEAT_SVE || FEAT_SME
0111 LD1H (scalar plus immediate, single register) — 64-bit elementFEAT_SVE || FEAT_SME
1000 LD1SH (scalar plus immediate) — 64-bit elementFEAT_SVE || FEAT_SME
1001 LD1SH (scalar plus immediate) — 32-bit elementFEAT_SVE || FEAT_SME
1010 LD1W (scalar plus immediate, single register) — 32-bit elementFEAT_SVE || FEAT_SME
1011 LD1W (scalar plus immediate, single register) — 64-bit elementFEAT_SVE || FEAT_SME
1100 LD1SB (scalar plus immediate) — 64-bit elementFEAT_SVE || FEAT_SME
1101 LD1SB (scalar plus immediate) — 32-bit elementFEAT_SVE || FEAT_SME
1110 LD1SB (scalar plus immediate) — 16-bit elementFEAT_SVE || FEAT_SME
1111 LD1D (scalar plus immediate, single register)FEAT_SVE || FEAT_SME

SVE contiguous non-fault load (scalar plus immediate)

The encodings in this section are decoded from SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010dtype1imm4101PgRnZt
Decode fields Instruction Details Feature
dtype
0000 LDNF1B — 8-bit elementFEAT_SVE
0001 LDNF1B — 16-bit elementFEAT_SVE
0010 LDNF1B — 32-bit elementFEAT_SVE
0011 LDNF1B — 64-bit elementFEAT_SVE
0100 LDNF1SWFEAT_SVE
0101 LDNF1H — 16-bit elementFEAT_SVE
0110 LDNF1H — 32-bit elementFEAT_SVE
0111 LDNF1H — 64-bit elementFEAT_SVE
1000 LDNF1SH — 64-bit elementFEAT_SVE
1001 LDNF1SH — 32-bit elementFEAT_SVE
1010 LDNF1W — 32-bit elementFEAT_SVE
1011 LDNF1W — 64-bit elementFEAT_SVE
1100 LDNF1SB — 64-bit elementFEAT_SVE
1101 LDNF1SB — 32-bit elementFEAT_SVE
1110 LDNF1SB — 16-bit elementFEAT_SVE
1111 LDNF1DFEAT_SVE

SVE load and broadcast quadword (scalar plus scalar)

The encodings in this section are decoded from SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010mszsszRm000PgRnZt
Decode fields Instruction Details Feature
msz ssz Rm
0x 11111 UNALLOCATED-
1x UNALLOCATED-
00 00 != 11111 LD1RQB (scalar plus scalar)FEAT_SVE || FEAT_SME
00 01 != 11111 LD1ROB (scalar plus scalar)FEAT_F64MM
01 00 != 11111 LD1RQH (scalar plus scalar)FEAT_SVE || FEAT_SME
01 01 != 11111 LD1ROH (scalar plus scalar)FEAT_F64MM
10 00 != 11111 LD1RQW (scalar plus scalar)FEAT_SVE || FEAT_SME
10 01 != 11111 LD1ROW (scalar plus scalar)FEAT_F64MM
11 00 != 11111 LD1RQD (scalar plus scalar)FEAT_SVE || FEAT_SME
11 01 != 11111 LD1ROD (scalar plus scalar)FEAT_F64MM

SVE contiguous load (scalar plus scalar)

The encodings in this section are decoded from SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010dtypeRm010PgRnZt
Decode fields Instruction Details Feature
dtype Rm
11111 UNALLOCATED-
0000 != 11111 LD1B (scalar plus scalar, single register) — 8-bit elementFEAT_SVE || FEAT_SME
0001 != 11111 LD1B (scalar plus scalar, single register) — 16-bit elementFEAT_SVE || FEAT_SME
0010 != 11111 LD1B (scalar plus scalar, single register) — 32-bit elementFEAT_SVE || FEAT_SME
0011 != 11111 LD1B (scalar plus scalar, single register) — 64-bit elementFEAT_SVE || FEAT_SME
0100 != 11111 LD1SW (scalar plus scalar)FEAT_SVE || FEAT_SME
0101 != 11111 LD1H (scalar plus scalar, single register) — 16-bit elementFEAT_SVE || FEAT_SME
0110 != 11111 LD1H (scalar plus scalar, single register) — 32-bit elementFEAT_SVE || FEAT_SME
0111 != 11111 LD1H (scalar plus scalar, single register) — 64-bit elementFEAT_SVE || FEAT_SME
1000 != 11111 LD1SH (scalar plus scalar) — 64-bit elementFEAT_SVE || FEAT_SME
1001 != 11111 LD1SH (scalar plus scalar) — 32-bit elementFEAT_SVE || FEAT_SME
1010 != 11111 LD1W (scalar plus scalar, single register) — 32-bit elementFEAT_SVE || FEAT_SME
1011 != 11111 LD1W (scalar plus scalar, single register) — 64-bit elementFEAT_SVE || FEAT_SME
1100 != 11111 LD1SB (scalar plus scalar) — 64-bit elementFEAT_SVE || FEAT_SME
1101 != 11111 LD1SB (scalar plus scalar) — 32-bit elementFEAT_SVE || FEAT_SME
1110 != 11111 LD1SB (scalar plus scalar) — 16-bit elementFEAT_SVE || FEAT_SME
1111 != 11111 LD1D (scalar plus scalar, single register)FEAT_SVE || FEAT_SME

SVE contiguous first-fault load (scalar plus scalar)

The encodings in this section are decoded from SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010dtypeRm011PgRnZt
Decode fields Instruction Details Feature
dtype
0000 LDFF1B (scalar plus scalar) — 8-bit elementFEAT_SVE
0001 LDFF1B (scalar plus scalar) — 16-bit elementFEAT_SVE
0010 LDFF1B (scalar plus scalar) — 32-bit elementFEAT_SVE
0011 LDFF1B (scalar plus scalar) — 64-bit elementFEAT_SVE
0100 LDFF1SW (scalar plus scalar)FEAT_SVE
0101 LDFF1H (scalar plus scalar) — 16-bit elementFEAT_SVE
0110 LDFF1H (scalar plus scalar) — 32-bit elementFEAT_SVE
0111 LDFF1H (scalar plus scalar) — 64-bit elementFEAT_SVE
1000 LDFF1SH (scalar plus scalar) — 64-bit elementFEAT_SVE
1001 LDFF1SH (scalar plus scalar) — 32-bit elementFEAT_SVE
1010 LDFF1W (scalar plus scalar) — 32-bit elementFEAT_SVE
1011 LDFF1W (scalar plus scalar) — 64-bit elementFEAT_SVE
1100 LDFF1SB (scalar plus scalar) — 64-bit elementFEAT_SVE
1101 LDFF1SB (scalar plus scalar) — 32-bit elementFEAT_SVE
1110 LDFF1SB (scalar plus scalar) — 16-bit elementFEAT_SVE
1111 LDFF1D (scalar plus scalar)FEAT_SVE

SVE load multiple structures (scalar plus immediate)

The encodings in this section are decoded from SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010msz!= 000imm4111PgRnZt
opc

The following constraints also apply to this encoding: opc != '00'

Decode fields Instruction Details Feature
msz opc
00 01 LD2B (scalar plus immediate)FEAT_SVE || FEAT_SME
00 10 LD3B (scalar plus immediate)FEAT_SVE || FEAT_SME
00 11 LD4B (scalar plus immediate)FEAT_SVE || FEAT_SME
01 01 LD2H (scalar plus immediate)FEAT_SVE || FEAT_SME
01 10 LD3H (scalar plus immediate)FEAT_SVE || FEAT_SME
01 11 LD4H (scalar plus immediate)FEAT_SVE || FEAT_SME
10 01 LD2W (scalar plus immediate)FEAT_SVE || FEAT_SME
10 10 LD3W (scalar plus immediate)FEAT_SVE || FEAT_SME
10 11 LD4W (scalar plus immediate)FEAT_SVE || FEAT_SME
11 01 LD2D (scalar plus immediate)FEAT_SVE || FEAT_SME
11 10 LD3D (scalar plus immediate)FEAT_SVE || FEAT_SME
11 11 LD4D (scalar plus immediate)FEAT_SVE || FEAT_SME

SVE load multiple structures (scalar plus scalar)

The encodings in this section are decoded from SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010msz!= 00Rm110PgRnZt
opc

The following constraints also apply to this encoding: opc != '00'

Decode fields Instruction Details Feature
msz opc Rm
!= 00 11111 UNALLOCATED-
00 01 != 11111 LD2B (scalar plus scalar)FEAT_SVE || FEAT_SME
00 10 != 11111 LD3B (scalar plus scalar)FEAT_SVE || FEAT_SME
00 11 != 11111 LD4B (scalar plus scalar)FEAT_SVE || FEAT_SME
01 01 != 11111 LD2H (scalar plus scalar)FEAT_SVE || FEAT_SME
01 10 != 11111 LD3H (scalar plus scalar)FEAT_SVE || FEAT_SME
01 11 != 11111 LD4H (scalar plus scalar)FEAT_SVE || FEAT_SME
10 01 != 11111 LD2W (scalar plus scalar)FEAT_SVE || FEAT_SME
10 10 != 11111 LD3W (scalar plus scalar)FEAT_SVE || FEAT_SME
10 11 != 11111 LD4W (scalar plus scalar)FEAT_SVE || FEAT_SME
11 01 != 11111 LD2D (scalar plus scalar)FEAT_SVE || FEAT_SME
11 10 != 11111 LD3D (scalar plus scalar)FEAT_SVE || FEAT_SME
11 11 != 11111 LD4D (scalar plus scalar)FEAT_SVE || FEAT_SME

SVE Memory - 64-bit Gather

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
1100010op0op1op2op3
Decode fieldsInstruction detailsFeature
op0op1op2op3
00 00 101 LD1QFEAT_SVE2p1
00 01 0xx 1 UNALLOCATED-
00 11 1xx 0 SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)-
00 11 1 UNALLOCATED-
00 x1 0xx 0 SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)-
00 111 0 SVE 64-bit gather prefetch (vector plus immediate)-
00 111 1 UNALLOCATED-
00 1x0 SVE2 64-bit gather non-temporal load (vector plus scalar)-
01 1xx SVE 64-bit gather load (vector plus immediate)-
10 1xx SVE 64-bit gather load (scalar plus 64-bit unscaled offsets)-
x0 0xx SVE 64-bit gather load (scalar plus unpacked 32-bit unscaled offsets)-
!= 00 00 101 UNALLOCATED-
!= 00 11 1xx SVE 64-bit gather load (scalar plus 64-bit scaled offsets)-
!= 00 x1 0xx SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets)-

SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)

The encodings in this section are decoded from SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
11000100011Zm1mszPgRn0prfop
Decode fields Instruction Details Feature
msz
00 PRFB (scalar plus vector)FEAT_SVE
01 PRFH (scalar plus vector)FEAT_SVE
10 PRFW (scalar plus vector)FEAT_SVE
11 PRFD (scalar plus vector)FEAT_SVE

SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)

The encodings in this section are decoded from SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
110001000xs1Zm0mszPgRn0prfop
Decode fields Instruction Details Feature
msz
00 PRFB (scalar plus vector)FEAT_SVE
01 PRFH (scalar plus vector)FEAT_SVE
10 PRFW (scalar plus vector)FEAT_SVE
11 PRFD (scalar plus vector)FEAT_SVE

SVE 64-bit gather prefetch (vector plus immediate)

The encodings in this section are decoded from SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
1100010msz00imm5111PgZn0prfop
Decode fields Instruction Details Feature
msz
00 PRFB (vector plus immediate)FEAT_SVE
01 PRFH (vector plus immediate)FEAT_SVE
10 PRFW (vector plus immediate)FEAT_SVE
11 PRFD (vector plus immediate)FEAT_SVE

SVE2 64-bit gather non-temporal load (vector plus scalar)

The encodings in this section are decoded from SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
1100010msz00Rm1U0PgZnZt
Decode fields Instruction Details Feature
msz U
00 0 LDNT1SBFEAT_SVE2
00 1 LDNT1B (vector plus scalar)FEAT_SVE2
01 0 LDNT1SHFEAT_SVE2
01 1 LDNT1H (vector plus scalar)FEAT_SVE2
10 0 LDNT1SWFEAT_SVE2
10 1 LDNT1W (vector plus scalar)FEAT_SVE2
11 0 UNALLOCATED-
11 1 LDNT1D (vector plus scalar)FEAT_SVE2

SVE 64-bit gather load (vector plus immediate)

The encodings in this section are decoded from SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
1100010msz01imm51UffPgZnZt
Decode fields Instruction Details Feature
msz U ff
00 0 0 LD1SB (vector plus immediate)FEAT_SVE
00 0 1 LDFF1SB (vector plus immediate)FEAT_SVE
00 1 0 LD1B (vector plus immediate)FEAT_SVE
00 1 1 LDFF1B (vector plus immediate)FEAT_SVE
01 0 0 LD1SH (vector plus immediate)FEAT_SVE
01 0 1 LDFF1SH (vector plus immediate)FEAT_SVE
01 1 0 LD1H (vector plus immediate)FEAT_SVE
01 1 1 LDFF1H (vector plus immediate)FEAT_SVE
10 0 0 LD1SW (vector plus immediate)FEAT_SVE
10 0 1 LDFF1SW (vector plus immediate)FEAT_SVE
10 1 0 LD1W (vector plus immediate)FEAT_SVE
10 1 1 LDFF1W (vector plus immediate)FEAT_SVE
11 0 UNALLOCATED-
11 1 0 LD1D (vector plus immediate)FEAT_SVE
11 1 1 LDFF1D (vector plus immediate)FEAT_SVE

SVE 64-bit gather load (scalar plus 64-bit unscaled offsets)

The encodings in this section are decoded from SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
1100010msz10Zm1UffPgRnZt
Decode fields Instruction Details Feature
msz U ff
00 0 0 LD1SB (scalar plus vector)FEAT_SVE
00 0 1 LDFF1SB (scalar plus vector)FEAT_SVE
00 1 0 LD1B (scalar plus vector)FEAT_SVE
00 1 1 LDFF1B (scalar plus vector)FEAT_SVE
01 0 0 LD1SH (scalar plus vector)FEAT_SVE
01 0 1 LDFF1SH (scalar plus vector)FEAT_SVE
01 1 0 LD1H (scalar plus vector)FEAT_SVE
01 1 1 LDFF1H (scalar plus vector)FEAT_SVE
10 0 0 LD1SW (scalar plus vector)FEAT_SVE
10 0 1 LDFF1SW (scalar plus vector)FEAT_SVE
10 1 0 LD1W (scalar plus vector)FEAT_SVE
10 1 1 LDFF1W (scalar plus vector)FEAT_SVE
11 0 UNALLOCATED-
11 1 0 LD1D (scalar plus vector)FEAT_SVE
11 1 1 LDFF1D (scalar plus vector)FEAT_SVE

SVE 64-bit gather load (scalar plus unpacked 32-bit unscaled offsets)

The encodings in this section are decoded from SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
1100010mszxs0Zm0UffPgRnZt
Decode fields Instruction Details Feature
msz U ff
00 0 0 LD1SB (scalar plus vector)FEAT_SVE
00 0 1 LDFF1SB (scalar plus vector)FEAT_SVE
00 1 0 LD1B (scalar plus vector)FEAT_SVE
00 1 1 LDFF1B (scalar plus vector)FEAT_SVE
01 0 0 LD1SH (scalar plus vector)FEAT_SVE
01 0 1 LDFF1SH (scalar plus vector)FEAT_SVE
01 1 0 LD1H (scalar plus vector)FEAT_SVE
01 1 1 LDFF1H (scalar plus vector)FEAT_SVE
10 0 0 LD1SW (scalar plus vector)FEAT_SVE
10 0 1 LDFF1SW (scalar plus vector)FEAT_SVE
10 1 0 LD1W (scalar plus vector)FEAT_SVE
10 1 1 LDFF1W (scalar plus vector)FEAT_SVE
11 0 UNALLOCATED-
11 1 0 LD1D (scalar plus vector)FEAT_SVE
11 1 1 LDFF1D (scalar plus vector)FEAT_SVE

SVE 64-bit gather load (scalar plus 64-bit scaled offsets)

The encodings in this section are decoded from SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
1100010!= 0011Zm1UffPgRnZt
opc

The following constraints also apply to this encoding: opc != '00'

Decode fields Instruction Details Feature
opc U ff
01 0 0 LD1SH (scalar plus vector)FEAT_SVE
01 0 1 LDFF1SH (scalar plus vector)FEAT_SVE
01 1 0 LD1H (scalar plus vector)FEAT_SVE
01 1 1 LDFF1H (scalar plus vector)FEAT_SVE
10 0 0 LD1SW (scalar plus vector)FEAT_SVE
10 0 1 LDFF1SW (scalar plus vector)FEAT_SVE
10 1 0 LD1W (scalar plus vector)FEAT_SVE
10 1 1 LDFF1W (scalar plus vector)FEAT_SVE
11 0 UNALLOCATED-
11 1 0 LD1D (scalar plus vector)FEAT_SVE
11 1 1 LDFF1D (scalar plus vector)FEAT_SVE

SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets)

The encodings in this section are decoded from SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
1100010!= 00xs1Zm0UffPgRnZt
opc

The following constraints also apply to this encoding: opc != '00'

Decode fields Instruction Details Feature
opc U ff
01 0 0 LD1SH (scalar plus vector)FEAT_SVE
01 0 1 LDFF1SH (scalar plus vector)FEAT_SVE
01 1 0 LD1H (scalar plus vector)FEAT_SVE
01 1 1 LDFF1H (scalar plus vector)FEAT_SVE
10 0 0 LD1SW (scalar plus vector)FEAT_SVE
10 0 1 LDFF1SW (scalar plus vector)FEAT_SVE
10 1 0 LD1W (scalar plus vector)FEAT_SVE
10 1 1 LDFF1W (scalar plus vector)FEAT_SVE
11 0 UNALLOCATED-
11 1 0 LD1D (scalar plus vector)FEAT_SVE
11 1 1 LDFF1D (scalar plus vector)FEAT_SVE

SVE Memory - Non-temporal and Quadword Scatter Store

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
1110010op0op1001
Decode fieldsInstruction detailsFeature
op0op1
000 1 ST1QFEAT_SVE2p1
xx0 0 SVE2 64-bit scatter non-temporal store (vector plus scalar)-
xx1 0 SVE2 32-bit scatter non-temporal store (vector plus scalar)-
!= 000 1 UNALLOCATED-

SVE2 64-bit scatter non-temporal store (vector plus scalar)

The encodings in this section are decoded from SVE Memory - Non-temporal and Quadword Scatter Store.

313029282726252423222120191817161514131211109876543210
1110010msz00Rm001PgZnZt
Decode fields Instruction Details Feature
msz
00 STNT1B (vector plus scalar)FEAT_SVE2
01 STNT1H (vector plus scalar)FEAT_SVE2
10 STNT1W (vector plus scalar)FEAT_SVE2
11 STNT1D (vector plus scalar)FEAT_SVE2

SVE2 32-bit scatter non-temporal store (vector plus scalar)

The encodings in this section are decoded from SVE Memory - Non-temporal and Quadword Scatter Store.

313029282726252423222120191817161514131211109876543210
1110010msz10Rm001PgZnZt
Decode fields Instruction Details Feature
msz
00 STNT1B (vector plus scalar)FEAT_SVE2
01 STNT1H (vector plus scalar)FEAT_SVE2
10 STNT1W (vector plus scalar)FEAT_SVE2
11 UNALLOCATED-

SVE Memory - Non-temporal and Multi-register Contiguous Store

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
1110010op0011
Decode fieldsInstruction details
op0
00 SVE contiguous non-temporal store (scalar plus scalar)
!= 00 SVE store multiple structures (scalar plus scalar)

SVE contiguous non-temporal store (scalar plus scalar)

The encodings in this section are decoded from SVE Memory - Non-temporal and Multi-register Contiguous Store.

313029282726252423222120191817161514131211109876543210
1110010msz00Rm011PgRnZt
Decode fields Instruction Details Feature
msz Rm
11111 UNALLOCATED-
00 != 11111 STNT1B (scalar plus scalar, single register)FEAT_SVE || FEAT_SME
01 != 11111 STNT1H (scalar plus scalar, single register)FEAT_SVE || FEAT_SME
10 != 11111 STNT1W (scalar plus scalar, single register)FEAT_SVE || FEAT_SME
11 != 11111 STNT1D (scalar plus scalar, single register)FEAT_SVE || FEAT_SME

SVE store multiple structures (scalar plus scalar)

The encodings in this section are decoded from SVE Memory - Non-temporal and Multi-register Contiguous Store.

313029282726252423222120191817161514131211109876543210
1110010msz!= 00Rm011PgRnZt
opc

The following constraints also apply to this encoding: opc != '00'

Decode fields Instruction Details Feature
msz opc Rm
!= 00 11111 UNALLOCATED-
00 01 != 11111 ST2B (scalar plus scalar)FEAT_SVE || FEAT_SME
00 10 != 11111 ST3B (scalar plus scalar)FEAT_SVE || FEAT_SME
00 11 != 11111 ST4B (scalar plus scalar)FEAT_SVE || FEAT_SME
01 01 != 11111 ST2H (scalar plus scalar)FEAT_SVE || FEAT_SME
01 10 != 11111 ST3H (scalar plus scalar)FEAT_SVE || FEAT_SME
01 11 != 11111 ST4H (scalar plus scalar)FEAT_SVE || FEAT_SME
10 01 != 11111 ST2W (scalar plus scalar)FEAT_SVE || FEAT_SME
10 10 != 11111 ST3W (scalar plus scalar)FEAT_SVE || FEAT_SME
10 11 != 11111 ST4W (scalar plus scalar)FEAT_SVE || FEAT_SME
11 01 != 11111 ST2D (scalar plus scalar)FEAT_SVE || FEAT_SME
11 10 != 11111 ST3D (scalar plus scalar)FEAT_SVE || FEAT_SME
11 11 != 11111 ST4D (scalar plus scalar)FEAT_SVE || FEAT_SME

SVE Memory - Contiguous Store and Unsized Contiguous

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
1110010op0op10op20op3
Decode fieldsInstruction detailsFeature
op0op1op2op3
0xx 00 0 SVE store multiple structures (quadwords, scalar plus immediate)-
0xx 01 0 UNALLOCATED-
0xx 1x 0 SVE store multiple structures (quadwords, scalar plus scalar)-
10x 0 UNALLOCATED-
110 0 0 STR (predicate)FEAT_SVE || FEAT_SME
110 0 1 UNALLOCATED-
110 1 STR (vector)FEAT_SVE || FEAT_SME
111 0 UNALLOCATED-
!= 110 1 SVE contiguous store (scalar plus scalar)-

SVE store multiple structures (quadwords, scalar plus immediate)

The encodings in this section are decoded from SVE Memory - Contiguous Store and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
11100100num00imm4000PgRnZt
Decode fields Instruction Details Feature
num
00 UNALLOCATED-
01 ST2Q (scalar plus immediate)FEAT_SVE2p1 || FEAT_SME2p1
10 ST3Q (scalar plus immediate)FEAT_SVE2p1 || FEAT_SME2p1
11 ST4Q (scalar plus immediate)FEAT_SVE2p1 || FEAT_SME2p1

SVE store multiple structures (quadwords, scalar plus scalar)

The encodings in this section are decoded from SVE Memory - Contiguous Store and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
11100100num1Rm000PgRnZt
Decode fields Instruction Details Feature
num Rm
00 UNALLOCATED-
01 != 11111 ST2Q (scalar plus scalar)FEAT_SVE2p1 || FEAT_SME2p1
10 != 11111 ST3Q (scalar plus scalar)FEAT_SVE2p1 || FEAT_SME2p1
11 != 11111 ST4Q (scalar plus scalar)FEAT_SVE2p1 || FEAT_SME2p1
!= 00 11111 UNALLOCATED-

SVE contiguous store (scalar plus scalar)

The encodings in this section are decoded from SVE Memory - Contiguous Store and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1110010!= 110o2Rm010PgRnZt
opc

The following constraints also apply to this encoding: opc != '110'

Decode fields Instruction Details Feature
opc o2 Rm
xx1 11111 UNALLOCATED-
0x0 11111 UNALLOCATED-
00x != 11111 ST1B (scalar plus scalar, single register)FEAT_SVE || FEAT_SME
01x != 11111 ST1H (scalar plus scalar, single register)FEAT_SVE || FEAT_SME
100 0 11111 UNALLOCATED-
100 0 != 11111 ST1W (scalar plus scalar, single register) — SVE2FEAT_SVE2p1
100 1 UNALLOCATED-
101 != 11111 ST1W (scalar plus scalar, single register) — SVEFEAT_SVE || FEAT_SME
111 0 != 11111 ST1D (scalar plus scalar, single register) — SVE2FEAT_SVE2p1
111 1 != 11111 ST1D (scalar plus scalar, single register) — SVEFEAT_SVE || FEAT_SME

SVE Memory - Scatter

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
1110010op0101
Decode fieldsInstruction details
op0
00 SVE 64-bit scatter store (scalar plus 64-bit unscaled offsets)
01 SVE 64-bit scatter store (scalar plus 64-bit scaled offsets)
10 SVE 64-bit scatter store (vector plus immediate)
11 SVE 32-bit scatter store (vector plus immediate)

SVE 64-bit scatter store (scalar plus 64-bit unscaled offsets)

The encodings in this section are decoded from SVE Memory - Scatter.

313029282726252423222120191817161514131211109876543210
1110010msz00Zm101PgRnZt
Decode fields Instruction Details Feature
msz
00 ST1B (scalar plus vector)FEAT_SVE
01 ST1H (scalar plus vector)FEAT_SVE
10 ST1W (scalar plus vector)FEAT_SVE
11 ST1D (scalar plus vector)FEAT_SVE

SVE 64-bit scatter store (scalar plus 64-bit scaled offsets)

The encodings in this section are decoded from SVE Memory - Scatter.

313029282726252423222120191817161514131211109876543210
1110010msz01Zm101PgRnZt
Decode fields Instruction Details Feature
msz
00 UNALLOCATED-
01 ST1H (scalar plus vector)FEAT_SVE
10 ST1W (scalar plus vector)FEAT_SVE
11 ST1D (scalar plus vector)FEAT_SVE

SVE 64-bit scatter store (vector plus immediate)

The encodings in this section are decoded from SVE Memory - Scatter.

313029282726252423222120191817161514131211109876543210
1110010msz10imm5101PgZnZt
Decode fields Instruction Details Feature
msz
00 ST1B (vector plus immediate)FEAT_SVE
01 ST1H (vector plus immediate)FEAT_SVE
10 ST1W (vector plus immediate)FEAT_SVE
11 ST1D (vector plus immediate)FEAT_SVE

SVE 32-bit scatter store (vector plus immediate)

The encodings in this section are decoded from SVE Memory - Scatter.

313029282726252423222120191817161514131211109876543210
1110010msz11imm5101PgZnZt
Decode fields Instruction Details Feature
msz
00 ST1B (vector plus immediate)FEAT_SVE
01 ST1H (vector plus immediate)FEAT_SVE
10 ST1W (vector plus immediate)FEAT_SVE
11 UNALLOCATED-

SVE Memory - Contiguous Store with Immediate Offset

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
1110010op0op1111
Decode fieldsInstruction details
op0op1
00 1 SVE contiguous non-temporal store (scalar plus immediate)
0 SVE contiguous store (scalar plus immediate)
!= 00 1 SVE store multiple structures (scalar plus immediate)

SVE contiguous non-temporal store (scalar plus immediate)

The encodings in this section are decoded from SVE Memory - Contiguous Store with Immediate Offset.

313029282726252423222120191817161514131211109876543210
1110010msz001imm4111PgRnZt
Decode fields Instruction Details Feature
msz
00 STNT1B (scalar plus immediate, single register)FEAT_SVE || FEAT_SME
01 STNT1H (scalar plus immediate, single register)FEAT_SVE || FEAT_SME
10 STNT1W (scalar plus immediate, single register)FEAT_SVE || FEAT_SME
11 STNT1D (scalar plus immediate, single register)FEAT_SVE || FEAT_SME

SVE contiguous store (scalar plus immediate)

The encodings in this section are decoded from SVE Memory - Contiguous Store with Immediate Offset.

313029282726252423222120191817161514131211109876543210
1110010mszopc0imm4111PgRnZt
Decode fields Instruction Details Feature
msz opc
00 ST1B (scalar plus immediate, single register)FEAT_SVE || FEAT_SME
01 ST1H (scalar plus immediate, single register)FEAT_SVE || FEAT_SME
10 00 ST1W (scalar plus immediate, single register) — SVE2FEAT_SVE2p1
10 01 UNALLOCATED-
10 1x ST1W (scalar plus immediate, single register) — SVEFEAT_SVE || FEAT_SME
11 0x UNALLOCATED-
11 10 ST1D (scalar plus immediate, single register) — SVE2FEAT_SVE2p1
11 11 ST1D (scalar plus immediate, single register) — SVEFEAT_SVE || FEAT_SME

SVE store multiple structures (scalar plus immediate)

The encodings in this section are decoded from SVE Memory - Contiguous Store with Immediate Offset.

313029282726252423222120191817161514131211109876543210
1110010msz!= 001imm4111PgRnZt
opc

The following constraints also apply to this encoding: opc != '00'

Decode fields Instruction Details Feature
msz opc
00 01 ST2B (scalar plus immediate)FEAT_SVE || FEAT_SME
00 10 ST3B (scalar plus immediate)FEAT_SVE || FEAT_SME
00 11 ST4B (scalar plus immediate)FEAT_SVE || FEAT_SME
01 01 ST2H (scalar plus immediate)FEAT_SVE || FEAT_SME
01 10 ST3H (scalar plus immediate)FEAT_SVE || FEAT_SME
01 11 ST4H (scalar plus immediate)FEAT_SVE || FEAT_SME
10 01 ST2W (scalar plus immediate)FEAT_SVE || FEAT_SME
10 10 ST3W (scalar plus immediate)FEAT_SVE || FEAT_SME
10 11 ST4W (scalar plus immediate)FEAT_SVE || FEAT_SME
11 01 ST2D (scalar plus immediate)FEAT_SVE || FEAT_SME
11 10 ST3D (scalar plus immediate)FEAT_SVE || FEAT_SME
11 11 ST4D (scalar plus immediate)FEAT_SVE || FEAT_SME

SVE Memory - Scatter with Optional Sign Extend

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
1110010op010
Decode fieldsInstruction details
op0
00 SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offsets)
01 SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offsets)
10 SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets)
11 SVE 32-bit scatter store (scalar plus 32-bit scaled offsets)

SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offsets)

The encodings in this section are decoded from SVE Memory - Scatter with Optional Sign Extend.

313029282726252423222120191817161514131211109876543210
1110010msz00Zm1xs0PgRnZt
Decode fields Instruction Details Feature
msz
00 ST1B (scalar plus vector)FEAT_SVE
01 ST1H (scalar plus vector)FEAT_SVE
10 ST1W (scalar plus vector)FEAT_SVE
11 ST1D (scalar plus vector)FEAT_SVE

SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offsets)

The encodings in this section are decoded from SVE Memory - Scatter with Optional Sign Extend.

313029282726252423222120191817161514131211109876543210
1110010msz01Zm1xs0PgRnZt
Decode fields Instruction Details Feature
msz
00 UNALLOCATED-
01 ST1H (scalar plus vector)FEAT_SVE
10 ST1W (scalar plus vector)FEAT_SVE
11 ST1D (scalar plus vector)FEAT_SVE

SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets)

The encodings in this section are decoded from SVE Memory - Scatter with Optional Sign Extend.

313029282726252423222120191817161514131211109876543210
1110010msz10Zm1xs0PgRnZt
Decode fields Instruction Details Feature
msz
00 ST1B (scalar plus vector)FEAT_SVE
01 ST1H (scalar plus vector)FEAT_SVE
10 ST1W (scalar plus vector)FEAT_SVE
11 UNALLOCATED-

SVE 32-bit scatter store (scalar plus 32-bit scaled offsets)

The encodings in this section are decoded from SVE Memory - Scatter with Optional Sign Extend.

313029282726252423222120191817161514131211109876543210
1110010msz11Zm1xs0PgRnZt
Decode fields Instruction Details Feature
msz
00 UNALLOCATED-
01 ST1H (scalar plus vector)FEAT_SVE
10 ST1W (scalar plus vector)FEAT_SVE
11 UNALLOCATED-

SVE integer add/subtract vectors (unpredicated)

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
00000100size1Zm000opcZnZd
Decode fields Instruction Details Feature
size opc
000 ADD (vectors, unpredicated)FEAT_SVE || FEAT_SME
001 SUB (vectors, unpredicated)FEAT_SVE || FEAT_SME
100 SQADD (vectors, unpredicated)FEAT_SVE || FEAT_SME
101 UQADD (vectors, unpredicated)FEAT_SVE || FEAT_SME
110 SQSUB (vectors, unpredicated)FEAT_SVE || FEAT_SME
111 UQSUB (vectors, unpredicated)FEAT_SVE || FEAT_SME
11 010 ADDPT (unpredicated)FEAT_SVE && FEAT_CPA
11 011 SUBPT (unpredicated)FEAT_SVE && FEAT_CPA
!= 11 01x UNALLOCATED-

SVE address generation

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
00000100opc1Zm1010mszZnZd
Decode fields Instruction Details Feature
opc
00 ADR — Unpacked 32-bit signed offsetsFEAT_SVE
01 ADR — Unpacked 32-bit unsigned offsetsFEAT_SVE
1x ADR — Packed offsetsFEAT_SVE

SVE table lookup (three sources)

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
00000101size1Zm00101opZnZd
Decode fields Instruction Details Feature
op
0 TBLFEAT_SVE2 || FEAT_SME
1 TBXFEAT_SVE2 || FEAT_SME

SVE permute vector elements

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
00000101size1Zm011opcZnZd
Decode fields Instruction Details Feature
opc
000 ZIP1, ZIP2 (vectors) — Low halvesFEAT_SVE || FEAT_SME
001 ZIP1, ZIP2 (vectors) — High halvesFEAT_SVE || FEAT_SME
010 UZP1, UZP2 (vectors) — EvenFEAT_SVE || FEAT_SME
011 UZP1, UZP2 (vectors) — OddFEAT_SVE || FEAT_SME
100 TRN1, TRN2 (vectors) — EvenFEAT_SVE || FEAT_SME
101 TRN1, TRN2 (vectors) — OddFEAT_SVE || FEAT_SME
11x UNALLOCATED-

SVE integer compare with unsigned immediate

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
001001001imm7ltPgZnnePd
Decode fields Instruction Details Feature
lt ne
0 0 CMP<cc> (immediate) — Higher or sameFEAT_SVE || FEAT_SME
0 1 CMP<cc> (immediate) — HigherFEAT_SVE || FEAT_SME
1 0 CMP<cc> (immediate) — LowerFEAT_SVE || FEAT_SME
1 1 CMP<cc> (immediate) — Lower or sameFEAT_SVE || FEAT_SME

SVE predicate logical operations

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
00100101opS00Pm01Pgo2Pno3Pd
Decode fields Instruction Details Feature
op S o2 o3
0 0 0 0 AND (predicates)FEAT_SVE || FEAT_SME
0 0 0 1 BIC (predicates)FEAT_SVE || FEAT_SME
0 0 1 0 EOR (predicates)FEAT_SVE || FEAT_SME
0 0 1 1 SEL (predicates)FEAT_SVE || FEAT_SME
0 1 0 0 ANDSFEAT_SVE || FEAT_SME
0 1 0 1 BICSFEAT_SVE || FEAT_SME
0 1 1 0 EORSFEAT_SVE || FEAT_SME
0 1 1 1 UNALLOCATED-
1 0 0 0 ORR (predicates)FEAT_SVE || FEAT_SME
1 0 0 1 ORN (predicates)FEAT_SVE || FEAT_SME
1 0 1 0 NORFEAT_SVE || FEAT_SME
1 0 1 1 NANDFEAT_SVE || FEAT_SME
1 1 0 0 ORRSFEAT_SVE || FEAT_SME
1 1 0 1 ORNSFEAT_SVE || FEAT_SME
1 1 1 0 NORSFEAT_SVE || FEAT_SME
1 1 1 1 NANDSFEAT_SVE || FEAT_SME

SVE integer compare with signed immediate

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
00100101size0imm5op0o2PgZnnePd
Decode fields Instruction Details Feature
op o2 ne
0 0 0 CMP<cc> (immediate) — Greater than or equalFEAT_SVE || FEAT_SME
0 0 1 CMP<cc> (immediate) — Greater thanFEAT_SVE || FEAT_SME
0 1 0 CMP<cc> (immediate) — Less thanFEAT_SVE || FEAT_SME
0 1 1 CMP<cc> (immediate) — Less than or equalFEAT_SVE || FEAT_SME
1 0 0 CMP<cc> (immediate) — EqualFEAT_SVE || FEAT_SME
1 0 1 CMP<cc> (immediate) — Not equalFEAT_SVE || FEAT_SME
1 1 UNALLOCATED-

SVE broadcast predicate element

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
00100101i1tszh1tszlRv01PnSPm0Pd
Decode fields Instruction Details Feature
S
0 PSELFEAT_SME || FEAT_SVE2p1
1 UNALLOCATED-

SVE two-way dot product

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01000100000Zm11001UZnZda
Decode fields Instruction Details Feature
U
0 SDOT (2-way, vectors)FEAT_SME2 || FEAT_SVE2p1
1 UDOT (2-way, vectors)FEAT_SME2 || FEAT_SVE2p1

SVE two-way dot product (indexed)

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01000100100opc11001UZnZda
Decode fields Instruction Details Feature
U
0 SDOT (2-way, indexed)FEAT_SME2 || FEAT_SVE2p1
1 UDOT (2-way, indexed)FEAT_SME2 || FEAT_SVE2p1

SVE integer clamp

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01000100size0Zm11000UZnZd
Decode fields Instruction Details Feature
U
0 SCLAMPFEAT_SME || FEAT_SVE2p1
1 UCLAMPFEAT_SME || FEAT_SVE2p1

SVE2 multiply-add (checked pointer)

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01000100opc0Zm1101opc2ZnZda
Decode fields Instruction Details Feature
opc opc2
11 x1 UNALLOCATED-
11 00 MLAPTFEAT_SVE && FEAT_CPA
11 10 MADPTFEAT_SVE && FEAT_CPA
!= 11 UNALLOCATED-

SVE permute vector elements (quadwords)

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01000100size0Zm111opcZnZd
Decode fields Instruction Details Feature
opc
000 ZIPQ1FEAT_SVE2p1 || FEAT_SME2p1
001 ZIPQ2FEAT_SVE2p1 || FEAT_SME2p1
010 UZPQ1FEAT_SVE2p1 || FEAT_SME2p1
011 UZPQ2FEAT_SVE2p1 || FEAT_SME2p1
10x UNALLOCATED-
110 TBLQFEAT_SVE2p1 || FEAT_SME2p1
111 UNALLOCATED-

SVE2 character match

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01000101size1Zm100PgZnopPd
Decode fields Instruction Details Feature
op
0 MATCHFEAT_SVE2
1 NMATCHFEAT_SVE2

SVE2 FP8 matrix multiply-accumulate

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
011001000op1Zm111000ZnZda
Decode fields Instruction Details Feature
op
0 FMMLA (widening, FP8 to FP32)FEAT_SVE2 && FEAT_F8F32MM
1 FMMLA (widening, FP8 to FP16)FEAT_SVE2 && FEAT_F8F16MM

SVE2 FP8 multiply-add long (indexed)

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100T01i4hZm0101i4lZnZda
Decode fields Instruction Details Feature
T
0 FMLALB (indexed, FP8 to FP16)FEAT_SSVE_FP8FMA || (FEAT_SVE2 && FEAT_FP8FMA)
1 FMLALT (indexed, FP8 to FP16)FEAT_SSVE_FP8FMA || (FEAT_SVE2 && FEAT_FP8FMA)

SVE floating-point convert (top, predicated)

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100opc0000opc2101PgZnZd
Decode fields Instruction Details Feature
opc opc2
x0 11 UNALLOCATED-
00 0x UNALLOCATED-
00 10 FCVTXNTFEAT_SVE2p2 || FEAT_SME2p2
01 UNALLOCATED-
10 00 FCVTNT (predicated) — Single-precision to half-precision, zeroingFEAT_SVE2p2 || FEAT_SME2p2
10 01 FCVTLT — Half-precision to single-precision, zeroingFEAT_SVE2p2 || FEAT_SME2p2
10 10 BFCVTNTFEAT_SVE2p2 || FEAT_SME2p2
11 0x UNALLOCATED-
11 10 FCVTNT (predicated) — Double-precision to single-precision, zeroingFEAT_SVE2p2 || FEAT_SME2p2
11 11 FCVTLT — Single-precision to double-precision, zeroingFEAT_SVE2p2 || FEAT_SME2p2

SVE floating-point convert precision odd elements

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100opc0010opc2101PgZnZd
Decode fields Instruction Details Feature
opc opc2
x0 11 UNALLOCATED-
00 0x UNALLOCATED-
00 10 FCVTXNTFEAT_SVE2 || FEAT_SME
01 UNALLOCATED-
10 00 FCVTNT (predicated) — Single-precision to half-precision, mergingFEAT_SVE2 || FEAT_SME
10 01 FCVTLT — Half-precision to single-precision, mergingFEAT_SVE2 || FEAT_SME
10 10 BFCVTNT(FEAT_SVE && FEAT_BF16) || (FEAT_SME && FEAT_BF16)
11 0x UNALLOCATED-
11 10 FCVTNT (predicated) — Double-precision to single-precision, mergingFEAT_SVE2 || FEAT_SME
11 11 FCVTLT — Single-precision to double-precision, mergingFEAT_SVE2 || FEAT_SME

SVE2 floating-point pairwise operations

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100010opc100PgZmZdn
Decode fields Instruction Details Feature
opc
000 FADDPFEAT_SVE2 || FEAT_SME
001 UNALLOCATED-
01x UNALLOCATED-
100 FMAXNMPFEAT_SVE2 || FEAT_SME
101 FMINNMPFEAT_SVE2 || FEAT_SME
110 FMAXPFEAT_SVE2 || FEAT_SME
111 FMINPFEAT_SVE2 || FEAT_SME

SVE floating-point recursive reduction (quadwords)

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100size010opc101PgZnVd
Decode fields Instruction Details Feature
opc
000 FADDQVFEAT_SVE2p1 || FEAT_SME2p1
001 UNALLOCATED-
01x UNALLOCATED-
100 FMAXNMQVFEAT_SVE2p1 || FEAT_SME2p1
101 FMINNMQVFEAT_SVE2p1 || FEAT_SME2p1
110 FMAXQVFEAT_SVE2p1 || FEAT_SME2p1
111 FMINQVFEAT_SVE2p1 || FEAT_SME2p1

SVE floating-point multiply-add (indexed)

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100size1opc0000o2opZnZda
Decode fields Instruction Details Feature
size o2 op
0x 0 0 FMLA (indexed) — Half-precisionFEAT_SVE || FEAT_SME
0x 0 1 FMLS (indexed) — Half-precisionFEAT_SVE || FEAT_SME
0x 1 0 BFMLA (indexed)FEAT_SVE_B16B16
0x 1 1 BFMLS (indexed)FEAT_SVE_B16B16
1x 1 UNALLOCATED-
10 0 0 FMLA (indexed) — Single-precisionFEAT_SVE || FEAT_SME
10 0 1 FMLS (indexed) — Single-precisionFEAT_SVE || FEAT_SME
11 0 0 FMLA (indexed) — Double-precisionFEAT_SVE || FEAT_SME
11 0 1 FMLS (indexed) — Double-precisionFEAT_SVE || FEAT_SME

SVE floating-point complex multiply-add (indexed)

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100size1opc0001rotZnZda
Decode fields Instruction Details Feature
size
0x UNALLOCATED-
10 FCMLA (indexed) — Half-precisionFEAT_SVE || FEAT_SME
11 FCMLA (indexed) — Single-precisionFEAT_SVE || FEAT_SME

SVE FP clamp

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100size1Zm001001ZnZd
Decode fields Instruction Details Feature
size
00 BFCLAMPFEAT_SVE_B16B16
!= 00 FCLAMPFEAT_SME2 || FEAT_SVE2p1

SVE floating-point multiply (indexed)

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100size1opc0010o20ZnZd
Decode fields Instruction Details Feature
size o2
0x 0 FMUL (indexed) — Half-precisionFEAT_SVE || FEAT_SME
0x 1 BFMUL (indexed)FEAT_SVE_B16B16
1x 1 UNALLOCATED-
10 0 FMUL (indexed) — Single-precisionFEAT_SVE || FEAT_SME
11 0 FMUL (indexed) — Double-precisionFEAT_SVE || FEAT_SME

SVE2 FP8 multiply-add long long (indexed)

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100TT1i4hZm1100i4lZnZda
Decode fields Instruction Details Feature
TT
00 FMLALLBB (indexed)FEAT_SSVE_FP8FMA || (FEAT_SVE2 && FEAT_FP8FMA)
01 FMLALLBT (indexed)FEAT_SSVE_FP8FMA || (FEAT_SVE2 && FEAT_FP8FMA)
10 FMLALLTB (indexed)FEAT_SSVE_FP8FMA || (FEAT_SVE2 && FEAT_FP8FMA)
11 FMLALLTT (indexed)FEAT_SSVE_FP8FMA || (FEAT_SVE2 && FEAT_FP8FMA)

SVE floating-point matrix multiply accumulate

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100opc1Zm111001ZnZda
Decode fields Instruction Details Feature
opc
00 FMMLA (widening, FP16 to FP32)FEAT_SVE_F16F32MM
01 BFMMLAFEAT_SVE && FEAT_BF16
10 FMMLA (non-widening) — 32-bit elementFEAT_F32MM
11 FMMLA (non-widening) — 64-bit elementFEAT_F64MM

SVE floating-point recursive reduction

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01100101size000opc001PgZnVd
Decode fields Instruction Details Feature
opc
000 FADDVFEAT_SVE || FEAT_SME
001 UNALLOCATED-
01x UNALLOCATED-
100 FMAXNMVFEAT_SVE || FEAT_SME
101 FMINNMVFEAT_SVE || FEAT_SME
110 FMAXVFEAT_SVE || FEAT_SME
111 FMINVFEAT_SVE || FEAT_SME

SVE floating-point arithmetic (unpredicated)

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01100101size0Zm000opcZnZd
Decode fields Instruction Details Feature
size opc
011 FTSMULFEAT_SVE
10x UNALLOCATED-
110 FRECPSFEAT_SVE || FEAT_SME
111 FRSQRTSFEAT_SVE || FEAT_SME
00 000 BFADD (unpredicated)FEAT_SVE_B16B16
00 001 BFSUB (unpredicated)FEAT_SVE_B16B16
00 010 BFMUL (vectors, unpredicated)FEAT_SVE_B16B16
!= 00 000 FADD (vectors, unpredicated)FEAT_SVE || FEAT_SME
!= 00 001 FSUB (vectors, unpredicated)FEAT_SVE || FEAT_SME
!= 00 010 FMUL (vectors, unpredicated)FEAT_SVE || FEAT_SME

SVE floating-point compare vectors

The encodings in this section are decoded from SVE encodings.

313029282726252423222120191817161514131211109876543210
01100101size0Zmop1o2PgZno3Pd
Decode fields Instruction Details Feature
op o2 o3
0 0 0 FCM<cc> (vectors) — Greater than or equalFEAT_SVE || FEAT_SME
0 0 1 FCM<cc> (vectors) — Greater thanFEAT_SVE || FEAT_SME
0 1 0 FCM<cc> (vectors) — EqualFEAT_SVE || FEAT_SME
0 1 1 FCM<cc> (vectors) — Not equalFEAT_SVE || FEAT_SME
1 0 0 FCM<cc> (vectors) — UnorderedFEAT_SVE || FEAT_SME
1 0 1 FAC<cc> — Greater than or equalFEAT_SVE || FEAT_SME
1 1 0 UNALLOCATED-
1 1 1 FAC<cc> — Greater thanFEAT_SVE || FEAT_SME

Data Processing -- Immediate

The encodings in this section are decoded from A64 instruction set encoding.

313029282726252423222120191817161514131211109876543210
op0100op1
Decode fieldsInstruction details
op0op1
11 111x Data-processing (1 source immediate)
00xx PC-rel. addressing
010x Add/subtract (immediate)
0110 Add/subtract (immediate, with tags)
0111 Min/max (immediate)
100x Logical (immediate)
101x Move wide (immediate)
110x Bitfield
!= 11 111x Extract

Data-processing (1 source immediate)

The encodings in this section are decoded from Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sf11100111opcimm16Rd
Decode fields Instruction Details Feature
sf opc Rd
0 UNALLOCATED-
1 0x != 11111 UNALLOCATED-
1 00 11111 AUTIASPPCFEAT_PAuth_LR
1 01 11111 AUTIBSPPCFEAT_PAuth_LR
1 1x UNALLOCATED-

PC-rel. addressing

The encodings in this section are decoded from Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
opimmlo10000immhiRd
Decode fields Instruction Details
op
0 ADR
1 ADRP

Add/subtract (immediate)

The encodings in this section are decoded from Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopS100010shimm12RnRd
Decode fields Instruction Details
sf op S
0 0 0 ADD (immediate) — 32-bit
0 0 1 ADDS (immediate) — 32-bit
0 1 0 SUB (immediate) — 32-bit
0 1 1 SUBS (immediate) — 32-bit
1 0 0 ADD (immediate) — 64-bit
1 0 1 ADDS (immediate) — 64-bit
1 1 0 SUB (immediate) — 64-bit
1 1 1 SUBS (immediate) — 64-bit

Add/subtract (immediate, with tags)

The encodings in this section are decoded from Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopS1000110imm6op3imm4RnRd
Decode fields Instruction Details Feature
sf op S
0 UNALLOCATED-
1 1 UNALLOCATED-
1 0 0 ADDGFEAT_MTE
1 1 0 SUBGFEAT_MTE

Min/max (immediate)

The encodings in this section are decoded from Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopS1000111opcimm8RnRd
Decode fields Instruction Details Feature
sf op S opc
0 0 01xx UNALLOCATED-
0 0 1xxx UNALLOCATED-
0 1 UNALLOCATED-
1 UNALLOCATED-
0 0 0 0000 SMAX (immediate) — 32-bitFEAT_CSSC
0 0 0 0001 UMAX (immediate) — 32-bitFEAT_CSSC
0 0 0 0010 SMIN (immediate) — 32-bitFEAT_CSSC
0 0 0 0011 UMIN (immediate) — 32-bitFEAT_CSSC
1 0 0 0000 SMAX (immediate) — 64-bitFEAT_CSSC
1 0 0 0001 UMAX (immediate) — 64-bitFEAT_CSSC
1 0 0 0010 SMIN (immediate) — 64-bitFEAT_CSSC
1 0 0 0011 UMIN (immediate) — 64-bitFEAT_CSSC

Logical (immediate)

The encodings in this section are decoded from Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopc100100NimmrimmsRnRd
Decode fields Instruction Details
sf opc N
0 1 UNALLOCATED
0 00 0 AND (immediate) — 32-bit
0 01 0 ORR (immediate) — 32-bit
0 10 0 EOR (immediate) — 32-bit
0 11 0 ANDS (immediate) — 32-bit
1 00 AND (immediate) — 64-bit
1 01 ORR (immediate) — 64-bit
1 10 EOR (immediate) — 64-bit
1 11 ANDS (immediate) — 64-bit

Move wide (immediate)

The encodings in this section are decoded from Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopc100101hwimm16Rd
Decode fields Instruction Details
sf opc hw
01 0x UNALLOCATED
0 1x UNALLOCATED
0 00 0x MOVN — 32-bit
0 10 0x MOVZ — 32-bit
0 11 0x MOVK — 32-bit
1 00 MOVN — 64-bit
1 01 1x UNALLOCATED
1 10 MOVZ — 64-bit
1 11 MOVK — 64-bit

Bitfield

The encodings in this section are decoded from Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopc100110NimmrimmsRnRd
Decode fields Instruction Details
sf opc N
0 1 UNALLOCATED
0 00 0 SBFM — 32-bit
0 01 0 BFM — 32-bit
0 10 0 UBFM — 32-bit
0 11 0 UNALLOCATED
1 0 UNALLOCATED
1 00 1 SBFM — 64-bit
1 01 1 BFM — 64-bit
1 10 1 UBFM — 64-bit
1 11 1 UNALLOCATED

Extract

The encodings in this section are decoded from Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sf!= 11100111No0RmimmsRnRd
op21

The following constraints also apply to this encoding: op21 != '11'

Decode fields Instruction Details
sf op21 N o0 imms
00 1 UNALLOCATED
01 UNALLOCATED
10 UNALLOCATED
0 00 0 0 0xxxxx EXTR — 32-bit
0 00 0 0 1xxxxx UNALLOCATED
0 00 1 0 UNALLOCATED
1 00 0 0 UNALLOCATED
1 00 1 0 EXTR — 64-bit

Branches, Exception Generating and System instructions

The encodings in this section are decoded from A64 instruction set encoding.

313029282726252423222120191817161514131211109876543210
op0101op1op2
Decode fieldsInstruction details
op0op1op2
010 00xxxxxxxxxxxx Conditional branch (immediate)
010 01xxxxxxxxxxxx Miscellaneous branch (immediate)
011 00xxxxxxxx1xxx Compare bytes/halfwords in registers and branch
01x 1xxxxxxxxxxxxx UNALLOCATED
110 00xxxxxxxxxxxx Exception generation
110 010000000x00xx UNALLOCATED
110 010000001000xx UNALLOCATED
110 01000000110000 UNALLOCATED
110 01000000110001 System instructions with register argument
110 01000000110010 11111 Hints
110 01000000110010 != 11111 UNALLOCATED
110 01000000110011 Barriers
110 01000001xx00xx UNALLOCATED
110 0100000xxx0100 PSTATE
110 0100000xxx0101 UNALLOCATED
110 0100000xxx011x UNALLOCATED
110 0100000xxx1xxx UNALLOCATED
110 0100100xxxxxxx System with result
110 0100x01xxxxxxx System instructions
110 0100x1xxxxxxxx System register move
110 0101x00xxxxxxx UNALLOCATED
110 0101x01xxxxxxx System pair instructions
110 0101x1xxxxxxxx System register pair move
110 011xxxxxxxxxxx UNALLOCATED
110 1xxxxxxxxxxxxx Unconditional branch (register)
111 00xxxxxxxx1xxx UNALLOCATED
111 1xxxxxxxxxxxxx UNALLOCATED
x00 Unconditional branch (immediate)
x01 0xxxxxxxxxxxxx Compare and branch (immediate)
x01 1xxxxxxxxxxxxx Test and branch (immediate)
x11 00xxxxxxxx00xx Compare registers and branch
x11 00xxxxxxxx01xx UNALLOCATED
x11 01xxxxxxxxx0xx Compare register with immediate and branch
x11 01xxxxxxxxx1xx UNALLOCATED

Conditional branch (immediate)

The encodings in this section are decoded from Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
01010100imm19o0cond
Decode fields Instruction Details Feature
o0
0 B.cond-
1 BC.condFEAT_HBC

Miscellaneous branch (immediate)

The encodings in this section are decoded from Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
01010101opcimm16op2
Decode fields Instruction Details Feature
opc op2
00x != 11111 UNALLOCATED-
000 11111 RETAASPPC, RETABSPPC — RETAASPPCFEAT_PAuth_LR
001 11111 RETAASPPC, RETABSPPC — RETABSPPCFEAT_PAuth_LR
01x UNALLOCATED-
1xx UNALLOCATED-

Compare bytes/halfwords in registers and branch

The encodings in this section are decoded from Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
01110100ccRm1Himm9Rt
Decode fields Instruction Details Feature
cc H
000 0 CBB<cc> — Greater thanFEAT_CMPBR
000 1 CBH<cc> — Greater thanFEAT_CMPBR
001 0 CBB<cc> — Greater than or equalFEAT_CMPBR
001 1 CBH<cc> — Greater than or equalFEAT_CMPBR
010 0 CBB<cc> — HigherFEAT_CMPBR
010 1 CBH<cc> — HigherFEAT_CMPBR
011 0 CBB<cc> — Higher or sameFEAT_CMPBR
011 1 CBH<cc> — Higher or sameFEAT_CMPBR
10x UNALLOCATED-
110 0 CBB<cc> — EqualFEAT_CMPBR
110 1 CBH<cc> — EqualFEAT_CMPBR
111 0 CBB<cc> — Not equalFEAT_CMPBR
111 1 CBH<cc> — Not equalFEAT_CMPBR

Exception generation

The encodings in this section are decoded from Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
11010100opcimm16op2LL
Decode fields Instruction Details Feature
opc op2 LL
!= 000 UNALLOCATED-
x11 000 != 00 UNALLOCATED-
000 000 00 UNALLOCATED-
000 000 01 SVC-
000 000 10 HVC-
000 000 11 SMC-
001 000 00 BRK-
001 000 != 00 UNALLOCATED-
010 000 00 HLT-
010 000 != 00 UNALLOCATED-
011 000 00 TCANCELFEAT_TME
1x0 000 UNALLOCATED-
1x1 000 00 UNALLOCATED-
101 000 01 DCPS1-
101 000 10 DCPS2-
101 000 11 DCPS3-

System instructions with register argument

The encodings in this section are decoded from Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
11010101000000110001CRmop2Rt
Decode fields Instruction Details Feature
CRm op2
0000 000 WFETFEAT_WFxT
0000 001 WFITFEAT_WFxT
0000 01x UNALLOCATED-
0000 1xx UNALLOCATED-
!= 0000 UNALLOCATED-

Hints

The encodings in this section are decoded from Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
11010101000000110010CRmop211111
Decode fields Instruction Details Feature
CRm op2
HINT-
0000 000 NOP-
0000 001 YIELD-
0000 010 WFE-
0000 011 WFI-
0000 100 SEV-
0000 101 SEVL-
0000 110 DGHFEAT_DGH
0000 111 XPACD, XPACI, XPACLRIFEAT_PAuth
0001 000 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA — PACIA1716FEAT_PAuth
0001 010 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB — PACIB1716FEAT_PAuth
0001 100 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA — AUTIA1716FEAT_PAuth
0001 110 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB — AUTIB1716FEAT_PAuth
0010 000 ESBFEAT_RAS
0010 001 PSBFEAT_SPE
0010 010 TSBFEAT_TRF
0010 011 GCSBFEAT_GCS
0010 100 CSDB-
0010 110 CLRBHBFEAT_CLRBHB
0011 000 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA — PACIAZFEAT_PAuth
0011 001 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA — PACIASPFEAT_PAuth
0011 010 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB — PACIBZFEAT_PAuth
0011 011 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB — PACIBSPFEAT_PAuth
0011 100 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA — AUTIAZFEAT_PAuth
0011 101 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA — AUTIASPFEAT_PAuth
0011 110 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB — AUTIBZFEAT_PAuth
0011 111 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB — AUTIBSPFEAT_PAuth
0100 xx0 BTIFEAT_BTI
0100 111 PACMFEAT_PAuth_LR
0101 000 CHKFEATFEAT_CHK
0110 00x STSHHFEAT_PCDPHINT

Barriers

The encodings in this section are decoded from Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
11010101000000110011CRmop2Rt
Decode fields Instruction Details Feature
CRm op2 Rt
!= 11111 UNALLOCATED-
010 11111 CLREX-
100 11111 DSB — Memory barrier-
101 11111 DMB-
110 11111 ISB-
111 11111 SBFEAT_SB
xx0x 00x 11111 UNALLOCATED-
xx1x 000 11111 UNALLOCATED-
xx10 001 11111 DSB — Memory nXS barrierFEAT_XS
xx11 001 11111 UNALLOCATED-
0000 011 11111 TCOMMITFEAT_TME
!= 0000 011 11111 UNALLOCATED-

PSTATE

The encodings in this section are decoded from Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101010100000op10100CRmop2Rt
Decode fields Instruction Details Feature
op1 op2 Rt
11111 MSR (immediate)-
!= 11111 UNALLOCATED-
000 000 11111 CFINVFEAT_FlagM
000 001 11111 XAFLAGFEAT_FlagM2
000 010 11111 AXFLAGFEAT_FlagM2

System with result

The encodings in this section are decoded from Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101010100100op1CRnCRmop2Rt
Decode fields Instruction Details Feature
op1 CRn CRm op2
011 0011 000x != 011 UNALLOCATED-
011 0011 0000 011 TSTARTFEAT_TME
011 0011 0001 011 TTESTFEAT_TME
011 0011 001x UNALLOCATED-
011 0011 01xx UNALLOCATED-
011 0011 1xxx UNALLOCATED-
011 != 0011 UNALLOCATED-
!= 011 UNALLOCATED-

System instructions

The encodings in this section are decoded from Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101010100L01op1CRnCRmop2Rt
Decode fields Instruction Details
L
0 SYS
1 SYSL

System register move

The encodings in this section are decoded from Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101010100L1o0op1CRnCRmop2Rt
Decode fields Instruction Details
L
0 MSR (register)
1 MRS

System pair instructions

The encodings in this section are decoded from Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101010101L01op1CRnCRmop2Rt
Decode fields Instruction Details Feature
L
0 SYSPFEAT_SYSINSTR128
1 UNALLOCATED-

System register pair move

The encodings in this section are decoded from Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101010101L1o0op1CRnCRmop2Rt
Decode fields Instruction Details Feature
L
0 MSRRFEAT_SYSREG128
1 MRRSFEAT_SYSREG128

Unconditional branch (register)

The encodings in this section are decoded from Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101011opcop2op3Rnop4
Decode fields Instruction Details Feature
opc op2 op3 Rn op4
11111 0001xx UNALLOCATED-
11111 001xxx UNALLOCATED-
11111 01xxxx UNALLOCATED-
11111 1xxxxx UNALLOCATED-
!= 11111 UNALLOCATED-
00x0 11111 000000 != 00000 UNALLOCATED-
00x0 11111 000001 UNALLOCATED-
000x 11111 00001x != 11111 UNALLOCATED-
0000 11111 000000 00000 BR-
0000 11111 000010 11111 BRAA, BRAAZ, BRAB, BRABZ — Key A, zero modifierFEAT_PAuth
0000 11111 000011 11111 BRAA, BRAAZ, BRAB, BRABZ — Key B, zero modifierFEAT_PAuth
0001 11111 000000 00000 BLR-
0001 11111 000000 != 00000 UNALLOCATED-
0001 11111 000001 UNALLOCATED-
0001 11111 000010 11111 BLRAA, BLRAAZ, BLRAB, BLRABZ — Key A, zero modifierFEAT_PAuth
0001 11111 000011 11111 BLRAA, BLRAAZ, BLRAB, BLRABZ — Key B, zero modifierFEAT_PAuth
0010 11111 000000 00000 RET-
0010 11111 00001x != 11111 UNALLOCATED-
0010 11111 000010 11111 11111 RETAA, RETAB — RETAAFEAT_PAuth
0010 11111 000010 11111 != 11111 RETAASPPCR, RETABSPPCR — RETAASPPCRFEAT_PAuth_LR
0010 11111 000011 11111 11111 RETAA, RETAB — RETABFEAT_PAuth
0010 11111 000011 11111 != 11111 RETAASPPCR, RETABSPPCR — RETABSPPCRFEAT_PAuth_LR
0011 11111 0000xx UNALLOCATED-
010x 11111 0000xx != 11111 UNALLOCATED-
010x 11111 000000 11111 != 00000 UNALLOCATED-
010x 11111 000001 11111 UNALLOCATED-
010x 11111 00001x 11111 xxxx0 UNALLOCATED-
0100 11111 000000 11111 00000 ERET-
0100 11111 00001x 11111 0xxx1 UNALLOCATED-
0100 11111 00001x 11111 10xx1 UNALLOCATED-
0100 11111 00001x 11111 110x1 UNALLOCATED-
0100 11111 00001x 11111 11101 UNALLOCATED-
0100 11111 000010 11111 11111 ERETAA, ERETAB — ERETAAFEAT_PAuth
0100 11111 000011 11111 11111 ERETAA, ERETAB — ERETABFEAT_PAuth
0101 11111 000000 11111 00000 DRPS-
0101 11111 00001x 11111 xxxx1 UNALLOCATED-
011x 11111 0000xx UNALLOCATED-
100x 11111 00000x UNALLOCATED-
1000 11111 000010 BRAA, BRAAZ, BRAB, BRABZ — Key A, register modifierFEAT_PAuth
1000 11111 000011 BRAA, BRAAZ, BRAB, BRABZ — Key B, register modifierFEAT_PAuth
1001 11111 000010 BLRAA, BLRAAZ, BLRAB, BLRABZ — Key A, register modifierFEAT_PAuth
1001 11111 000011 BLRAA, BLRAAZ, BLRAB, BLRABZ — Key B, register modifierFEAT_PAuth
101x 11111 0000xx UNALLOCATED-
11xx 11111 0000xx UNALLOCATED-

Unconditional branch (immediate)

The encodings in this section are decoded from Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
op00101imm26
Decode fields Instruction Details
op
0 B
1 BL

Compare and branch (immediate)

The encodings in this section are decoded from Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
sf011010opimm19Rt
Decode fields Instruction Details
sf op
0 0 CBZ — 32-bit
0 1 CBNZ — 32-bit
1 0 CBZ — 64-bit
1 1 CBNZ — 64-bit

Test and branch (immediate)

The encodings in this section are decoded from Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
b5011011opb40imm14Rt
Decode fields Instruction Details
op
0 TBZ
1 TBNZ

Compare registers and branch

The encodings in this section are decoded from Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
sf1110100ccRm00imm9Rt
Decode fields Instruction Details Feature
sf cc
10x UNALLOCATED-
0 000 CB<cc> (register) — 32-bit greater thanFEAT_CMPBR
0 001 CB<cc> (register) — 32-bit greater than or equalFEAT_CMPBR
0 010 CB<cc> (register) — 32-bit higherFEAT_CMPBR
0 011 CB<cc> (register) — 32-bit higher or sameFEAT_CMPBR
0 110 CB<cc> (register) — 32-bit equalFEAT_CMPBR
0 111 CB<cc> (register) — 32-bit not equalFEAT_CMPBR
1 000 CB<cc> (register) — 64-bit greater thanFEAT_CMPBR
1 001 CB<cc> (register) — 64-bit greater than or equalFEAT_CMPBR
1 010 CB<cc> (register) — 64-bit higherFEAT_CMPBR
1 011 CB<cc> (register) — 64-bit higher or sameFEAT_CMPBR
1 110 CB<cc> (register) — 64-bit equalFEAT_CMPBR
1 111 CB<cc> (register) — 64-bit not equalFEAT_CMPBR

Compare register with immediate and branch

The encodings in this section are decoded from Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
sf1110101ccimm60imm9Rt
Decode fields Instruction Details Feature
sf cc
10x UNALLOCATED-
0 000 CB<cc> (immediate) — 32-bit greater thanFEAT_CMPBR
0 001 CB<cc> (immediate) — 32-bit less thanFEAT_CMPBR
0 010 CB<cc> (immediate) — 32-bit higherFEAT_CMPBR
0 011 CB<cc> (immediate) — 32-bit lowerFEAT_CMPBR
0 110 CB<cc> (immediate) — 32-bit equalFEAT_CMPBR
0 111 CB<cc> (immediate) — 32-bit not equalFEAT_CMPBR
1 000 CB<cc> (immediate) — 64-bit greater thanFEAT_CMPBR
1 001 CB<cc> (immediate) — 64-bit less thanFEAT_CMPBR
1 010 CB<cc> (immediate) — 64-bit higherFEAT_CMPBR
1 011 CB<cc> (immediate) — 64-bit lowerFEAT_CMPBR
1 110 CB<cc> (immediate) — 64-bit equalFEAT_CMPBR
1 111 CB<cc> (immediate) — 64-bit not equalFEAT_CMPBR

Data Processing -- Register

The encodings in this section are decoded from A64 instruction set encoding.

313029282726252423222120191817161514131211109876543210
op0op1101op2op3
Decode fieldsInstruction details
op0op1op2op3
0 1 0110 Data-processing (2 source)
1 1 0110 Data-processing (1 source)
0 0xxx Logical (shifted register)
0 1xx0 Add/subtract (shifted register)
0 1xx1 Add/subtract (extended register)
1 0000 000000 Add/subtract (with carry)
1 0000 001xxx Add/subtract (checked pointer)
1 0000 011xxx UNALLOCATED
1 0000 100000 UNALLOCATED
1 0000 1x1xxx UNALLOCATED
1 0000 x00001 Rotate right into flags
1 0000 x0010x UNALLOCATED
1 0000 x10x0x UNALLOCATED
1 0000 xx0010 Evaluate into flags
1 0000 xx0011 UNALLOCATED
1 0000 xx011x UNALLOCATED
1 0010 xxxx0x Conditional compare (register)
1 0010 xxxx1x Conditional compare (immediate)
1 0100 Conditional select
1 0xx1 UNALLOCATED
1 1xxx Data-processing (3 source)

Data-processing (2 source)

The encodings in this section are decoded from Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sf0S11010110RmopcodeRnRd
Decode fields Instruction Details Feature
sf S opcode
1xxxxx UNALLOCATED-
0 00011x UNALLOCATED-
1 00001x UNALLOCATED-
1 0001xx UNALLOCATED-
1 001xxx UNALLOCATED-
1 01xxxx UNALLOCATED-
0 00000x UNALLOCATED-
0 0 0x11xx UNALLOCATED-
0 0 000010 UDIV — 32-bit-
0 0 000011 SDIV — 32-bit-
0 0 00010x UNALLOCATED-
0 0 001000 LSLV — 32-bit-
0 0 001001 LSRV — 32-bit-
0 0 001010 ASRV — 32-bit-
0 0 001011 RORV — 32-bit-
0 0 010x11 UNALLOCATED-
0 0 010000 CRC32B, CRC32H, CRC32W, CRC32X — CRC32BFEAT_CRC32
0 0 010001 CRC32B, CRC32H, CRC32W, CRC32X — CRC32HFEAT_CRC32
0 0 010010 CRC32B, CRC32H, CRC32W, CRC32X — CRC32WFEAT_CRC32
0 0 010100 CRC32CB, CRC32CH, CRC32CW, CRC32CX — CRC32CBFEAT_CRC32
0 0 010101 CRC32CB, CRC32CH, CRC32CW, CRC32CX — CRC32CHFEAT_CRC32
0 0 010110 CRC32CB, CRC32CH, CRC32CW, CRC32CX — CRC32CWFEAT_CRC32
0 0 011000 SMAX (register) — 32-bitFEAT_CSSC
0 0 011001 UMAX (register) — 32-bitFEAT_CSSC
0 0 011010 SMIN (register) — 32-bitFEAT_CSSC
0 0 011011 UMIN (register) — 32-bitFEAT_CSSC
1 000001 UNALLOCATED-
1 0 000000 SUBPFEAT_MTE
1 0 000010 UDIV — 64-bit-
1 0 000011 SDIV — 64-bit-
1 0 000100 IRGFEAT_MTE
1 0 000101 GMIFEAT_MTE
1 0 001000 LSLV — 64-bit-
1 0 001001 LSRV — 64-bit-
1 0 001010 ASRV — 64-bit-
1 0 001011 RORV — 64-bit-
1 0 001100 PACGAFEAT_PAuth
1 0 001101 UNALLOCATED-
1 0 00111x UNALLOCATED-
1 0 010xx0 UNALLOCATED-
1 0 010001 UNALLOCATED-
1 0 010011 CRC32B, CRC32H, CRC32W, CRC32X — CRC32XFEAT_CRC32
1 0 010101 UNALLOCATED-
1 0 010111 CRC32CB, CRC32CH, CRC32CW, CRC32CX — CRC32CXFEAT_CRC32
1 0 011000 SMAX (register) — 64-bitFEAT_CSSC
1 0 011001 UMAX (register) — 64-bitFEAT_CSSC
1 0 011010 SMIN (register) — 64-bitFEAT_CSSC
1 0 011011 UMIN (register) — 64-bitFEAT_CSSC
1 0 0111xx UNALLOCATED-
1 1 000000 SUBPSFEAT_MTE

Data-processing (1 source)

The encodings in this section are decoded from Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sf1S11010110opcode2opcodeRnRd
Decode fields Instruction Details Feature
sf S opcode2 opcode Rn Rd
0 00000 001001 UNALLOCATED-
0 00000 00101x UNALLOCATED-
0 00000 0011xx UNALLOCATED-
0 00000 01xxxx UNALLOCATED-
0 00000 1xxxxx UNALLOCATED-
0 0001x UNALLOCATED-
0 001xx UNALLOCATED-
0 01xxx UNALLOCATED-
0 1xxxx UNALLOCATED-
1 UNALLOCATED-
0 0 00000 000000 RBIT — 32-bit-
0 0 00000 000001 REV16 — 32-bit-
0 0 00000 000010 REV — 32-bit-
0 0 00000 000011 UNALLOCATED-
0 0 00000 000100 CLZ — 32-bit-
0 0 00000 000101 CLS — 32-bit-
0 0 00000 000110 CTZ — 32-bitFEAT_CSSC
0 0 00000 000111 CNT — 32-bitFEAT_CSSC
0 0 00000 001000 ABS — 32-bitFEAT_CSSC
0 0 00001 UNALLOCATED-
1 0 00000 000000 RBIT — 64-bit-
1 0 00000 000001 REV16 — 64-bit-
1 0 00000 000010 REV32-
1 0 00000 000011 REV — 64-bit-
1 0 00000 000100 CLZ — 64-bit-
1 0 00000 000101 CLS — 64-bit-
1 0 00000 000110 CTZ — 64-bitFEAT_CSSC
1 0 00000 000111 CNT — 64-bitFEAT_CSSC
1 0 00000 001000 ABS — 64-bitFEAT_CSSC
1 0 00001 000000 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA — PACIAFEAT_PAuth
1 0 00001 000001 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB — PACIBFEAT_PAuth
1 0 00001 000010 PACDA, PACDZA — PACDAFEAT_PAuth
1 0 00001 000011 PACDB, PACDZB — PACDBFEAT_PAuth
1 0 00001 000100 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA — AUTIAFEAT_PAuth
1 0 00001 000101 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB — AUTIBFEAT_PAuth
1 0 00001 000110 AUTDA, AUTDZA — AUTDAFEAT_PAuth
1 0 00001 000111 AUTDB, AUTDZB — AUTDBFEAT_PAuth
1 0 00001 001xxx != 11111 UNALLOCATED-
1 0 00001 001000 11111 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA — PACIZAFEAT_PAuth
1 0 00001 001001 11111 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB — PACIZBFEAT_PAuth
1 0 00001 001010 11111 PACDA, PACDZA — PACDZAFEAT_PAuth
1 0 00001 001011 11111 PACDB, PACDZB — PACDZBFEAT_PAuth
1 0 00001 001100 11111 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA — AUTIZAFEAT_PAuth
1 0 00001 001101 11111 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB — AUTIZBFEAT_PAuth
1 0 00001 001110 11111 AUTDA, AUTDZA — AUTDZAFEAT_PAuth
1 0 00001 001111 11111 AUTDB, AUTDZB — AUTDZBFEAT_PAuth
1 0 00001 01000x != 11111 UNALLOCATED-
1 0 00001 010000 11111 XPACD, XPACI, XPACLRI — XPACIFEAT_PAuth
1 0 00001 010001 11111 XPACD, XPACI, XPACLRI — XPACDFEAT_PAuth
1 0 00001 01001x UNALLOCATED-
1 0 00001 0101xx UNALLOCATED-
1 0 00001 011xxx UNALLOCATED-
1 0 00001 10xxxx != 11110 UNALLOCATED-
1 0 00001 1000xx != 11111 11110 UNALLOCATED-
1 0 00001 100000 11111 11110 PACNBIASPPCFEAT_PAuth_LR
1 0 00001 100001 11111 11110 PACNBIBSPPCFEAT_PAuth_LR
1 0 00001 100010 11111 11110 PACIA171615FEAT_PAuth_LR
1 0 00001 100011 11111 11110 PACIB171615FEAT_PAuth_LR
1 0 00001 100100 11110 AUTIASPPCRFEAT_PAuth_LR
1 0 00001 100101 11110 AUTIBSPPCRFEAT_PAuth_LR
1 0 00001 10011x 11110 UNALLOCATED-
1 0 00001 101xxx != 11111 11110 UNALLOCATED-
1 0 00001 101000 11111 11110 PACIASPPCFEAT_PAuth_LR
1 0 00001 101001 11111 11110 PACIBSPPCFEAT_PAuth_LR
1 0 00001 10101x 11111 11110 UNALLOCATED-
1 0 00001 10110x 11111 11110 UNALLOCATED-
1 0 00001 101110 11111 11110 AUTIA171615FEAT_PAuth_LR
1 0 00001 101111 11111 11110 AUTIB171615FEAT_PAuth_LR
1 0 00001 11xxxx UNALLOCATED-

Logical (shifted register)

The encodings in this section are decoded from Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopc01010shiftNRmimm6RnRd
Decode fields Instruction Details
sf opc N
0 00 0 AND (shifted register) — 32-bit
0 00 1 BIC (shifted register) — 32-bit
0 01 0 ORR (shifted register) — 32-bit
0 01 1 ORN (shifted register) — 32-bit
0 10 0 EOR (shifted register) — 32-bit
0 10 1 EON (shifted register) — 32-bit
0 11 0 ANDS (shifted register) — 32-bit
0 11 1 BICS (shifted register) — 32-bit
1 00 0 AND (shifted register) — 64-bit
1 00 1 BIC (shifted register) — 64-bit
1 01 0 ORR (shifted register) — 64-bit
1 01 1 ORN (shifted register) — 64-bit
1 10 0 EOR (shifted register) — 64-bit
1 10 1 EON (shifted register) — 64-bit
1 11 0 ANDS (shifted register) — 64-bit
1 11 1 BICS (shifted register) — 64-bit

Add/subtract (shifted register)

The encodings in this section are decoded from Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS01011shift0Rmimm6RnRd
Decode fields Instruction Details
sf op S
0 0 0 ADD (shifted register) — 32-bit
0 0 1 ADDS (shifted register) — 32-bit
0 1 0 SUB (shifted register) — 32-bit
0 1 1 SUBS (shifted register) — 32-bit
1 0 0 ADD (shifted register) — 64-bit
1 0 1 ADDS (shifted register) — 64-bit
1 1 0 SUB (shifted register) — 64-bit
1 1 1 SUBS (shifted register) — 64-bit

Add/subtract (extended register)

The encodings in this section are decoded from Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS01011opt1Rmoptionimm3RnRd
Decode fields Instruction Details
sf op S opt
!= 00 UNALLOCATED
0 0 0 00 ADD (extended register) — 32-bit
0 0 1 00 ADDS (extended register) — 32-bit
0 1 0 00 SUB (extended register) — 32-bit
0 1 1 00 SUBS (extended register) — 32-bit
1 0 0 00 ADD (extended register) — 64-bit
1 0 1 00 ADDS (extended register) — 64-bit
1 1 0 00 SUB (extended register) — 64-bit
1 1 1 00 SUBS (extended register) — 64-bit

Add/subtract (with carry)

The encodings in this section are decoded from Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010000Rm000000RnRd
Decode fields Instruction Details
sf op S
0 0 0 ADC — 32-bit
0 0 1 ADCS — 32-bit
0 1 0 SBC — 32-bit
0 1 1 SBCS — 32-bit
1 0 0 ADC — 64-bit
1 0 1 ADCS — 64-bit
1 1 0 SBC — 64-bit
1 1 1 SBCS — 64-bit

Add/subtract (checked pointer)

The encodings in this section are decoded from Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010000Rm001imm3RnRd
Decode fields Instruction Details Feature
sf op S
0 UNALLOCATED-
1 1 UNALLOCATED-
1 0 0 ADDPTFEAT_CPA
1 1 0 SUBPTFEAT_CPA

Rotate right into flags

The encodings in this section are decoded from Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010000imm600001Rno2mask
Decode fields Instruction Details Feature
sf op S o2
0 UNALLOCATED-
1 0 0 UNALLOCATED-
1 0 1 0 RMIFFEAT_FlagM
1 0 1 1 UNALLOCATED-
1 1 UNALLOCATED-

Evaluate into flags

The encodings in this section are decoded from Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010000opcode2sz0010Rno3mask
Decode fields Instruction Details Feature
sf op S opcode2 sz o3 mask
0 0 0 UNALLOCATED-
0 0 1 000000 0 != 1101 UNALLOCATED-
0 0 1 000000 1 UNALLOCATED-
0 0 1 000000 0 0 1101 SETF8, SETF16 — SETF8FEAT_FlagM
0 0 1 000000 1 0 1101 SETF8, SETF16 — SETF16FEAT_FlagM
0 0 1 != 000000 UNALLOCATED-
0 1 UNALLOCATED-
1 UNALLOCATED-

Conditional compare (register)

The encodings in this section are decoded from Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010010Rmcond0o2Rno3nzcv
Decode fields Instruction Details
sf op S o2 o3
0 UNALLOCATED
1 0 1 UNALLOCATED
1 1 UNALLOCATED
0 0 1 0 0 CCMN (register) — 32-bit
0 1 1 0 0 CCMP (register) — 32-bit
1 0 1 0 0 CCMN (register) — 64-bit
1 1 1 0 0 CCMP (register) — 64-bit

Conditional compare (immediate)

The encodings in this section are decoded from Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010010imm5cond1o2Rno3nzcv
Decode fields Instruction Details
sf op S o2 o3
0 UNALLOCATED
1 0 1 UNALLOCATED
1 1 UNALLOCATED
0 0 1 0 0 CCMN (immediate) — 32-bit
0 1 1 0 0 CCMP (immediate) — 32-bit
1 0 1 0 0 CCMN (immediate) — 64-bit
1 1 1 0 0 CCMP (immediate) — 64-bit

Conditional select

The encodings in this section are decoded from Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010100Rmcondop2RnRd
Decode fields Instruction Details
sf op S op2
0 1x UNALLOCATED
1 UNALLOCATED
0 0 0 00 CSEL — 32-bit
0 0 0 01 CSINC — 32-bit
0 1 0 00 CSINV — 32-bit
0 1 0 01 CSNEG — 32-bit
1 0 0 00 CSEL — 64-bit
1 0 0 01 CSINC — 64-bit
1 1 0 00 CSINV — 64-bit
1 1 0 01 CSNEG — 64-bit

Data-processing (3 source)

The encodings in this section are decoded from Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfop5411011op31Rmo0RaRnRd
Decode fields Instruction Details Feature
sf op54 op31 o0
00 100 UNALLOCATED-
!= 00 UNALLOCATED-
0 00 x01 UNALLOCATED-
0 00 x1x UNALLOCATED-
0 00 000 0 MADD — 32-bit-
0 00 000 1 MSUB — 32-bit-
1 00 x10 1 UNALLOCATED-
1 00 000 0 MADD — 64-bit-
1 00 000 1 MSUB — 64-bit-
1 00 001 0 SMADDL-
1 00 001 1 SMSUBL-
1 00 010 0 SMULH-
1 00 011 0 MADDPTFEAT_CPA
1 00 011 1 MSUBPTFEAT_CPA
1 00 101 0 UMADDL-
1 00 101 1 UMSUBL-
1 00 110 0 UMULH-
1 00 111 UNALLOCATED-

Data Processing -- Scalar Floating-Point and Advanced SIMD

The encodings in this section are decoded from A64 instruction set encoding.

313029282726252423222120191817161514131211109876543210
op0111op1op2op3
Decode fieldsInstruction detailsFeature
op0op1op2op3
00x0 0x x101 00xxxxx10 UNALLOCATED-
00x0 11 xxxxxxxx1 UNALLOCATED-
0100 0x x101 00xxxxx10 Cryptographic AES-
0101 0x x0xx xxx0xxx00 Cryptographic three-register SHA-
0101 0x x0xx xxx0xxx10 UNALLOCATED-
0101 0x x0xx xxx1xxxx0 UNALLOCATED-
0101 0x x101 00xxxxx10 Cryptographic two-register SHA-
0111 0x x0xx xxxxxxxx0 UNALLOCATED-
011x 0x x101 00xxxxx10 UNALLOCATED-
01x1 00 00xx xxx0xxxx1 Advanced SIMD scalar copy-
01x1 01 00xx xxx0xxxx1 UNALLOCATED-
01x1 0x 0111 00xxxxx10 UNALLOCATED-
01x1 0x 10xx xxx00xxx1 Advanced SIMD scalar three same FP16-
01x1 0x 10xx xxx01xxx1 UNALLOCATED-
01x1 0x 1111 00xxxxx10 Advanced SIMD scalar two-register miscellaneous FP16-
01x1 0x x0xx xxx1xxxx1 Advanced SIMD scalar three same extra-
01x1 0x x100 00xxxxx10 Advanced SIMD scalar two-register miscellaneous-
01x1 0x x110 00xxxxx10 Advanced SIMD scalar pairwise-
01x1 0x x1xx 01xxxxx10 UNALLOCATED-
01x1 0x x1xx 1xxxxxx10 UNALLOCATED-
01x1 0x x1xx xxxxxxx00 Advanced SIMD scalar three different-
01x1 0x x1xx xxxxxxxx1 Advanced SIMD scalar three same-
01x1 10 xxxxxxxx1 Advanced SIMD scalar shift by immediate-
01x1 1x xxxxxxxx0 Advanced SIMD scalar x indexed element-
01xx 11 xxxxxxxx1 UNALLOCATED-
0x00 0x x0xx xxx0xxx00 Advanced SIMD table lookup-
0x00 0x x0xx xxx0xxx10 Advanced SIMD permute-
0x10 0x x0xx xxx0xxxx0 Advanced SIMD extract-
0xx0 00 00xx xxx0xxxx1 Advanced SIMD copy-
0xx0 01 00xx xxx0xxxx1 UNALLOCATED-
0xx0 0x 0111 00xxxxx10 UNALLOCATED-
0xx0 0x 10xx xxx00xxx1 Advanced SIMD three same (FP16)-
0xx0 0x 10xx xxx01xxx1 UNALLOCATED-
0xx0 0x 1111 00xxxxx10 Advanced SIMD two-register miscellaneous (FP16)-
0xx0 0x x0xx xxx1xxxx0 UNALLOCATED-
0xx0 0x x0xx xxx1xxxx1 Advanced SIMD three-register extension-
0xx0 0x x100 00xxxxx10 Advanced SIMD two-register miscellaneous-
0xx0 0x x110 00xxxxx10 Advanced SIMD across lanes-
0xx0 0x x1xx 01xxxxx10 UNALLOCATED-
0xx0 0x x1xx 1xxxxxx10 UNALLOCATED-
0xx0 0x x1xx xxxxxxx00 Advanced SIMD three different-
0xx0 0x x1xx xxxxxxxx1 Advanced SIMD three same-
0xx0 10 0000 xxxxxxxx1 Advanced SIMD modified immediate-
0xx0 10 != 0000 xxxxxxxx1 Advanced SIMD shift by immediate-
0xx0 1x xxxxxxxx0 Advanced SIMD vector x indexed element-
10x0 UNALLOCATED-
1100 00 0xxx xxx1xxxxx UNALLOCATED-
1100 00 10xx xxx10xxxx Cryptographic three-register, imm2-
1100 00 10xx xxx11xxxx UNALLOCATED-
1100 00 11xx xxx1x00xx Cryptographic three-register SHA 512-
1100 00 11xx xxx1x01xx UNALLOCATED-
1100 00 11xx xxx1x1xxx UNALLOCATED-
1100 00 xxx0xxxxx Cryptographic four-register-
1100 01 00xx XARFEAT_SHA3
1100 01 1000 0000xxxxx UNALLOCATED-
1100 01 1000 0001000xx Cryptographic two-register SHA 512-
1100 01 1000 0001100xx UNALLOCATED-
1100 01 1000 0001x01xx UNALLOCATED-
1100 01 1000 0001x1xxx UNALLOCATED-
1100 01 1000 001xxxxxx UNALLOCATED-
1100 01 1000 01xxxxxxx UNALLOCATED-
1100 01 1000 1xxxxxxxx UNALLOCATED-
1100 01 1001 UNALLOCATED-
1100 01 101x UNALLOCATED-
1100 01 x1xx UNALLOCATED-
1100 1x UNALLOCATED-
1110 UNALLOCATED-
11x1 UNALLOCATED-
x0x1 0x x0xx Conversion between floating-point and fixed-point-
x0x1 0x x1xx xxx000000 Conversion between floating-point and integer-
x0x1 0x x1xx xxx100000 UNALLOCATED-
x0x1 0x x1xx xxxx10000 Floating-point data-processing (1 source)-
x0x1 0x x1xx xxxxx1000 Floating-point compare-
x0x1 0x x1xx xxxxxx100 Floating-point immediate-
x0x1 0x x1xx xxxxxxx01 Floating-point conditional compare-
x0x1 0x x1xx xxxxxxx10 Floating-point data-processing (2 source)-
x0x1 0x x1xx xxxxxxx11 Floating-point conditional select-
x0x1 1x Floating-point data-processing (3 source)-

Cryptographic AES

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01001110size10100opcode10RnRd
Decode fields Instruction Details Feature
size opcode
00 000xx UNALLOCATED-
00 00100 AESEFEAT_AES
00 00101 AESDFEAT_AES
00 00110 AESMCFEAT_AES
00 00111 AESIMCFEAT_AES
00 01xxx UNALLOCATED-
00 1xxxx UNALLOCATED-
!= 00 UNALLOCATED-

Cryptographic three-register SHA

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01011110size0Rm0opcode00RnRd
Decode fields Instruction Details Feature
size opcode
00 000 SHA1CFEAT_SHA1
00 001 SHA1PFEAT_SHA1
00 010 SHA1MFEAT_SHA1
00 011 SHA1SU0FEAT_SHA1
00 100 SHA256HFEAT_SHA256
00 101 SHA256H2FEAT_SHA256
00 110 SHA256SU1FEAT_SHA256
00 111 UNALLOCATED-
!= 00 UNALLOCATED-

Cryptographic two-register SHA

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01011110size10100opcode10RnRd
Decode fields Instruction Details Feature
size opcode
00 00000 SHA1HFEAT_SHA1
00 00001 SHA1SU1FEAT_SHA1
00 00010 SHA256SU0FEAT_SHA256
00 00011 UNALLOCATED-
00 001xx UNALLOCATED-
00 01xxx UNALLOCATED-
00 1xxxx UNALLOCATED-
!= 00 UNALLOCATED-

Advanced SIMD scalar copy

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01op11110000imm50imm41RnRd
Decode fields Instruction Details Feature
op imm4
0 0000 DUP (element)FEAT_AdvSIMD
0 != 0000 UNALLOCATED-
1 UNALLOCATED-

Advanced SIMD scalar three same FP16

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110a10Rm00opcode1RnRd
Decode fields Instruction Details Feature
U a opcode
00x UNALLOCATED-
0 010 UNALLOCATED-
0 101 UNALLOCATED-
0 0 011 FMULXFEAT_AdvSIMD && FEAT_FP16
0 0 100 FCMEQ (register)FEAT_AdvSIMD && FEAT_FP16
0 0 110 UNALLOCATED-
0 0 111 FRECPSFEAT_AdvSIMD && FEAT_FP16
0 1 x10 UNALLOCATED-
0 1 011 UNALLOCATED-
0 1 100 UNALLOCATED-
0 1 111 FRSQRTSFEAT_AdvSIMD && FEAT_FP16
1 011 UNALLOCATED-
1 11x UNALLOCATED-
1 0 100 FCMGE (register)FEAT_AdvSIMD && FEAT_FP16
1 0 101 FACGEFEAT_AdvSIMD && FEAT_FP16
1 1 010 FABDFEAT_AdvSIMD && FEAT_FP16
1 1 100 FCMGT (register)FEAT_AdvSIMD && FEAT_FP16
1 1 101 FACGTFEAT_AdvSIMD && FEAT_FP16

Advanced SIMD scalar two-register miscellaneous FP16

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110a111100opcode10RnRd
Decode fields Instruction Details Feature
U a opcode
x0xxx UNALLOCATED-
1100x UNALLOCATED-
0 01xxx UNALLOCATED-
1 010xx UNALLOCATED-
1 11100 UNALLOCATED-
0 0 11010 FCVTNS (vector)FEAT_AdvSIMD && FEAT_FP16
0 0 11011 FCVTMS (vector)FEAT_AdvSIMD && FEAT_FP16
0 0 11100 FCVTAS (vector)FEAT_AdvSIMD && FEAT_FP16
0 0 11101 SCVTF (vector, integer)FEAT_AdvSIMD && FEAT_FP16
0 0 1111x UNALLOCATED-
0 1 01100 FCMGT (zero)FEAT_AdvSIMD && FEAT_FP16
0 1 01101 FCMEQ (zero)FEAT_AdvSIMD && FEAT_FP16
0 1 01110 FCMLT (zero)FEAT_AdvSIMD && FEAT_FP16
0 1 01111 UNALLOCATED-
0 1 11010 FCVTPS (vector)FEAT_AdvSIMD && FEAT_FP16
0 1 11011 FCVTZS (vector, integer)FEAT_AdvSIMD && FEAT_FP16
0 1 11101 FRECPEFEAT_AdvSIMD && FEAT_FP16
0 1 11110 UNALLOCATED-
0 1 11111 FRECPXFEAT_AdvSIMD && FEAT_FP16
1 1111x UNALLOCATED-
1 0 11010 FCVTNU (vector)FEAT_AdvSIMD && FEAT_FP16
1 0 11011 FCVTMU (vector)FEAT_AdvSIMD && FEAT_FP16
1 0 11100 FCVTAU (vector)FEAT_AdvSIMD && FEAT_FP16
1 0 11101 UCVTF (vector, integer)FEAT_AdvSIMD && FEAT_FP16
1 1 01100 FCMGE (zero)FEAT_AdvSIMD && FEAT_FP16
1 1 01101 FCMLE (zero)FEAT_AdvSIMD && FEAT_FP16
1 1 0111x UNALLOCATED-
1 1 11010 FCVTPU (vector)FEAT_AdvSIMD && FEAT_FP16
1 1 11011 FCVTZU (vector, integer)FEAT_AdvSIMD && FEAT_FP16
1 1 11101 FRSQRTEFEAT_AdvSIMD && FEAT_FP16

Advanced SIMD scalar three same extra

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110size0Rm1opcode1RnRd
Decode fields Instruction Details Feature
U opcode
0 UNALLOCATED-
1 0000 SQRDMLAH (vector)FEAT_RDM
1 0001 SQRDMLSH (vector)FEAT_RDM
1 001x UNALLOCATED-
1 01xx UNALLOCATED-
1 1xxx UNALLOCATED-

Advanced SIMD scalar two-register miscellaneous

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110size10000opcode10RnRd
Decode fields Instruction Details Feature
U size opcode
00x0x UNALLOCATED-
1x000 UNALLOCATED-
10xx1 UNALLOCATED-
11001 UNALLOCATED-
0x 01xxx UNALLOCATED-
0x 1111x UNALLOCATED-
1x 01111 UNALLOCATED-
1x 11100 UNALLOCATED-
10 010x1 UNALLOCATED-
10 01000 UNALLOCATED-
0 x0x10 UNALLOCATED-
0 00011 SUQADDFEAT_AdvSIMD
0 00111 SQABSFEAT_AdvSIMD
0 10100 SQXTN, SQXTN2FEAT_AdvSIMD
0 0x 11010 FCVTNS (vector)FEAT_AdvSIMD
0 0x 11011 FCVTMS (vector)FEAT_AdvSIMD
0 0x 11100 FCVTAS (vector)FEAT_AdvSIMD
0 0x 11101 SCVTF (vector, integer)FEAT_AdvSIMD
0 1x 01100 FCMGT (zero)FEAT_AdvSIMD
0 1x 01101 FCMEQ (zero)FEAT_AdvSIMD
0 1x 01110 FCMLT (zero)FEAT_AdvSIMD
0 1x 11010 FCVTPS (vector)FEAT_AdvSIMD
0 1x 11011 FCVTZS (vector, integer)FEAT_AdvSIMD
0 1x 11101 FRECPEFEAT_AdvSIMD
0 1x 11110 UNALLOCATED-
0 1x 11111 FRECPXFEAT_AdvSIMD
0 10 01010 UNALLOCATED-
0 11 01000 CMGT (zero)FEAT_AdvSIMD
0 11 01001 CMEQ (zero)FEAT_AdvSIMD
0 11 01010 CMLT (zero)FEAT_AdvSIMD
0 11 01011 ABSFEAT_AdvSIMD
1 00x10 UNALLOCATED-
1 00011 USQADDFEAT_AdvSIMD
1 00111 SQNEGFEAT_AdvSIMD
1 10010 SQXTUN, SQXTUN2FEAT_AdvSIMD
1 10100 UQXTN, UQXTN2FEAT_AdvSIMD
1 0x 11010 FCVTNU (vector)FEAT_AdvSIMD
1 0x 11011 FCVTMU (vector)FEAT_AdvSIMD
1 0x 11100 FCVTAU (vector)FEAT_AdvSIMD
1 0x 11101 UCVTF (vector, integer)FEAT_AdvSIMD
1 00 10110 UNALLOCATED-
1 01 10110 FCVTXN, FCVTXN2FEAT_AdvSIMD
1 1x 01x10 UNALLOCATED-
1 1x 01100 FCMGE (zero)FEAT_AdvSIMD
1 1x 01101 FCMLE (zero)FEAT_AdvSIMD
1 1x 1x110 UNALLOCATED-
1 1x 11010 FCVTPU (vector)FEAT_AdvSIMD
1 1x 11011 FCVTZU (vector, integer)FEAT_AdvSIMD
1 1x 11101 FRSQRTEFEAT_AdvSIMD
1 1x 11111 UNALLOCATED-
1 11 01000 CMGE (zero)FEAT_AdvSIMD
1 11 01001 CMLE (zero)FEAT_AdvSIMD
1 11 01011 NEG (vector)FEAT_AdvSIMD

Advanced SIMD scalar pairwise

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110size11000opcode10RnRd
Decode fields Instruction Details Feature
U size opcode
x0xxx UNALLOCATED-
01110 UNALLOCATED-
111xx UNALLOCATED-
10 01101 UNALLOCATED-
0 x1 011x1 UNALLOCATED-
0 x1 01100 UNALLOCATED-
0 00 01100 FMAXNMP (scalar) — Half-precisionFEAT_AdvSIMD && FEAT_FP16
0 00 01101 FADDP (scalar) — Half-precisionFEAT_AdvSIMD && FEAT_FP16
0 00 01111 FMAXP (scalar) — Half-precisionFEAT_AdvSIMD && FEAT_FP16
0 10 01100 FMINNMP (scalar) — Half-precisionFEAT_AdvSIMD && FEAT_FP16
0 10 01111 FMINP (scalar) — Half-precisionFEAT_AdvSIMD && FEAT_FP16
0 11 x100x UNALLOCATED-
0 11 x1010 UNALLOCATED-
0 11 01011 UNALLOCATED-
0 11 11011 ADDP (scalar)FEAT_AdvSIMD
0 != 11 x10xx UNALLOCATED-
1 x10xx UNALLOCATED-
1 0x 01100 FMAXNMP (scalar) — Single-precision and double-precisionFEAT_AdvSIMD
1 0x 01101 FADDP (scalar) — Single-precision and double-precisionFEAT_AdvSIMD
1 0x 01111 FMAXP (scalar) — Single-precision and double-precisionFEAT_AdvSIMD
1 1x 01100 FMINNMP (scalar) — Single-precision and double-precisionFEAT_AdvSIMD
1 1x 01111 FMINP (scalar) — Single-precision and double-precisionFEAT_AdvSIMD
1 11 01101 UNALLOCATED-

Advanced SIMD scalar three different

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110size1Rmopcode00RnRd
Decode fields Instruction Details Feature
U opcode
0 0xxx UNALLOCATED-
0 1xx0 UNALLOCATED-
0 1001 SQDMLAL, SQDMLAL2 (vector)FEAT_AdvSIMD
0 1011 SQDMLSL, SQDMLSL2 (vector)FEAT_AdvSIMD
0 1101 SQDMULL, SQDMULL2 (vector)FEAT_AdvSIMD
0 1111 UNALLOCATED-
1 UNALLOCATED-

Advanced SIMD scalar three same

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110size1Rmopcode1RnRd
Decode fields Instruction Details Feature
U size opcode
x0011 UNALLOCATED-
011x1 UNALLOCATED-
11001 UNALLOCATED-
11110 UNALLOCATED-
x0 0x1x0 UNALLOCATED-
x1 00100 UNALLOCATED-
x1 011x0 UNALLOCATED-
0x xx0x0 UNALLOCATED-
0x 10x01 UNALLOCATED-
01 00110 UNALLOCATED-
1x 10010 UNALLOCATED-
1x 11000 UNALLOCATED-
10 0x0x0 UNALLOCATED-
10 10x0x UNALLOCATED-
11 00000 UNALLOCATED-
11 00010 UNALLOCATED-
11 10101 UNALLOCATED-
!= 10 10100 UNALLOCATED-
!= 11 00111 UNALLOCATED-
0 00001 SQADDFEAT_AdvSIMD
0 00101 SQSUBFEAT_AdvSIMD
0 01001 SQSHL (register)FEAT_AdvSIMD
0 01011 SQRSHLFEAT_AdvSIMD
0 10110 SQDMULH (vector)FEAT_AdvSIMD
0 10111 UNALLOCATED-
0 11101 UNALLOCATED-
0 0x 11011 FMULXFEAT_AdvSIMD
0 0x 11100 FCMEQ (register)FEAT_AdvSIMD
0 0x 11111 FRECPSFEAT_AdvSIMD
0 1x 11010 UNALLOCATED-
0 1x 11011 UNALLOCATED-
0 1x 11100 UNALLOCATED-
0 1x 11111 FRSQRTSFEAT_AdvSIMD
0 11 00110 CMGT (register)FEAT_AdvSIMD
0 11 00111 CMGE (register)FEAT_AdvSIMD
0 11 01000 SSHLFEAT_AdvSIMD
0 11 01010 SRSHLFEAT_AdvSIMD
0 11 10000 ADD (vector)FEAT_AdvSIMD
0 11 10001 CMTSTFEAT_AdvSIMD
1 00001 UQADDFEAT_AdvSIMD
1 00101 UQSUBFEAT_AdvSIMD
1 01001 UQSHL (register)FEAT_AdvSIMD
1 01011 UQRSHLFEAT_AdvSIMD
1 1x111 UNALLOCATED-
1 10110 SQRDMULH (vector)FEAT_AdvSIMD
1 11011 UNALLOCATED-
1 0x 11100 FCMGE (register)FEAT_AdvSIMD
1 0x 11101 FACGEFEAT_AdvSIMD
1 1x 11010 FABDFEAT_AdvSIMD
1 1x 11100 FCMGT (register)FEAT_AdvSIMD
1 1x 11101 FACGTFEAT_AdvSIMD
1 11 00110 CMHI (register)FEAT_AdvSIMD
1 11 00111 CMHS (register)FEAT_AdvSIMD
1 11 01000 USHLFEAT_AdvSIMD
1 11 01010 URSHLFEAT_AdvSIMD
1 11 10000 SUB (vector)FEAT_AdvSIMD
1 11 10001 CMEQ (register)FEAT_AdvSIMD

Advanced SIMD scalar shift by immediate

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U111110immhimmbopcode1RnRd
Decode fields Instruction Details Feature
U immh opcode
0xxx1 UNALLOCATED-
101xx UNALLOCATED-
11101 UNALLOCATED-
0xxx x10x0 UNALLOCATED-
0xxx 00xx0 UNALLOCATED-
0xxx 110x1 UNALLOCATED-
0000 x1110 UNALLOCATED-
0000 1001x UNALLOCATED-
0000 11100 UNALLOCATED-
0000 11111 UNALLOCATED-
1xxx 110xx UNALLOCATED-
!= 0000 11110 UNALLOCATED-
0 01100 UNALLOCATED-
0 1000x UNALLOCATED-
0 1xxx 00000 SSHRFEAT_AdvSIMD
0 1xxx 00010 SSRAFEAT_AdvSIMD
0 1xxx 00100 SRSHRFEAT_AdvSIMD
0 1xxx 00110 SRSRAFEAT_AdvSIMD
0 1xxx 01000 UNALLOCATED-
0 1xxx 01010 SHLFEAT_AdvSIMD
0 != 0000 01110 SQSHL (immediate)FEAT_AdvSIMD
0 != 0000 10010 SQSHRN, SQSHRN2FEAT_AdvSIMD
0 != 0000 10011 SQRSHRN, SQRSHRN2FEAT_AdvSIMD
0 != 0000 11100 SCVTF (vector, fixed-point)FEAT_AdvSIMD
0 != 0000 11111 FCVTZS (vector, fixed-point)FEAT_AdvSIMD
1 0000 01100 UNALLOCATED-
1 0000 1000x UNALLOCATED-
1 1xxx 00000 USHRFEAT_AdvSIMD
1 1xxx 00010 USRAFEAT_AdvSIMD
1 1xxx 00100 URSHRFEAT_AdvSIMD
1 1xxx 00110 URSRAFEAT_AdvSIMD
1 1xxx 01000 SRIFEAT_AdvSIMD
1 1xxx 01010 SLIFEAT_AdvSIMD
1 != 0000 01100 SQSHLUFEAT_AdvSIMD
1 != 0000 01110 UQSHL (immediate)FEAT_AdvSIMD
1 != 0000 10000 SQSHRUN, SQSHRUN2FEAT_AdvSIMD
1 != 0000 10001 SQRSHRUN, SQRSHRUN2FEAT_AdvSIMD
1 != 0000 10010 UQSHRN, UQSHRN2FEAT_AdvSIMD
1 != 0000 10011 UQRSHRN, UQRSHRN2FEAT_AdvSIMD
1 != 0000 11100 UCVTF (vector, fixed-point)FEAT_AdvSIMD
1 != 0000 11111 FCVTZU (vector, fixed-point)FEAT_AdvSIMD

Advanced SIMD scalar x indexed element

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11111sizeLMRmopcodeH0RnRd
Decode fields Instruction Details Feature
U size opcode
01 1001 UNALLOCATED-
0 0xx0 UNALLOCATED-
0 0011 SQDMLAL, SQDMLAL2 (by element)FEAT_AdvSIMD
0 0111 SQDMLSL, SQDMLSL2 (by element)FEAT_AdvSIMD
0 10x0 UNALLOCATED-
0 1011 SQDMULL, SQDMULL2 (by element)FEAT_AdvSIMD
0 1100 SQDMULH (by element)FEAT_AdvSIMD
0 1101 SQRDMULH (by element)FEAT_AdvSIMD
0 111x UNALLOCATED-
0 00 0001 FMLA (by element) — Scalar, half-precisionFEAT_AdvSIMD && FEAT_FP16
0 00 0101 FMLS (by element) — Scalar, half-precisionFEAT_AdvSIMD && FEAT_FP16
0 00 1001 FMUL (by element) — Scalar, half-precisionFEAT_AdvSIMD && FEAT_FP16
0 01 0x01 UNALLOCATED-
0 1x 0001 FMLA (by element) — Scalar, single-precision and double-precisionFEAT_AdvSIMD
0 1x 0101 FMLS (by element) — Scalar, single-precision and double-precisionFEAT_AdvSIMD
0 1x 1001 FMUL (by element) — Scalar, single-precision and double-precisionFEAT_AdvSIMD
1 0xxx UNALLOCATED-
1 1xx0 UNALLOCATED-
1 1011 UNALLOCATED-
1 1101 SQRDMLAH (by element)FEAT_RDM
1 1111 SQRDMLSH (by element)FEAT_RDM
1 00 1001 FMULX (by element) — Scalar, half-precisionFEAT_AdvSIMD && FEAT_FP16
1 1x 1001 FMULX (by element) — Scalar, single-precision and double-precisionFEAT_AdvSIMD

Advanced SIMD table lookup

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0Q001110op20Rm0lenop00RnRd
Decode fields Instruction Details Feature
Q op2 len op
00 00 0 TBL — Single register tableFEAT_AdvSIMD
00 00 1 TBX — Single register tableFEAT_AdvSIMD
00 01 0 TBL — Two register tableFEAT_AdvSIMD
00 01 1 TBX — Two register tableFEAT_AdvSIMD
00 10 0 TBL — Three register tableFEAT_AdvSIMD
00 10 1 TBX — Three register tableFEAT_AdvSIMD
00 11 0 TBL — Four register tableFEAT_AdvSIMD
00 11 1 TBX — Four register tableFEAT_AdvSIMD
0 != 00 UNALLOCATED-
1 01 1 LUTI4 — HalfwordFEAT_AdvSIMD && FEAT_LUT
1 01 x0 0 UNALLOCATED-
1 01 x1 0 LUTI4 — ByteFEAT_AdvSIMD && FEAT_LUT
1 10 0 UNALLOCATED-
1 10 1 LUTI2 — ByteFEAT_AdvSIMD && FEAT_LUT
1 11 LUTI2 — HalfwordFEAT_AdvSIMD && FEAT_LUT

Advanced SIMD permute

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0Q001110size0Rm0opcode10RnRd
Decode fields Instruction Details Feature
opcode
x00 UNALLOCATED-
001 UZP1FEAT_AdvSIMD
010 TRN1FEAT_AdvSIMD
011 ZIP1FEAT_AdvSIMD
101 UZP2FEAT_AdvSIMD
110 TRN2FEAT_AdvSIMD
111 ZIP2FEAT_AdvSIMD

Advanced SIMD extract

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0Q101110op20Rm0imm40RnRd
Decode fields Instruction Details Feature
op2
00 EXTFEAT_AdvSIMD
!= 00 UNALLOCATED-

Advanced SIMD copy

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0Qop01110000imm50imm41RnRd
Decode fields Instruction Details Feature
Q op imm5 imm4
0 0000 DUP (element)FEAT_AdvSIMD
0 0001 DUP (general)FEAT_AdvSIMD
0 01x0 UNALLOCATED-
0 1xxx UNALLOCATED-
0 0 001x UNALLOCATED-
0 0 0101 SMOV — 32-bitFEAT_AdvSIMD
0 0 0111 UMOV — 32-bitFEAT_AdvSIMD
0 1 UNALLOCATED-
1 0 0010 UNALLOCATED-
1 0 0011 INS (general)FEAT_AdvSIMD
1 0 0101 SMOV — 64-bitFEAT_AdvSIMD
1 0 x0xxx 0111 UNALLOCATED-
1 0 x1000 0111 UMOV — 64-bitFEAT_AdvSIMD
1 0 x1001 0111 UNALLOCATED-
1 0 x101x 0111 UNALLOCATED-
1 0 x11xx 0111 UNALLOCATED-
1 1 INS (element)FEAT_AdvSIMD

Advanced SIMD three same (FP16)

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110a10Rm00opcode1RnRd
Decode fields Instruction Details Feature
U a opcode
0 0 000 FMAXNM (vector)FEAT_AdvSIMD && FEAT_FP16
0 0 001 FMLA (vector)FEAT_AdvSIMD && FEAT_FP16
0 0 010 FADD (vector)FEAT_AdvSIMD && FEAT_FP16
0 0 011 FMULXFEAT_AdvSIMD && FEAT_FP16
0 0 100 FCMEQ (register)FEAT_AdvSIMD && FEAT_FP16
0 0 101 UNALLOCATED-
0 0 110 FMAX (vector)FEAT_AdvSIMD && FEAT_FP16
0 0 111 FRECPSFEAT_AdvSIMD && FEAT_FP16
0 1 000 FMINNM (vector)FEAT_AdvSIMD && FEAT_FP16
0 1 001 FMLS (vector)FEAT_AdvSIMD && FEAT_FP16
0 1 010 FSUB (vector)FEAT_AdvSIMD && FEAT_FP16
0 1 011 FAMAXFEAT_AdvSIMD && FEAT_FAMINMAX
0 1 10x UNALLOCATED-
0 1 110 FMIN (vector)FEAT_AdvSIMD && FEAT_FP16
0 1 111 FRSQRTSFEAT_AdvSIMD && FEAT_FP16
1 001 UNALLOCATED-
1 0 000 FMAXNMP (vector)FEAT_AdvSIMD && FEAT_FP16
1 0 010 FADDP (vector)FEAT_AdvSIMD && FEAT_FP16
1 0 011 FMUL (vector)FEAT_AdvSIMD && FEAT_FP16
1 0 100 FCMGE (register)FEAT_AdvSIMD && FEAT_FP16
1 0 101 FACGEFEAT_AdvSIMD && FEAT_FP16
1 0 110 FMAXP (vector)FEAT_AdvSIMD && FEAT_FP16
1 0 111 FDIV (vector)FEAT_AdvSIMD && FEAT_FP16
1 1 000 FMINNMP (vector)FEAT_AdvSIMD && FEAT_FP16
1 1 010 FABDFEAT_AdvSIMD && FEAT_FP16
1 1 011 FAMINFEAT_AdvSIMD && FEAT_FAMINMAX
1 1 100 FCMGT (register)FEAT_AdvSIMD && FEAT_FP16
1 1 101 FACGTFEAT_AdvSIMD && FEAT_FP16
1 1 110 FMINP (vector)FEAT_AdvSIMD && FEAT_FP16
1 1 111 FSCALEFEAT_FP8

Advanced SIMD two-register miscellaneous (FP16)

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110a111100opcode10RnRd
Decode fields Instruction Details Feature
U a opcode
x0xxx UNALLOCATED-
0 01xxx UNALLOCATED-
0 1111x UNALLOCATED-
1 010xx UNALLOCATED-
1 11100 UNALLOCATED-
0 0 11000 FRINTN (vector)FEAT_AdvSIMD && FEAT_FP16
0 0 11001 FRINTM (vector)FEAT_AdvSIMD && FEAT_FP16
0 0 11010 FCVTNS (vector)FEAT_AdvSIMD && FEAT_FP16
0 0 11011 FCVTMS (vector)FEAT_AdvSIMD && FEAT_FP16
0 0 11100 FCVTAS (vector)FEAT_AdvSIMD && FEAT_FP16
0 0 11101 SCVTF (vector, integer)FEAT_AdvSIMD && FEAT_FP16
0 1 01100 FCMGT (zero)FEAT_AdvSIMD && FEAT_FP16
0 1 01101 FCMEQ (zero)FEAT_AdvSIMD && FEAT_FP16
0 1 01110 FCMLT (zero)FEAT_AdvSIMD && FEAT_FP16
0 1 01111 FABS (vector)FEAT_AdvSIMD && FEAT_FP16
0 1 11000 FRINTP (vector)FEAT_AdvSIMD && FEAT_FP16
0 1 11001 FRINTZ (vector)FEAT_AdvSIMD && FEAT_FP16
0 1 11010 FCVTPS (vector)FEAT_AdvSIMD && FEAT_FP16
0 1 11011 FCVTZS (vector, integer)FEAT_AdvSIMD && FEAT_FP16
0 1 11101 FRECPEFEAT_AdvSIMD && FEAT_FP16
0 1 1111x UNALLOCATED-
1 0 11000 FRINTA (vector)FEAT_AdvSIMD && FEAT_FP16
1 0 11001 FRINTX (vector)FEAT_AdvSIMD && FEAT_FP16
1 0 11010 FCVTNU (vector)FEAT_AdvSIMD && FEAT_FP16
1 0 11011 FCVTMU (vector)FEAT_AdvSIMD && FEAT_FP16
1 0 11100 FCVTAU (vector)FEAT_AdvSIMD && FEAT_FP16
1 0 11101 UCVTF (vector, integer)FEAT_AdvSIMD && FEAT_FP16
1 1 x1110 UNALLOCATED-
1 1 01100 FCMGE (zero)FEAT_AdvSIMD && FEAT_FP16
1 1 01101 FCMLE (zero)FEAT_AdvSIMD && FEAT_FP16
1 1 01111 FNEG (vector)FEAT_AdvSIMD && FEAT_FP16
1 1 11000 UNALLOCATED-
1 1 11001 FRINTI (vector)FEAT_AdvSIMD && FEAT_FP16
1 1 11010 FCVTPU (vector)FEAT_AdvSIMD && FEAT_FP16
1 1 11011 FCVTZU (vector, integer)FEAT_AdvSIMD && FEAT_FP16
1 1 11101 FRSQRTEFEAT_AdvSIMD && FEAT_FP16
1 1 11111 FSQRT (vector)FEAT_AdvSIMD && FEAT_FP16

Advanced SIMD three-register extension

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110size0Rm1opcode1RnRd
Decode fields Instruction Details Feature
Q U size opcode
0 0000 UNALLOCATED-
0 0010 SDOT (vector)FEAT_DotProd
0 0x 1010 UNALLOCATED-
0 0x 1100 UNALLOCATED-
0 00 1110 FCVTN, FCVTN2 (single-precision to 8-bit floating-point)FEAT_FP8
0 00 1111 FDOT (8-bit floating-point to single-precision, vector)FEAT_FP8DOT4
0 01 1110 FCVTN (half-precision to 8-bit floating-point)FEAT_FP8
0 01 1111 FDOT (8-bit floating-point to half-precision, vector)FEAT_FP8DOT2
0 10 0001 UNALLOCATED-
0 10 0011 USDOT (vector)FEAT_I8MM
0 10 1xx0 UNALLOCATED-
0 10 1x11 UNALLOCATED-
0 10 1001 UNALLOCATED-
0 11 1xx0 UNALLOCATED-
0 != 10 x0x1 UNALLOCATED-
1 0000 SQRDMLAH (vector)FEAT_RDM
1 0001 SQRDMLSH (vector)FEAT_RDM
1 0010 UDOT (vector)FEAT_DotProd
1 0011 UNALLOCATED-
1 10xx FCMLAFEAT_FCMA
1 11x0 FCADDFEAT_FCMA
1 x0 1111 UNALLOCATED-
1 01 1111 BFDOT (vector)FEAT_BF16
1 11 1111 BFMLALB, BFMLALT (vector)FEAT_BF16
0 01xx UNALLOCATED-
0 1101 UNALLOCATED-
0 0 00 1000 FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (vector) — FMLALLBBFEAT_FP8FMA
0 0 01 1000 FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (vector) — FMLALLBTFEAT_FP8FMA
0 0 11 1111 FMLALB, FMLALT (vector) — FMLALBFEAT_FP8FMA
1 10 011x UNALLOCATED-
1 != 10 01xx UNALLOCATED-
1 0 00 1000 FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (vector) — FMLALLTBFEAT_FP8FMA
1 0 01 1000 FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (vector) — FMLALLTTFEAT_FP8FMA
1 0 10 0100 SMMLA (vector)FEAT_I8MM
1 0 10 0101 USMMLA (vector)FEAT_I8MM
1 0 11 1101 UNALLOCATED-
1 0 11 1111 FMLALB, FMLALT (vector) — FMLALTFEAT_FP8FMA
1 0 != 11 1101 UNALLOCATED-
1 1 00 1101 FMMLA (8-bit floating-point to half-precision)FEAT_F8F16MM
1 1 01 1101 BFMMLAFEAT_BF16
1 1 10 0100 UMMLA (vector)FEAT_I8MM
1 1 10 0101 UNALLOCATED-
1 1 10 1101 FMMLA (8-bit floating-point to single-precision)FEAT_F8F32MM
1 1 11 1101 UNALLOCATED-

Advanced SIMD two-register miscellaneous

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110size10000opcode10RnRd
Decode fields Instruction Details Feature
U size opcode
1000x UNALLOCATED-
10101 UNALLOCATED-
0x 011xx UNALLOCATED-
10 11110 UNALLOCATED-
11 1x110 UNALLOCATED-
0 00000 REV64FEAT_AdvSIMD
0 00001 REV16 (vector)FEAT_AdvSIMD
0 00010 SADDLPFEAT_AdvSIMD
0 00011 SUQADDFEAT_AdvSIMD
0 00100 CLS (vector)FEAT_AdvSIMD
0 00101 CNTFEAT_AdvSIMD
0 00110 SADALPFEAT_AdvSIMD
0 00111 SQABSFEAT_AdvSIMD
0 01000 CMGT (zero)FEAT_AdvSIMD
0 01001 CMEQ (zero)FEAT_AdvSIMD
0 01010 CMLT (zero)FEAT_AdvSIMD
0 01011 ABSFEAT_AdvSIMD
0 10010 XTN, XTN2FEAT_AdvSIMD
0 10011 UNALLOCATED-
0 10100 SQXTN, SQXTN2FEAT_AdvSIMD
0 0x 10110 FCVTN, FCVTN2 (double to single-precision, single to half-precision)FEAT_AdvSIMD
0 0x 10111 FCVTL, FCVTL2FEAT_AdvSIMD
0 0x 11000 FRINTN (vector)FEAT_AdvSIMD
0 0x 11001 FRINTM (vector)FEAT_AdvSIMD
0 0x 11010 FCVTNS (vector)FEAT_AdvSIMD
0 0x 11011 FCVTMS (vector)FEAT_AdvSIMD
0 0x 11100 FCVTAS (vector)FEAT_AdvSIMD
0 0x 11101 SCVTF (vector, integer)FEAT_AdvSIMD
0 0x 11110 FRINT32Z (vector)FEAT_FRINTTS
0 0x 11111 FRINT64Z (vector)FEAT_FRINTTS
0 1x 01100 FCMGT (zero)FEAT_AdvSIMD
0 1x 01101 FCMEQ (zero)FEAT_AdvSIMD
0 1x 01110 FCMLT (zero)FEAT_AdvSIMD
0 1x 01111 FABS (vector)FEAT_AdvSIMD
0 1x 1x111 UNALLOCATED-
0 1x 11000 FRINTP (vector)FEAT_AdvSIMD
0 1x 11001 FRINTZ (vector)FEAT_AdvSIMD
0 1x 11010 FCVTPS (vector)FEAT_AdvSIMD
0 1x 11011 FCVTZS (vector, integer)FEAT_AdvSIMD
0 1x 11100 URECPEFEAT_AdvSIMD
0 1x 11101 FRECPEFEAT_AdvSIMD
0 10 10110 BFCVTN, BFCVTN2FEAT_BF16
1 00000 REV32 (vector)FEAT_AdvSIMD
1 00010 UADDLPFEAT_AdvSIMD
1 00011 USQADDFEAT_AdvSIMD
1 00100 CLZ (vector)FEAT_AdvSIMD
1 00110 UADALPFEAT_AdvSIMD
1 00111 SQNEGFEAT_AdvSIMD
1 01000 CMGE (zero)FEAT_AdvSIMD
1 01001 CMLE (zero)FEAT_AdvSIMD
1 01010 UNALLOCATED-
1 01011 NEG (vector)FEAT_AdvSIMD
1 10010 SQXTUN, SQXTUN2FEAT_AdvSIMD
1 10011 SHLL, SHLL2FEAT_AdvSIMD
1 10100 UQXTN, UQXTN2FEAT_AdvSIMD
1 x0 10110 UNALLOCATED-
1 0x 00001 UNALLOCATED-
1 0x 11000 FRINTA (vector)FEAT_AdvSIMD
1 0x 11001 FRINTX (vector)FEAT_AdvSIMD
1 0x 11010 FCVTNU (vector)FEAT_AdvSIMD
1 0x 11011 FCVTMU (vector)FEAT_AdvSIMD
1 0x 11100 FCVTAU (vector)FEAT_AdvSIMD
1 0x 11101 UCVTF (vector, integer)FEAT_AdvSIMD
1 0x 11110 FRINT32X (vector)FEAT_FRINTTS
1 0x 11111 FRINT64X (vector)FEAT_FRINTTS
1 00 00101 NOTFEAT_AdvSIMD
1 00 10111 F1CVTL, F1CVTL2, F2CVTL, F2CVTL2 — F1CVTL{2}FEAT_FP8
1 01 00101 RBIT (vector)FEAT_AdvSIMD
1 01 10110 FCVTXN, FCVTXN2FEAT_AdvSIMD
1 01 10111 F1CVTL, F1CVTL2, F2CVTL, F2CVTL2 — F2CVTL{2}FEAT_FP8
1 1x 00x01 UNALLOCATED-
1 1x 01100 FCMGE (zero)FEAT_AdvSIMD
1 1x 01101 FCMLE (zero)FEAT_AdvSIMD
1 1x 01110 UNALLOCATED-
1 1x 01111 FNEG (vector)FEAT_AdvSIMD
1 1x 11000 UNALLOCATED-
1 1x 11001 FRINTI (vector)FEAT_AdvSIMD
1 1x 11010 FCVTPU (vector)FEAT_AdvSIMD
1 1x 11011 FCVTZU (vector, integer)FEAT_AdvSIMD
1 1x 11100 URSQRTEFEAT_AdvSIMD
1 1x 11101 FRSQRTEFEAT_AdvSIMD
1 1x 11111 FSQRT (vector)FEAT_AdvSIMD
1 10 10111 BF1CVTL, BF1CVTL2, BF2CVTL, BF2CVTL2 — BF1CVTL{2}FEAT_FP8
1 11 10111 BF1CVTL, BF1CVTL2, BF2CVTL, BF2CVTL2 — BF2CVTL{2}FEAT_FP8

Advanced SIMD across lanes

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110size11000opcode10RnRd
Decode fields Instruction Details Feature
Q U size opcode
x100x UNALLOCATED-
000x0 UNALLOCATED-
00001 UNALLOCATED-
01011 UNALLOCATED-
100xx UNALLOCATED-
x0 001xx UNALLOCATED-
x0 01101 UNALLOCATED-
x0 101xx UNALLOCATED-
x0 111xx UNALLOCATED-
x1 xx1xx UNALLOCATED-
0 00011 SADDLVFEAT_AdvSIMD
0 01010 SMAXVFEAT_AdvSIMD
0 11010 SMINVFEAT_AdvSIMD
0 11011 ADDVFEAT_AdvSIMD
0 x0 01110 UNALLOCATED-
0 00 01100 FMAXNMV — Half-precisionFEAT_AdvSIMD && FEAT_FP16
0 00 01111 FMAXV — Half-precisionFEAT_AdvSIMD && FEAT_FP16
0 10 01100 FMINNMV — Half-precisionFEAT_AdvSIMD && FEAT_FP16
0 10 01111 FMINV — Half-precisionFEAT_AdvSIMD && FEAT_FP16
1 00011 UADDLVFEAT_AdvSIMD
1 01010 UMAXVFEAT_AdvSIMD
1 11010 UMINVFEAT_AdvSIMD
1 11011 UNALLOCATED-
0 1 x0 011x0 UNALLOCATED-
0 1 x0 01111 UNALLOCATED-
1 1 x0 01110 UNALLOCATED-
1 1 00 01100 FMAXNMV — Single-precisionFEAT_AdvSIMD
1 1 00 01111 FMAXV — Single-precisionFEAT_AdvSIMD
1 1 10 01100 FMINNMV — Single-precisionFEAT_AdvSIMD
1 1 10 01111 FMINV — Single-precisionFEAT_AdvSIMD

Advanced SIMD three different

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110size1Rmopcode00RnRd
Decode fields Instruction Details Feature
U opcode
0 0000 SADDL, SADDL2FEAT_AdvSIMD
0 0001 SADDW, SADDW2FEAT_AdvSIMD
0 0010 SSUBL, SSUBL2FEAT_AdvSIMD
0 0011 SSUBW, SSUBW2FEAT_AdvSIMD
0 0100 ADDHN, ADDHN2FEAT_AdvSIMD
0 0101 SABAL, SABAL2FEAT_AdvSIMD
0 0110 SUBHN, SUBHN2FEAT_AdvSIMD
0 0111 SABDL, SABDL2FEAT_AdvSIMD
0 1000 SMLAL, SMLAL2 (vector)FEAT_AdvSIMD
0 1001 SQDMLAL, SQDMLAL2 (vector)FEAT_AdvSIMD
0 1010 SMLSL, SMLSL2 (vector)FEAT_AdvSIMD
0 1011 SQDMLSL, SQDMLSL2 (vector)FEAT_AdvSIMD
0 1100 SMULL, SMULL2 (vector)FEAT_AdvSIMD
0 1101 SQDMULL, SQDMULL2 (vector)FEAT_AdvSIMD
0 1110 PMULL, PMULL2FEAT_AdvSIMD
0 1111 UNALLOCATED-
1 0000 UADDL, UADDL2FEAT_AdvSIMD
1 0001 UADDW, UADDW2FEAT_AdvSIMD
1 0010 USUBL, USUBL2FEAT_AdvSIMD
1 0011 USUBW, USUBW2FEAT_AdvSIMD
1 0100 RADDHN, RADDHN2FEAT_AdvSIMD
1 0101 UABAL, UABAL2FEAT_AdvSIMD
1 0110 RSUBHN, RSUBHN2FEAT_AdvSIMD
1 0111 UABDL, UABDL2FEAT_AdvSIMD
1 1xx1 UNALLOCATED-
1 1000 UMLAL, UMLAL2 (vector)FEAT_AdvSIMD
1 1010 UMLSL, UMLSL2 (vector)FEAT_AdvSIMD
1 1100 UMULL, UMULL2 (vector)FEAT_AdvSIMD
1 1110 UNALLOCATED-

Advanced SIMD three same

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110size1Rmopcode1RnRd
Decode fields Instruction Details Feature
U size opcode
0 00000 SHADDFEAT_AdvSIMD
0 00001 SQADDFEAT_AdvSIMD
0 00010 SRHADDFEAT_AdvSIMD
0 00100 SHSUBFEAT_AdvSIMD
0 00101 SQSUBFEAT_AdvSIMD
0 00110 CMGT (register)FEAT_AdvSIMD
0 00111 CMGE (register)FEAT_AdvSIMD
0 01000 SSHLFEAT_AdvSIMD
0 01001 SQSHL (register)FEAT_AdvSIMD
0 01010 SRSHLFEAT_AdvSIMD
0 01011 SQRSHLFEAT_AdvSIMD
0 01100 SMAXFEAT_AdvSIMD
0 01101 SMINFEAT_AdvSIMD
0 01110 SABDFEAT_AdvSIMD
0 01111 SABAFEAT_AdvSIMD
0 10000 ADD (vector)FEAT_AdvSIMD
0 10001 CMTSTFEAT_AdvSIMD
0 10010 MLA (vector)FEAT_AdvSIMD
0 10011 MUL (vector)FEAT_AdvSIMD
0 10100 SMAXPFEAT_AdvSIMD
0 10101 SMINPFEAT_AdvSIMD
0 10110 SQDMULH (vector)FEAT_AdvSIMD
0 10111 ADDP (vector)FEAT_AdvSIMD
0 x1 11101 UNALLOCATED-
0 0x 11000 FMAXNM (vector)FEAT_AdvSIMD
0 0x 11001 FMLA (vector)FEAT_AdvSIMD
0 0x 11010 FADD (vector)FEAT_AdvSIMD
0 0x 11011 FMULXFEAT_AdvSIMD
0 0x 11100 FCMEQ (register)FEAT_AdvSIMD
0 0x 11110 FMAX (vector)FEAT_AdvSIMD
0 0x 11111 FRECPSFEAT_AdvSIMD
0 00 00011 AND (vector)FEAT_AdvSIMD
0 00 11101 FMLAL, FMLAL2 (vector) — FMLALFEAT_FHM
0 01 00011 BIC (vector, register)FEAT_AdvSIMD
0 1x 11000 FMINNM (vector)FEAT_AdvSIMD
0 1x 11001 FMLS (vector)FEAT_AdvSIMD
0 1x 11010 FSUB (vector)FEAT_AdvSIMD
0 1x 11011 FAMAXFEAT_AdvSIMD && FEAT_FAMINMAX
0 1x 11100 UNALLOCATED-
0 1x 11110 FMIN (vector)FEAT_AdvSIMD
0 1x 11111 FRSQRTSFEAT_AdvSIMD
0 10 00011 ORR (vector, register)FEAT_AdvSIMD
0 10 11101 FMLSL, FMLSL2 (vector) — FMLSLFEAT_FHM
0 11 00011 ORN (vector)FEAT_AdvSIMD
1 00000 UHADDFEAT_AdvSIMD
1 00001 UQADDFEAT_AdvSIMD
1 00010 URHADDFEAT_AdvSIMD
1 00100 UHSUBFEAT_AdvSIMD
1 00101 UQSUBFEAT_AdvSIMD
1 00110 CMHI (register)FEAT_AdvSIMD
1 00111 CMHS (register)FEAT_AdvSIMD
1 01000 USHLFEAT_AdvSIMD
1 01001 UQSHL (register)FEAT_AdvSIMD
1 01010 URSHLFEAT_AdvSIMD
1 01011 UQRSHLFEAT_AdvSIMD
1 01100 UMAXFEAT_AdvSIMD
1 01101 UMINFEAT_AdvSIMD
1 01110 UABDFEAT_AdvSIMD
1 01111 UABAFEAT_AdvSIMD
1 10000 SUB (vector)FEAT_AdvSIMD
1 10001 CMEQ (register)FEAT_AdvSIMD
1 10010 MLS (vector)FEAT_AdvSIMD
1 10011 PMULFEAT_AdvSIMD
1 10100 UMAXPFEAT_AdvSIMD
1 10101 UMINPFEAT_AdvSIMD
1 10110 SQRDMULH (vector)FEAT_AdvSIMD
1 10111 UNALLOCATED-
1 x1 11001 UNALLOCATED-
1 0x 11000 FMAXNMP (vector)FEAT_AdvSIMD
1 0x 11010 FADDP (vector)FEAT_AdvSIMD
1 0x 11011 FMUL (vector)FEAT_AdvSIMD
1 0x 11100 FCMGE (register)FEAT_AdvSIMD
1 0x 11101 FACGEFEAT_AdvSIMD
1 0x 11110 FMAXP (vector)FEAT_AdvSIMD
1 0x 11111 FDIV (vector)FEAT_AdvSIMD
1 00 00011 EOR (vector)FEAT_AdvSIMD
1 00 11001 FMLAL, FMLAL2 (vector) — FMLAL2FEAT_FHM
1 01 00011 BSLFEAT_AdvSIMD
1 1x 11000 FMINNMP (vector)FEAT_AdvSIMD
1 1x 11010 FABDFEAT_AdvSIMD
1 1x 11011 FAMINFEAT_AdvSIMD && FEAT_FAMINMAX
1 1x 11100 FCMGT (register)FEAT_AdvSIMD
1 1x 11101 FACGTFEAT_AdvSIMD
1 1x 11110 FMINP (vector)FEAT_AdvSIMD
1 1x 11111 FSCALEFEAT_FP8
1 10 00011 BITFEAT_AdvSIMD
1 10 11001 FMLSL, FMLSL2 (vector) — FMLSL2FEAT_FHM
1 11 00011 BIFFEAT_AdvSIMD

Advanced SIMD modified immediate

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0Qop0111100000abccmodeo21defghRd
Decode fields Instruction Details Feature
Q op cmode o2
0 0xx0 0 MOVI — 32-bit shifted immediateFEAT_AdvSIMD
0 0xx1 0 ORR (vector, immediate) — 32-bitFEAT_AdvSIMD
0 10x0 0 MOVI — 16-bit shifted immediateFEAT_AdvSIMD
0 10x1 0 ORR (vector, immediate) — 16-bitFEAT_AdvSIMD
0 110x 0 MOVI — 32-bit shifting onesFEAT_AdvSIMD
0 1110 0 MOVI — 8-bitFEAT_AdvSIMD
0 1111 0 FMOV (vector, immediate) — Single-precisionFEAT_AdvSIMD
0 1111 1 FMOV (vector, immediate) — Half-precisionFEAT_AdvSIMD && FEAT_FP16
0 != 1111 1 UNALLOCATED-
1 1 UNALLOCATED-
1 0xx0 0 MVNI — 32-bit shifted immediateFEAT_AdvSIMD
1 0xx1 0 BIC (vector, immediate) — 32-bitFEAT_AdvSIMD
1 10x0 0 MVNI — 16-bit shifted immediateFEAT_AdvSIMD
1 10x1 0 BIC (vector, immediate) — 16-bitFEAT_AdvSIMD
1 110x 0 MVNI — 32-bit shifting onesFEAT_AdvSIMD
0 1 1110 0 MOVI — 64-bit scalarFEAT_AdvSIMD
0 1 1111 0 UNALLOCATED-
1 1 1110 0 MOVI — 64-bit vectorFEAT_AdvSIMD
1 1 1111 0 FMOV (vector, immediate) — Double-precisionFEAT_AdvSIMD

Advanced SIMD shift by immediate

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU011110!= 0000immbopcode1RnRd
immh

The following constraints also apply to this encoding: immh != '0000'

Decode fields Instruction Details Feature
U immh opcode
!= 0000 0xxx1 UNALLOCATED-
!= 0000 1x110 UNALLOCATED-
!= 0000 101x1 UNALLOCATED-
!= 0000 110xx UNALLOCATED-
!= 0000 11101 UNALLOCATED-
0 != 0000 00000 SSHRFEAT_AdvSIMD
0 != 0000 00010 SSRAFEAT_AdvSIMD
0 != 0000 00100 SRSHRFEAT_AdvSIMD
0 != 0000 00110 SRSRAFEAT_AdvSIMD
0 != 0000 01x00 UNALLOCATED-
0 != 0000 01010 SHLFEAT_AdvSIMD
0 != 0000 01110 SQSHL (immediate)FEAT_AdvSIMD
0 != 0000 10000 SHRN, SHRN2FEAT_AdvSIMD
0 != 0000 10001 RSHRN, RSHRN2FEAT_AdvSIMD
0 != 0000 10010 SQSHRN, SQSHRN2FEAT_AdvSIMD
0 != 0000 10011 SQRSHRN, SQRSHRN2FEAT_AdvSIMD
0 != 0000 10100 SSHLL, SSHLL2FEAT_AdvSIMD
0 != 0000 11100 SCVTF (vector, fixed-point)FEAT_AdvSIMD
0 != 0000 11111 FCVTZS (vector, fixed-point)FEAT_AdvSIMD
1 != 0000 00000 USHRFEAT_AdvSIMD
1 != 0000 00010 USRAFEAT_AdvSIMD
1 != 0000 00100 URSHRFEAT_AdvSIMD
1 != 0000 00110 URSRAFEAT_AdvSIMD
1 != 0000 01000 SRIFEAT_AdvSIMD
1 != 0000 01010 SLIFEAT_AdvSIMD
1 != 0000 01100 SQSHLUFEAT_AdvSIMD
1 != 0000 01110 UQSHL (immediate)FEAT_AdvSIMD
1 != 0000 10000 SQSHRUN, SQSHRUN2FEAT_AdvSIMD
1 != 0000 10001 SQRSHRUN, SQRSHRUN2FEAT_AdvSIMD
1 != 0000 10010 UQSHRN, UQSHRN2FEAT_AdvSIMD
1 != 0000 10011 UQRSHRN, UQRSHRN2FEAT_AdvSIMD
1 != 0000 10100 USHLL, USHLL2FEAT_AdvSIMD
1 != 0000 11100 UCVTF (vector, fixed-point)FEAT_AdvSIMD
1 != 0000 11111 FCVTZU (vector, fixed-point)FEAT_AdvSIMD

Advanced SIMD vector x indexed element

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01111sizeLMRmopcodeH0RnRd
Decode fields Instruction Details Feature
Q U size opcode
01 1001 UNALLOCATED-
0 0010 SMLAL, SMLAL2 (by element)FEAT_AdvSIMD
0 0011 SQDMLAL, SQDMLAL2 (by element)FEAT_AdvSIMD
0 0110 SMLSL, SMLSL2 (by element)FEAT_AdvSIMD
0 0111 SQDMLSL, SQDMLSL2 (by element)FEAT_AdvSIMD
0 1000 MUL (by element)FEAT_AdvSIMD
0 1010 SMULL, SMULL2 (by element)FEAT_AdvSIMD
0 1011 SQDMULL, SQDMULL2 (by element)FEAT_AdvSIMD
0 1100 SQDMULH (by element)FEAT_AdvSIMD
0 1101 SQRDMULH (by element)FEAT_AdvSIMD
0 1110 SDOT (by element)FEAT_DotProd
0 00 0000 FDOT (8-bit floating-point to single-precision, by element)FEAT_FP8DOT4
0 00 0001 FMLA (by element) — Vector, half-precisionFEAT_AdvSIMD && FEAT_FP16
0 00 0101 FMLS (by element) — Vector, half-precisionFEAT_AdvSIMD && FEAT_FP16
0 00 1001 FMUL (by element) — Vector, half-precisionFEAT_AdvSIMD && FEAT_FP16
0 00 1111 SUDOT (by element)FEAT_I8MM
0 01 0x01 UNALLOCATED-
0 01 0000 FDOT (8-bit floating-point to half-precision, by element)FEAT_FP8DOT2
0 01 1111 BFDOT (by element)FEAT_BF16
0 1x 0001 FMLA (by element) — Vector, single-precision and double-precisionFEAT_AdvSIMD
0 1x 0101 FMLS (by element) — Vector, single-precision and double-precisionFEAT_AdvSIMD
0 1x 1001 FMUL (by element) — Vector, single-precision and double-precisionFEAT_AdvSIMD
0 10 0000 FMLAL, FMLAL2 (by element) — FMLALFEAT_FHM
0 10 0100 FMLSL, FMLSL2 (by element) — FMLSLFEAT_FHM
0 10 1111 USDOT (by element)FEAT_I8MM
0 11 1111 BFMLALB, BFMLALT (by element)FEAT_BF16
0 != 10 0100 UNALLOCATED-
1 0xx1 FCMLA (by element)FEAT_FCMA
1 0000 MLA (by element)FEAT_AdvSIMD
1 0010 UMLAL, UMLAL2 (by element)FEAT_AdvSIMD
1 0100 MLS (by element)FEAT_AdvSIMD
1 0110 UMLSL, UMLSL2 (by element)FEAT_AdvSIMD
1 1010 UMULL, UMULL2 (by element)FEAT_AdvSIMD
1 1011 UNALLOCATED-
1 1101 SQRDMLAH (by element)FEAT_RDM
1 1110 UDOT (by element)FEAT_DotProd
1 1111 SQRDMLSH (by element)FEAT_RDM
1 0x 1100 UNALLOCATED-
1 00 1001 FMULX (by element) — Vector, half-precisionFEAT_AdvSIMD && FEAT_FP16
1 1x 1001 FMULX (by element) — Vector, single-precision and double-precisionFEAT_AdvSIMD
1 10 1000 FMLAL, FMLAL2 (by element) — FMLAL2FEAT_FHM
1 10 1100 FMLSL, FMLSL2 (by element) — FMLSL2FEAT_FHM
1 11 1x00 UNALLOCATED-
0 0 11 0000 FMLALB, FMLALT (by element) — FMLALBFEAT_FP8FMA
0 1 00 1000 FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (by element) — FMLALLBBFEAT_FP8FMA
0 1 01 1000 FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (by element) — FMLALLBTFEAT_FP8FMA
1 0 11 0000 FMLALB, FMLALT (by element) — FMLALTFEAT_FP8FMA
1 1 00 1000 FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (by element) — FMLALLTBFEAT_FP8FMA
1 1 01 1000 FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (by element) — FMLALLTTFEAT_FP8FMA

Cryptographic three-register, imm2

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
11001110010Rm10imm2opcodeRnRd
Decode fields Instruction Details Feature
opcode
00 SM3TT1AFEAT_SM3
01 SM3TT1BFEAT_SM3
10 SM3TT2AFEAT_SM3
11 SM3TT2BFEAT_SM3

Cryptographic three-register SHA 512

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
11001110011Rm1O00opcodeRnRd
Decode fields Instruction Details Feature
O opcode
0 00 SHA512HFEAT_SHA512
0 01 SHA512H2FEAT_SHA512
0 10 SHA512SU1FEAT_SHA512
0 11 RAX1FEAT_SHA3
1 00 SM3PARTW1FEAT_SM3
1 01 SM3PARTW2FEAT_SM3
1 10 SM4EKEYFEAT_SM4
1 11 UNALLOCATED-

Cryptographic four-register

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
110011100Op0Rm0RaRnRd
Decode fields Instruction Details Feature
Op0
00 EOR3FEAT_SHA3
01 BCAXFEAT_SHA3
10 SM3SS1FEAT_SM3
11 UNALLOCATED-

Cryptographic two-register SHA 512

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
11001110110000001000opcodeRnRd
Decode fields Instruction Details Feature
opcode
00 SHA512SU0FEAT_SHA512
01 SM4EFEAT_SM4
1x UNALLOCATED-

Conversion between floating-point and fixed-point

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
sf0S11110ftype0rmodeopcodescaleRnRd
Decode fields Instruction Details Feature
sf S ftype rmode opcode
0 1xx UNALLOCATED-
0 10 0xx UNALLOCATED-
0 != 10 x1 01x UNALLOCATED-
0 != 10 0x 00x UNALLOCATED-
0 != 10 10 0xx UNALLOCATED-
1 UNALLOCATED-
0 0 00 00 010 SCVTF (scalar, fixed-point) — 32-bit to single-precisionFEAT_FP
0 0 00 00 011 UCVTF (scalar, fixed-point) — 32-bit to single-precisionFEAT_FP
0 0 00 11 000 FCVTZS (scalar, fixed-point) — Single-precision to 32-bitFEAT_FP
0 0 00 11 001 FCVTZU (scalar, fixed-point) — Single-precision to 32-bitFEAT_FP
0 0 01 00 010 SCVTF (scalar, fixed-point) — 32-bit to double-precisionFEAT_FP
0 0 01 00 011 UCVTF (scalar, fixed-point) — 32-bit to double-precisionFEAT_FP
0 0 01 11 000 FCVTZS (scalar, fixed-point) — Double-precision to 32-bitFEAT_FP
0 0 01 11 001 FCVTZU (scalar, fixed-point) — Double-precision to 32-bitFEAT_FP
0 0 11 00 010 SCVTF (scalar, fixed-point) — 32-bit to half-precisionFEAT_FP16
0 0 11 00 011 UCVTF (scalar, fixed-point) — 32-bit to half-precisionFEAT_FP16
0 0 11 11 000 FCVTZS (scalar, fixed-point) — Half-precision to 32-bitFEAT_FP16
0 0 11 11 001 FCVTZU (scalar, fixed-point) — Half-precision to 32-bitFEAT_FP16
1 0 00 00 010 SCVTF (scalar, fixed-point) — 64-bit to single-precisionFEAT_FP
1 0 00 00 011 UCVTF (scalar, fixed-point) — 64-bit to single-precisionFEAT_FP
1 0 00 11 000 FCVTZS (scalar, fixed-point) — Single-precision to 64-bitFEAT_FP
1 0 00 11 001 FCVTZU (scalar, fixed-point) — Single-precision to 64-bitFEAT_FP
1 0 01 00 010 SCVTF (scalar, fixed-point) — 64-bit to double-precisionFEAT_FP
1 0 01 00 011 UCVTF (scalar, fixed-point) — 64-bit to double-precisionFEAT_FP
1 0 01 11 000 FCVTZS (scalar, fixed-point) — Double-precision to 64-bitFEAT_FP
1 0 01 11 001 FCVTZU (scalar, fixed-point) — Double-precision to 64-bitFEAT_FP
1 0 11 00 010 SCVTF (scalar, fixed-point) — 64-bit to half-precisionFEAT_FP16
1 0 11 00 011 UCVTF (scalar, fixed-point) — 64-bit to half-precisionFEAT_FP16
1 0 11 11 000 FCVTZS (scalar, fixed-point) — Half-precision to 64-bitFEAT_FP16
1 0 11 11 001 FCVTZU (scalar, fixed-point) — Half-precision to 64-bitFEAT_FP16

Conversion between floating-point and integer

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
sf0S11110ftype1rmodeopcode000000RnRd
Decode fields Instruction Details Feature
sf S ftype rmode opcode
0 10 x0 UNALLOCATED-
0 10 x1 0xx UNALLOCATED-
0 10 x1 10x UNALLOCATED-
0 11 x1 11x UNALLOCATED-
0 != 10 01 10x UNALLOCATED-
1 UNALLOCATED-
0 0 x0 01 11x UNALLOCATED-
0 0 00 00 000 FCVTNS (scalar) — Single-precision to 32-bitFEAT_FP
0 0 00 00 001 FCVTNU (scalar) — Single-precision to 32-bitFEAT_FP
0 0 00 00 010 SCVTF (scalar, integer) — 32-bit to single-precisionFEAT_FP
0 0 00 00 011 UCVTF (scalar, integer) — 32-bit to single-precisionFEAT_FP
0 0 00 00 100 FCVTAS (scalar) — Single-precision to 32-bitFEAT_FP
0 0 00 00 101 FCVTAU (scalar) — Single-precision to 32-bitFEAT_FP
0 0 00 00 110 FMOV (general) — Single-precision to 32-bitFEAT_FP
0 0 00 00 111 FMOV (general) — 32-bit to single-precisionFEAT_FP
0 0 00 01 000 FCVTPS (scalar) — Single-precision to 32-bitFEAT_FP
0 0 00 01 001 FCVTPU (scalar) — Single-precision to 32-bitFEAT_FP
0 0 00 1x 1xx UNALLOCATED-
0 0 00 10 000 FCVTMS (scalar) — Single-precision to 32-bitFEAT_FP
0 0 00 10 001 FCVTMU (scalar) — Single-precision to 32-bitFEAT_FP
0 0 00 11 000 FCVTZS (scalar, integer) — Single-precision to 32-bitFEAT_FP
0 0 00 11 001 FCVTZU (scalar, integer) — Single-precision to 32-bitFEAT_FP
0 0 00 != 00 01x UNALLOCATED-
0 0 01 0x 11x UNALLOCATED-
0 0 01 00 000 FCVTNS (scalar) — Double-precision to 32-bitFEAT_FP
0 0 01 00 001 FCVTNU (scalar) — Double-precision to 32-bitFEAT_FP
0 0 01 00 010 SCVTF (scalar, integer) — 32-bit to double-precisionFEAT_FP
0 0 01 00 011 UCVTF (scalar, integer) — 32-bit to double-precisionFEAT_FP
0 0 01 00 100 FCVTAS (scalar) — Double-precision to 32-bitFEAT_FP
0 0 01 00 101 FCVTAU (scalar) — Double-precision to 32-bitFEAT_FP
0 0 01 01 000 FCVTPS (scalar) — Double-precision to 32-bitFEAT_FP
0 0 01 01 001 FCVTPU (scalar) — Double-precision to 32-bitFEAT_FP
0 0 01 01 010 FCVTNS (scalar SIMD&FP) — Double-precision to 32-bitFEAT_FPRCVT
0 0 01 01 011 FCVTNU (scalar SIMD&FP) — Double-precision to 32-bitFEAT_FPRCVT
0 0 01 10 000 FCVTMS (scalar) — Double-precision to 32-bitFEAT_FP
0 0 01 10 001 FCVTMU (scalar) — Double-precision to 32-bitFEAT_FP
0 0 01 10 010 FCVTPS (scalar SIMD&FP) — Double-precision to 32-bitFEAT_FPRCVT
0 0 01 10 011 FCVTPU (scalar SIMD&FP) — Double-precision to 32-bitFEAT_FPRCVT
0 0 01 10 100 FCVTMS (scalar SIMD&FP) — Double-precision to 32-bitFEAT_FPRCVT
0 0 01 10 101 FCVTMU (scalar SIMD&FP) — Double-precision to 32-bitFEAT_FPRCVT
0 0 01 10 110 FCVTZS (scalar SIMD&FP) — Double-precision to 32-bitFEAT_FPRCVT
0 0 01 10 111 FCVTZU (scalar SIMD&FP) — Double-precision to 32-bitFEAT_FPRCVT
0 0 01 11 000 FCVTZS (scalar, integer) — Double-precision to 32-bitFEAT_FP
0 0 01 11 001 FCVTZU (scalar, integer) — Double-precision to 32-bitFEAT_FP
0 0 01 11 010 FCVTAS (scalar SIMD&FP) — Double-precision to 32-bitFEAT_FPRCVT
0 0 01 11 011 FCVTAU (scalar SIMD&FP) — Double-precision to 32-bitFEAT_FPRCVT
0 0 01 11 100 SCVTF (scalar SIMD&FP) — 32-bit to double-precisionFEAT_FPRCVT
0 0 01 11 101 UCVTF (scalar SIMD&FP) — 32-bit to double-precisionFEAT_FPRCVT
0 0 01 11 110 FJCVTZSFEAT_JSCVT
0 0 01 11 111 UNALLOCATED-
0 0 10 11 11x UNALLOCATED-
0 0 11 00 000 FCVTNS (scalar) — Half-precision to 32-bitFEAT_FP16
0 0 11 00 001 FCVTNU (scalar) — Half-precision to 32-bitFEAT_FP16
0 0 11 00 010 SCVTF (scalar, integer) — 32-bit to half-precisionFEAT_FP16
0 0 11 00 011 UCVTF (scalar, integer) — 32-bit to half-precisionFEAT_FP16
0 0 11 00 100 FCVTAS (scalar) — Half-precision to 32-bitFEAT_FP16
0 0 11 00 101 FCVTAU (scalar) — Half-precision to 32-bitFEAT_FP16
0 0 11 00 110 FMOV (general) — Half-precision to 32-bitFEAT_FP16
0 0 11 00 111 FMOV (general) — 32-bit to half-precisionFEAT_FP16
0 0 11 01 000 FCVTPS (scalar) — Half-precision to 32-bitFEAT_FP16
0 0 11 01 001 FCVTPU (scalar) — Half-precision to 32-bitFEAT_FP16
0 0 11 01 010 FCVTNS (scalar SIMD&FP) — Half-precision to 32-bitFEAT_FPRCVT
0 0 11 01 011 FCVTNU (scalar SIMD&FP) — Half-precision to 32-bitFEAT_FPRCVT
0 0 11 10 000 FCVTMS (scalar) — Half-precision to 32-bitFEAT_FP16
0 0 11 10 001 FCVTMU (scalar) — Half-precision to 32-bitFEAT_FP16
0 0 11 10 010 FCVTPS (scalar SIMD&FP) — Half-precision to 32-bitFEAT_FPRCVT
0 0 11 10 011 FCVTPU (scalar SIMD&FP) — Half-precision to 32-bitFEAT_FPRCVT
0 0 11 10 100 FCVTMS (scalar SIMD&FP) — Half-precision to 32-bitFEAT_FPRCVT
0 0 11 10 101 FCVTMU (scalar SIMD&FP) — Half-precision to 32-bitFEAT_FPRCVT
0 0 11 10 110 FCVTZS (scalar SIMD&FP) — Half-precision to 32-bitFEAT_FPRCVT
0 0 11 10 111 FCVTZU (scalar SIMD&FP) — Half-precision to 32-bitFEAT_FPRCVT
0 0 11 11 000 FCVTZS (scalar, integer) — Half-precision to 32-bitFEAT_FP16
0 0 11 11 001 FCVTZU (scalar, integer) — Half-precision to 32-bitFEAT_FP16
0 0 11 11 010 FCVTAS (scalar SIMD&FP) — Half-precision to 32-bitFEAT_FPRCVT
0 0 11 11 011 FCVTAU (scalar SIMD&FP) — Half-precision to 32-bitFEAT_FPRCVT
0 0 11 11 100 SCVTF (scalar SIMD&FP) — 32-bit to half-precisionFEAT_FPRCVT
0 0 11 11 101 UCVTF (scalar SIMD&FP) — 32-bit to half-precisionFEAT_FPRCVT
1 0 x0 11 11x UNALLOCATED-
1 0 00 0x 11x UNALLOCATED-
1 0 00 00 000 FCVTNS (scalar) — Single-precision to 64-bitFEAT_FP
1 0 00 00 001 FCVTNU (scalar) — Single-precision to 64-bitFEAT_FP
1 0 00 00 010 SCVTF (scalar, integer) — 64-bit to single-precisionFEAT_FP
1 0 00 00 011 UCVTF (scalar, integer) — 64-bit to single-precisionFEAT_FP
1 0 00 00 100 FCVTAS (scalar) — Single-precision to 64-bitFEAT_FP
1 0 00 00 101 FCVTAU (scalar) — Single-precision to 64-bitFEAT_FP
1 0 00 01 000 FCVTPS (scalar) — Single-precision to 64-bitFEAT_FP
1 0 00 01 001 FCVTPU (scalar) — Single-precision to 64-bitFEAT_FP
1 0 00 01 010 FCVTNS (scalar SIMD&FP) — Single-precision to 64-bitFEAT_FPRCVT
1 0 00 01 011 FCVTNU (scalar SIMD&FP) — Single-precision to 64-bitFEAT_FPRCVT
1 0 00 10 000 FCVTMS (scalar) — Single-precision to 64-bitFEAT_FP
1 0 00 10 001 FCVTMU (scalar) — Single-precision to 64-bitFEAT_FP
1 0 00 10 010 FCVTPS (scalar SIMD&FP) — Single-precision to 64-bitFEAT_FPRCVT
1 0 00 10 011 FCVTPU (scalar SIMD&FP) — Single-precision to 64-bitFEAT_FPRCVT
1 0 00 10 100 FCVTMS (scalar SIMD&FP) — Single-precision to 64-bitFEAT_FPRCVT
1 0 00 10 101 FCVTMU (scalar SIMD&FP) — Single-precision to 64-bitFEAT_FPRCVT
1 0 00 10 110 FCVTZS (scalar SIMD&FP) — Single-precision to 64-bitFEAT_FPRCVT
1 0 00 10 111 FCVTZU (scalar SIMD&FP) — Single-precision to 64-bitFEAT_FPRCVT
1 0 00 11 000 FCVTZS (scalar, integer) — Single-precision to 64-bitFEAT_FP
1 0 00 11 001 FCVTZU (scalar, integer) — Single-precision to 64-bitFEAT_FP
1 0 00 11 010 FCVTAS (scalar SIMD&FP) — Single-precision to 64-bitFEAT_FPRCVT
1 0 00 11 011 FCVTAU (scalar SIMD&FP) — Single-precision to 64-bitFEAT_FPRCVT
1 0 00 11 100 SCVTF (scalar SIMD&FP) — 64-bit to single-precisionFEAT_FPRCVT
1 0 00 11 101 UCVTF (scalar SIMD&FP) — 64-bit to single-precisionFEAT_FPRCVT
1 0 01 00 000 FCVTNS (scalar) — Double-precision to 64-bitFEAT_FP
1 0 01 00 001 FCVTNU (scalar) — Double-precision to 64-bitFEAT_FP
1 0 01 00 010 SCVTF (scalar, integer) — 64-bit to double-precisionFEAT_FP
1 0 01 00 011 UCVTF (scalar, integer) — 64-bit to double-precisionFEAT_FP
1 0 01 00 100 FCVTAS (scalar) — Double-precision to 64-bitFEAT_FP
1 0 01 00 101 FCVTAU (scalar) — Double-precision to 64-bitFEAT_FP
1 0 01 00 110 FMOV (general) — Double-precision to 64-bitFEAT_FP
1 0 01 00 111 FMOV (general) — 64-bit to double-precisionFEAT_FP
1 0 01 01 x1x UNALLOCATED-
1 0 01 01 000 FCVTPS (scalar) — Double-precision to 64-bitFEAT_FP
1 0 01 01 001 FCVTPU (scalar) — Double-precision to 64-bitFEAT_FP
1 0 01 1x 01x UNALLOCATED-
1 0 01 1x 1xx UNALLOCATED-
1 0 01 10 000 FCVTMS (scalar) — Double-precision to 64-bitFEAT_FP
1 0 01 10 001 FCVTMU (scalar) — Double-precision to 64-bitFEAT_FP
1 0 01 11 000 FCVTZS (scalar, integer) — Double-precision to 64-bitFEAT_FP
1 0 01 11 001 FCVTZU (scalar, integer) — Double-precision to 64-bitFEAT_FP
1 0 10 01 110 FMOV (general) — Top half of 128-bit to 64-bitFEAT_FP
1 0 10 01 111 FMOV (general) — 64-bit to top half of 128-bitFEAT_FP
1 0 11 00 000 FCVTNS (scalar) — Half-precision to 64-bitFEAT_FP16
1 0 11 00 001 FCVTNU (scalar) — Half-precision to 64-bitFEAT_FP16
1 0 11 00 010 SCVTF (scalar, integer) — 64-bit to half-precisionFEAT_FP16
1 0 11 00 011 UCVTF (scalar, integer) — 64-bit to half-precisionFEAT_FP16
1 0 11 00 100 FCVTAS (scalar) — Half-precision to 64-bitFEAT_FP16
1 0 11 00 101 FCVTAU (scalar) — Half-precision to 64-bitFEAT_FP16
1 0 11 00 110 FMOV (general) — Half-precision to 64-bitFEAT_FP16
1 0 11 00 111 FMOV (general) — 64-bit to half-precisionFEAT_FP16
1 0 11 01 000 FCVTPS (scalar) — Half-precision to 64-bitFEAT_FP16
1 0 11 01 001 FCVTPU (scalar) — Half-precision to 64-bitFEAT_FP16
1 0 11 01 010 FCVTNS (scalar SIMD&FP) — Half-precision to 64-bitFEAT_FPRCVT
1 0 11 01 011 FCVTNU (scalar SIMD&FP) — Half-precision to 64-bitFEAT_FPRCVT
1 0 11 10 000 FCVTMS (scalar) — Half-precision to 64-bitFEAT_FP16
1 0 11 10 001 FCVTMU (scalar) — Half-precision to 64-bitFEAT_FP16
1 0 11 10 010 FCVTPS (scalar SIMD&FP) — Half-precision to 64-bitFEAT_FPRCVT
1 0 11 10 011 FCVTPU (scalar SIMD&FP) — Half-precision to 64-bitFEAT_FPRCVT
1 0 11 10 100 FCVTMS (scalar SIMD&FP) — Half-precision to 64-bitFEAT_FPRCVT
1 0 11 10 101 FCVTMU (scalar SIMD&FP) — Half-precision to 64-bitFEAT_FPRCVT
1 0 11 10 110 FCVTZS (scalar SIMD&FP) — Half-precision to 64-bitFEAT_FPRCVT
1 0 11 10 111 FCVTZU (scalar SIMD&FP) — Half-precision to 64-bitFEAT_FPRCVT
1 0 11 11 000 FCVTZS (scalar, integer) — Half-precision to 64-bitFEAT_FP16
1 0 11 11 001 FCVTZU (scalar, integer) — Half-precision to 64-bitFEAT_FP16
1 0 11 11 010 FCVTAS (scalar SIMD&FP) — Half-precision to 64-bitFEAT_FPRCVT
1 0 11 11 011 FCVTAU (scalar SIMD&FP) — Half-precision to 64-bitFEAT_FPRCVT
1 0 11 11 100 SCVTF (scalar SIMD&FP) — 64-bit to half-precisionFEAT_FPRCVT
1 0 11 11 101 UCVTF (scalar SIMD&FP) — 64-bit to half-precisionFEAT_FPRCVT

Floating-point data-processing (1 source)

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110ftype1opcode10000RnRd
Decode fields Instruction Details Feature
M S ftype opcode
0 0 1xxxxx UNALLOCATED-
0 0 0x 0101xx UNALLOCATED-
0 0 0x 011xxx UNALLOCATED-
0 0 00 000000 FMOV (register) — Single-precisionFEAT_FP
0 0 00 000001 FABS (scalar) — Single-precisionFEAT_FP
0 0 00 000010 FNEG (scalar) — Single-precisionFEAT_FP
0 0 00 000011 FSQRT (scalar) — Single-precisionFEAT_FP
0 0 00 0001x0 UNALLOCATED-
0 0 00 000101 FCVT — Single-precision to double-precisionFEAT_FP
0 0 00 000111 FCVT — Single-precision to half-precisionFEAT_FP
0 0 00 001000 FRINTN (scalar) — Single-precisionFEAT_FP
0 0 00 001001 FRINTP (scalar) — Single-precisionFEAT_FP
0 0 00 001010 FRINTM (scalar) — Single-precisionFEAT_FP
0 0 00 001011 FRINTZ (scalar) — Single-precisionFEAT_FP
0 0 00 001100 FRINTA (scalar) — Single-precisionFEAT_FP
0 0 00 001110 FRINTX (scalar) — Single-precisionFEAT_FP
0 0 00 001111 FRINTI (scalar) — Single-precisionFEAT_FP
0 0 00 010000 FRINT32Z (scalar) — Single-precisionFEAT_FRINTTS
0 0 00 010001 FRINT32X (scalar) — Single-precisionFEAT_FRINTTS
0 0 00 010010 FRINT64Z (scalar) — Single-precisionFEAT_FRINTTS
0 0 00 010011 FRINT64X (scalar) — Single-precisionFEAT_FRINTTS
0 0 01 000000 FMOV (register) — Double-precisionFEAT_FP
0 0 01 000001 FABS (scalar) — Double-precisionFEAT_FP
0 0 01 000010 FNEG (scalar) — Double-precisionFEAT_FP
0 0 01 000011 FSQRT (scalar) — Double-precisionFEAT_FP
0 0 01 000100 FCVT — Double-precision to single-precisionFEAT_FP
0 0 01 000101 UNALLOCATED-
0 0 01 000110 BFCVTFEAT_BF16
0 0 01 000111 FCVT — Double-precision to half-precisionFEAT_FP
0 0 01 001000 FRINTN (scalar) — Double-precisionFEAT_FP
0 0 01 001001 FRINTP (scalar) — Double-precisionFEAT_FP
0 0 01 001010 FRINTM (scalar) — Double-precisionFEAT_FP
0 0 01 001011 FRINTZ (scalar) — Double-precisionFEAT_FP
0 0 01 001100 FRINTA (scalar) — Double-precisionFEAT_FP
0 0 01 001110 FRINTX (scalar) — Double-precisionFEAT_FP
0 0 01 001111 FRINTI (scalar) — Double-precisionFEAT_FP
0 0 01 010000 FRINT32Z (scalar) — Double-precisionFEAT_FRINTTS
0 0 01 010001 FRINT32X (scalar) — Double-precisionFEAT_FRINTTS
0 0 01 010010 FRINT64Z (scalar) — Double-precisionFEAT_FRINTTS
0 0 01 010011 FRINT64X (scalar) — Double-precisionFEAT_FRINTTS
0 0 10 0xxxxx UNALLOCATED-
0 0 11 000000 FMOV (register) — Half-precisionFEAT_FP16
0 0 11 000001 FABS (scalar) — Half-precisionFEAT_FP16
0 0 11 000010 FNEG (scalar) — Half-precisionFEAT_FP16
0 0 11 000011 FSQRT (scalar) — Half-precisionFEAT_FP16
0 0 11 000100 FCVT — Half-precision to single-precisionFEAT_FP
0 0 11 000101 FCVT — Half-precision to double-precisionFEAT_FP
0 0 11 00011x UNALLOCATED-
0 0 11 001000 FRINTN (scalar) — Half-precisionFEAT_FP16
0 0 11 001001 FRINTP (scalar) — Half-precisionFEAT_FP16
0 0 11 001010 FRINTM (scalar) — Half-precisionFEAT_FP16
0 0 11 001011 FRINTZ (scalar) — Half-precisionFEAT_FP16
0 0 11 001100 FRINTA (scalar) — Half-precisionFEAT_FP16
0 0 11 001110 FRINTX (scalar) — Half-precisionFEAT_FP16
0 0 11 001111 FRINTI (scalar) — Half-precisionFEAT_FP16
0 0 11 01xxxx UNALLOCATED-
0 0 != 10 001101 UNALLOCATED-
0 1 UNALLOCATED-
1 UNALLOCATED-

Floating-point compare

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110ftype1Rmop1000Rnopcode2
Decode fields Instruction Details Feature
M S ftype op opcode2
0 0 00 xx001 UNALLOCATED-
0 0 00 xx01x UNALLOCATED-
0 0 00 xx1xx UNALLOCATED-
0 0 != 00 UNALLOCATED-
0 0 00 00 00000 FCMP — Single-precisionFEAT_FP
0 0 00 00 01000 FCMP — Single-precision, zeroFEAT_FP
0 0 00 00 10000 FCMPE — Single-precisionFEAT_FP
0 0 00 00 11000 FCMPE — Single-precision, zeroFEAT_FP
0 0 01 00 00000 FCMP — Double-precisionFEAT_FP
0 0 01 00 01000 FCMP — Double-precision, zeroFEAT_FP
0 0 01 00 10000 FCMPE — Double-precisionFEAT_FP
0 0 01 00 11000 FCMPE — Double-precision, zeroFEAT_FP
0 0 10 00 xx000 UNALLOCATED-
0 0 11 00 00000 FCMP — Half-precisionFEAT_FP16
0 0 11 00 01000 FCMP — Half-precision, zeroFEAT_FP16
0 0 11 00 10000 FCMPE — Half-precisionFEAT_FP16
0 0 11 00 11000 FCMPE — Half-precision, zeroFEAT_FP16
0 1 UNALLOCATED-
1 UNALLOCATED-

Floating-point immediate

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110ftype1imm8100imm5Rd
Decode fields Instruction Details Feature
M S ftype imm5
0 0 != 00000 UNALLOCATED-
0 0 00 00000 FMOV (scalar, immediate) — Single-precisionFEAT_FP
0 0 01 00000 FMOV (scalar, immediate) — Double-precisionFEAT_FP
0 0 10 00000 UNALLOCATED-
0 0 11 00000 FMOV (scalar, immediate) — Half-precisionFEAT_FP16
0 1 UNALLOCATED-
1 UNALLOCATED-

Floating-point conditional compare

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110ftype1Rmcond01Rnopnzcv
Decode fields Instruction Details Feature
M S ftype op
0 0 00 0 FCCMP — Single-precisionFEAT_FP
0 0 00 1 FCCMPE — Single-precisionFEAT_FP
0 0 01 0 FCCMP — Double-precisionFEAT_FP
0 0 01 1 FCCMPE — Double-precisionFEAT_FP
0 0 10 UNALLOCATED-
0 0 11 0 FCCMP — Half-precisionFEAT_FP16
0 0 11 1 FCCMPE — Half-precisionFEAT_FP16
0 1 UNALLOCATED-
1 UNALLOCATED-

Floating-point data-processing (2 source)

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110ftype1Rmopcode10RnRd
Decode fields Instruction Details Feature
M S ftype opcode
0 0 00 0000 FMUL (scalar) — Single-precisionFEAT_FP
0 0 00 0001 FDIV (scalar) — Single-precisionFEAT_FP
0 0 00 0010 FADD (scalar) — Single-precisionFEAT_FP
0 0 00 0011 FSUB (scalar) — Single-precisionFEAT_FP
0 0 00 0100 FMAX (scalar) — Single-precisionFEAT_FP
0 0 00 0101 FMIN (scalar) — Single-precisionFEAT_FP
0 0 00 0110 FMAXNM (scalar) — Single-precisionFEAT_FP
0 0 00 0111 FMINNM (scalar) — Single-precisionFEAT_FP
0 0 00 1000 FNMUL (scalar) — Single-precisionFEAT_FP
0 0 01 0000 FMUL (scalar) — Double-precisionFEAT_FP
0 0 01 0001 FDIV (scalar) — Double-precisionFEAT_FP
0 0 01 0010 FADD (scalar) — Double-precisionFEAT_FP
0 0 01 0011 FSUB (scalar) — Double-precisionFEAT_FP
0 0 01 0100 FMAX (scalar) — Double-precisionFEAT_FP
0 0 01 0101 FMIN (scalar) — Double-precisionFEAT_FP
0 0 01 0110 FMAXNM (scalar) — Double-precisionFEAT_FP
0 0 01 0111 FMINNM (scalar) — Double-precisionFEAT_FP
0 0 01 1000 FNMUL (scalar) — Double-precisionFEAT_FP
0 0 10 UNALLOCATED-
0 0 11 0000 FMUL (scalar) — Half-precisionFEAT_FP16
0 0 11 0001 FDIV (scalar) — Half-precisionFEAT_FP16
0 0 11 0010 FADD (scalar) — Half-precisionFEAT_FP16
0 0 11 0011 FSUB (scalar) — Half-precisionFEAT_FP16
0 0 11 0100 FMAX (scalar) — Half-precisionFEAT_FP16
0 0 11 0101 FMIN (scalar) — Half-precisionFEAT_FP16
0 0 11 0110 FMAXNM (scalar) — Half-precisionFEAT_FP16
0 0 11 0111 FMINNM (scalar) — Half-precisionFEAT_FP16
0 0 11 1000 FNMUL (scalar) — Half-precisionFEAT_FP16
0 0 != 10 1001 UNALLOCATED-
0 0 != 10 101x UNALLOCATED-
0 0 != 10 11xx UNALLOCATED-
0 1 UNALLOCATED-
1 UNALLOCATED-

Floating-point conditional select

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110ftype1Rmcond11RnRd
Decode fields Instruction Details Feature
M S ftype
0 0 00 FCSEL — Single-precisionFEAT_FP
0 0 01 FCSEL — Double-precisionFEAT_FP
0 0 10 UNALLOCATED-
0 0 11 FCSEL — Half-precisionFEAT_FP16
0 1 UNALLOCATED-
1 UNALLOCATED-

Floating-point data-processing (3 source)

The encodings in this section are decoded from Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11111ftypeo1Rmo0RaRnRd
Decode fields Instruction Details Feature
M S ftype o1 o0
0 0 00 0 0 FMADD — Single-precisionFEAT_FP
0 0 00 0 1 FMSUB — Single-precisionFEAT_FP
0 0 00 1 0 FNMADD — Single-precisionFEAT_FP
0 0 00 1 1 FNMSUB — Single-precisionFEAT_FP
0 0 01 0 0 FMADD — Double-precisionFEAT_FP
0 0 01 0 1 FMSUB — Double-precisionFEAT_FP
0 0 01 1 0 FNMADD — Double-precisionFEAT_FP
0 0 01 1 1 FNMSUB — Double-precisionFEAT_FP
0 0 10 UNALLOCATED-
0 0 11 0 0 FMADD — Half-precisionFEAT_FP16
0 0 11 0 1 FMSUB — Half-precisionFEAT_FP16
0 0 11 1 0 FNMADD — Half-precisionFEAT_FP16
0 0 11 1 1 FNMSUB — Half-precisionFEAT_FP16
0 1 UNALLOCATED-
1 UNALLOCATED-

Loads and Stores

The encodings in this section are decoded from A64 instruction set encoding.

313029282726252423222120191817161514131211109876543210
op01op10op2
Decode fieldsInstruction details
op0op1op2
0000 0 1xx1xxxxxxxxxxx UNALLOCATED
0001 1 1xx1xxxxxxxxxxx UNALLOCATED
0x00 0 00x1xxxxxxxxxxx Compare and swap pair
0x00 0 10x0xxxxxxxxxxx UNALLOCATED
0x00 0 11x0xxxxxxxxxxx Compare and swap pair (unprivileged)
0x00 1 00x000000xxxxxx Advanced SIMD load/store multiple structures
0x00 1 00x000001xxxxxx UNALLOCATED
0x00 1 01x0xxxxxxxxxxx Advanced SIMD load/store multiple structures (post-indexed)
0x00 1 0xx1xxxxxxxxxxx UNALLOCATED
0x00 1 10x10001xxxxxxx UNALLOCATED
0x00 1 10x1001xxxxxxxx UNALLOCATED
0x00 1 10x101xxxxxxxxx UNALLOCATED
0x00 1 10x11xxxxxxxxxx UNALLOCATED
0x00 1 10xx0000xxxxxxx Advanced SIMD load/store single structure
0x00 1 11xxxxxxxxxxxxx Advanced SIMD load/store single structure (post-indexed)
0x00 1 x0x00001xxxxxxx UNALLOCATED
0x00 1 x0x0001xxxxxxxx UNALLOCATED
0x00 1 x0x001xxxxxxxxx UNALLOCATED
0x00 1 x0x01xxxxxxxxxx UNALLOCATED
0x01 0 1xx0xxxxxxxxx11 UNALLOCATED
0x01 0 1xx1xxxxx000010 RCW compare and swap
0x01 0 1xx1xxxxx000011 RCW compare and swap pair
0x01 0 1xx1xxxxx00011x UNALLOCATED
0x01 0 1xx1xxxxx001x1x UNALLOCATED
0x01 0 1xx1xxxxx01xx1x UNALLOCATED
0x01 0 1xx1xxxxx1xxx1x UNALLOCATED
0x01 0 1xx1xxxxxxxxx00 128-bit atomic memory operations
0x01 0 1xx1xxxxxxxxx01 Atomic memory operations (unprivileged)
1001 0 1xx0xxxxxxxxx11 UNALLOCATED
1001 1 1xx1xxxxxxxxxxx UNALLOCATED
100x 0 1xx1xxxxxxxxxxx UNALLOCATED
1101 0 1000111110xxx11 GCS load/store
1101 0 1100111110xxx11 UNALLOCATED
1101 0 1x000xxxxxxxx11 UNALLOCATED
1101 0 1x0010xxxxxxx11 UNALLOCATED
1101 0 1x00110xxxxxx11 UNALLOCATED
1101 0 1x001110xxxxx11 UNALLOCATED
1101 0 1x0011110xxxx11 UNALLOCATED
1101 0 1x00111111xxx11 UNALLOCATED
1101 0 1x10xxxxxxxxx11 UNALLOCATED
1101 0 1xx1xxxxxxxxxxx Load/store memory tags
1x00 0 00x1xxxxxxxxxxx Load/store exclusive pair
1x00 0 10x0xxxxxxxxxxx Load/store exclusive register (unprivileged)
1x00 0 11x0xxxxxxxxxxx Compare and swap (unprivileged)
1x00 1 UNALLOCATED
x100 0 1xx1xxxxxxxxxxx UNALLOCATED
x101 1 1xx1xxxxxxxxxxx UNALLOCATED
xx00 0 00x0xxxxxxxxxxx Load/store exclusive register
xx00 0 01x0xxxxxxxxxxx Load/store ordered
xx00 0 01x1xxxxxxxxxxx Compare and swap
xx01 0 10x0xxxxxxxxx10 LDIAPP/STILP
xx01 0 11x000000000010 LDAPR/STLR (writeback)
xx01 0 11x000000000110 UNALLOCATED
xx01 0 11x000000001x10 UNALLOCATED
xx01 0 11x00000001xx10 UNALLOCATED
xx01 0 11x0000001xxx10 UNALLOCATED
xx01 0 11x000001xxxx10 UNALLOCATED
xx01 0 11x00001xxxxx10 UNALLOCATED
xx01 0 11x0001xxxxxx10 UNALLOCATED
xx01 0 11x001xxxxxxx10 UNALLOCATED
xx01 0 11x01xxxxxxxx10 UNALLOCATED
xx01 0 1xx0xxxxxxxxx00 LDAPR/STLR (unscaled immediate)
xx01 1 1xx0xxxxxxxxx00 UNALLOCATED
xx01 1 1xx0xxxxxxxxx10 LDAPR/STLR (SIMD&FP)
xx01 1 1xx0xxxxxxxxx11 UNALLOCATED
xx01 0xxxxxxxxxxxxxx Load register (literal)
xx01 1xx0xxxxxxxxx01 Memory Copy and Memory Set
xx10 00xxxxxxxxxxxxx Load/store no-allocate pair (offset)
xx10 01xxxxxxxxxxxxx Load/store register pair (post-indexed)
xx10 10xxxxxxxxxxxxx Load/store register pair (offset)
xx10 11xxxxxxxxxxxxx Load/store register pair (pre-indexed)
xx11 0xx0xxxxxxxxx00 Load/store register (unscaled immediate)
xx11 0xx0xxxxxxxxx01 Load/store register (immediate post-indexed)
xx11 0xx0xxxxxxxxx10 Load/store register (unprivileged)
xx11 0xx0xxxxxxxxx11 Load/store register (immediate pre-indexed)
xx11 0xx1xxxxxxxxx00 Atomic memory operations
xx11 0xx1xxxxxxxxx10 Load/store register (register offset)
xx11 0xx1xxxxxxxxxx1 Load/store register (pac)
xx11 1xxxxxxxxxxxxxx Load/store register (unsigned immediate)

Compare and swap pair

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
0sz0010000L1Rso0Rt2RnRt
Decode fields Instruction Details Feature
sz L o0 Rt2
!= 11111 UNALLOCATED-
0 0 0 11111 CASP, CASPA, CASPAL, CASPL — 32-bit CASPFEAT_LSE
0 0 1 11111 CASP, CASPA, CASPAL, CASPL — 32-bit CASPLFEAT_LSE
0 1 0 11111 CASP, CASPA, CASPAL, CASPL — 32-bit CASPAFEAT_LSE
0 1 1 11111 CASP, CASPA, CASPAL, CASPL — 32-bit CASPALFEAT_LSE
1 0 0 11111 CASP, CASPA, CASPAL, CASPL — 64-bit CASPFEAT_LSE
1 0 1 11111 CASP, CASPA, CASPAL, CASPL — 64-bit CASPLFEAT_LSE
1 1 0 11111 CASP, CASPA, CASPAL, CASPL — 64-bit CASPAFEAT_LSE
1 1 1 11111 CASP, CASPA, CASPAL, CASPL — 64-bit CASPALFEAT_LSE

Compare and swap pair (unprivileged)

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
0sz0010011L0Rso0Rt2RnRt
Decode fields Instruction Details Feature
sz L o0 Rt2
0 UNALLOCATED-
1 != 11111 UNALLOCATED-
1 0 0 11111 CASPT, CASPAT, CASPALT, CASPLT — CASPTFEAT_LSUI
1 0 1 11111 CASPT, CASPAT, CASPALT, CASPLT — CASPLTFEAT_LSUI
1 1 0 11111 CASPT, CASPAT, CASPALT, CASPLT — CASPATFEAT_LSUI
1 1 1 11111 CASPT, CASPAT, CASPALT, CASPLT — CASPALTFEAT_LSUI

Advanced SIMD load/store multiple structures

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
0Q0011000L000000opcodesizeRnRt
Decode fields Instruction Details Feature
L opcode
x0x1 UNALLOCATED-
0101 UNALLOCATED-
11xx UNALLOCATED-
0 0000 ST4 (multiple structures)FEAT_AdvSIMD
0 0010 ST1 (multiple structures) — Four registersFEAT_AdvSIMD
0 0100 ST3 (multiple structures)FEAT_AdvSIMD
0 0110 ST1 (multiple structures) — Three registersFEAT_AdvSIMD
0 0111 ST1 (multiple structures) — One registerFEAT_AdvSIMD
0 1000 ST2 (multiple structures)FEAT_AdvSIMD
0 1010 ST1 (multiple structures) — Two registersFEAT_AdvSIMD
1 0000 LD4 (multiple structures)FEAT_AdvSIMD
1 0010 LD1 (multiple structures) — Four registersFEAT_AdvSIMD
1 0100 LD3 (multiple structures)FEAT_AdvSIMD
1 0110 LD1 (multiple structures) — Three registersFEAT_AdvSIMD
1 0111 LD1 (multiple structures) — One registerFEAT_AdvSIMD
1 1000 LD2 (multiple structures)FEAT_AdvSIMD
1 1010 LD1 (multiple structures) — Two registersFEAT_AdvSIMD

Advanced SIMD load/store multiple structures (post-indexed)

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
0Q0011001L0RmopcodesizeRnRt
Decode fields Instruction Details Feature
L Rm opcode
x0x1 UNALLOCATED-
0101 UNALLOCATED-
11xx UNALLOCATED-
0 11111 0000 ST4 (multiple structures) — Immediate offsetFEAT_AdvSIMD
0 11111 0010 ST1 (multiple structures) — Four registers, immediate offsetFEAT_AdvSIMD
0 11111 0100 ST3 (multiple structures) — Immediate offsetFEAT_AdvSIMD
0 11111 0110 ST1 (multiple structures) — Three registers, immediate offsetFEAT_AdvSIMD
0 11111 0111 ST1 (multiple structures) — One register, immediate offsetFEAT_AdvSIMD
0 11111 1000 ST2 (multiple structures) — Immediate offsetFEAT_AdvSIMD
0 11111 1010 ST1 (multiple structures) — Two registers, immediate offsetFEAT_AdvSIMD
0 != 11111 0000 ST4 (multiple structures) — Register offsetFEAT_AdvSIMD
0 != 11111 0010 ST1 (multiple structures) — Four registers, register offsetFEAT_AdvSIMD
0 != 11111 0100 ST3 (multiple structures) — Register offsetFEAT_AdvSIMD
0 != 11111 0110 ST1 (multiple structures) — Three registers, register offsetFEAT_AdvSIMD
0 != 11111 0111 ST1 (multiple structures) — One register, register offsetFEAT_AdvSIMD
0 != 11111 1000 ST2 (multiple structures) — Register offsetFEAT_AdvSIMD
0 != 11111 1010 ST1 (multiple structures) — Two registers, register offsetFEAT_AdvSIMD
1 11111 0000 LD4 (multiple structures) — Immediate offsetFEAT_AdvSIMD
1 11111 0010 LD1 (multiple structures) — Four registers, immediate offsetFEAT_AdvSIMD
1 11111 0100 LD3 (multiple structures) — Immediate offsetFEAT_AdvSIMD
1 11111 0110 LD1 (multiple structures) — Three registers, immediate offsetFEAT_AdvSIMD
1 11111 0111 LD1 (multiple structures) — One register, immediate offsetFEAT_AdvSIMD
1 11111 1000 LD2 (multiple structures) — Immediate offsetFEAT_AdvSIMD
1 11111 1010 LD1 (multiple structures) — Two registers, immediate offsetFEAT_AdvSIMD
1 != 11111 0000 LD4 (multiple structures) — Register offsetFEAT_AdvSIMD
1 != 11111 0010 LD1 (multiple structures) — Four registers, register offsetFEAT_AdvSIMD
1 != 11111 0100 LD3 (multiple structures) — Register offsetFEAT_AdvSIMD
1 != 11111 0110 LD1 (multiple structures) — Three registers, register offsetFEAT_AdvSIMD
1 != 11111 0111 LD1 (multiple structures) — One register, register offsetFEAT_AdvSIMD
1 != 11111 1000 LD2 (multiple structures) — Register offsetFEAT_AdvSIMD
1 != 11111 1010 LD1 (multiple structures) — Two registers, register offsetFEAT_AdvSIMD

Advanced SIMD load/store single structure

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
0Q0011010LR0000o2opcodeSsizeRnRt
Decode fields Instruction Details Feature
L R o2 opcode S size
0 01x x1 UNALLOCATED-
0 10x 1x UNALLOCATED-
0 10x 1 01 UNALLOCATED-
0 1 100 != 01 UNALLOCATED-
0 1 100 1 01 UNALLOCATED-
0 1 != 100 UNALLOCATED-
1 1 UNALLOCATED-
0 0 11x UNALLOCATED-
0 0 0 000 ST1 (single structure) — 8-bitFEAT_AdvSIMD
0 0 0 001 ST3 (single structure) — 8-bitFEAT_AdvSIMD
0 0 0 010 x0 ST1 (single structure) — 16-bitFEAT_AdvSIMD
0 0 0 011 x0 ST3 (single structure) — 16-bitFEAT_AdvSIMD
0 0 0 100 00 ST1 (single structure) — 32-bitFEAT_AdvSIMD
0 0 0 100 0 01 ST1 (single structure) — 64-bitFEAT_AdvSIMD
0 0 0 101 00 ST3 (single structure) — 32-bitFEAT_AdvSIMD
0 0 0 101 0 01 ST3 (single structure) — 64-bitFEAT_AdvSIMD
0 0 1 100 0 01 STL1 (SIMD&FP)FEAT_AdvSIMD && FEAT_LRCPC3
0 1 0 000 ST2 (single structure) — 8-bitFEAT_AdvSIMD
0 1 0 001 ST4 (single structure) — 8-bitFEAT_AdvSIMD
0 1 0 010 x0 ST2 (single structure) — 16-bitFEAT_AdvSIMD
0 1 0 011 x0 ST4 (single structure) — 16-bitFEAT_AdvSIMD
0 1 0 100 00 ST2 (single structure) — 32-bitFEAT_AdvSIMD
0 1 0 100 0 01 ST2 (single structure) — 64-bitFEAT_AdvSIMD
0 1 0 101 00 ST4 (single structure) — 32-bitFEAT_AdvSIMD
0 1 0 101 0 01 ST4 (single structure) — 64-bitFEAT_AdvSIMD
1 0 11x 1 UNALLOCATED-
1 0 0 000 LD1 (single structure) — 8-bitFEAT_AdvSIMD
1 0 0 001 LD3 (single structure) — 8-bitFEAT_AdvSIMD
1 0 0 010 x0 LD1 (single structure) — 16-bitFEAT_AdvSIMD
1 0 0 011 x0 LD3 (single structure) — 16-bitFEAT_AdvSIMD
1 0 0 100 00 LD1 (single structure) — 32-bitFEAT_AdvSIMD
1 0 0 100 0 01 LD1 (single structure) — 64-bitFEAT_AdvSIMD
1 0 0 101 00 LD3 (single structure) — 32-bitFEAT_AdvSIMD
1 0 0 101 0 01 LD3 (single structure) — 64-bitFEAT_AdvSIMD
1 0 0 110 0 LD1RFEAT_AdvSIMD
1 0 0 111 0 LD3RFEAT_AdvSIMD
1 0 1 100 0 01 LDAP1 (SIMD&FP)FEAT_AdvSIMD && FEAT_LRCPC3
1 1 0 000 LD2 (single structure) — 8-bitFEAT_AdvSIMD
1 1 0 001 LD4 (single structure) — 8-bitFEAT_AdvSIMD
1 1 0 010 x0 LD2 (single structure) — 16-bitFEAT_AdvSIMD
1 1 0 011 x0 LD4 (single structure) — 16-bitFEAT_AdvSIMD
1 1 0 100 00 LD2 (single structure) — 32-bitFEAT_AdvSIMD
1 1 0 100 0 01 LD2 (single structure) — 64-bitFEAT_AdvSIMD
1 1 0 101 00 LD4 (single structure) — 32-bitFEAT_AdvSIMD
1 1 0 101 0 01 LD4 (single structure) — 64-bitFEAT_AdvSIMD
1 1 0 110 0 LD2RFEAT_AdvSIMD
1 1 0 111 0 LD4RFEAT_AdvSIMD

Advanced SIMD load/store single structure (post-indexed)

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
0Q0011011LRRmopcodeSsizeRnRt
Decode fields Instruction Details Feature
L R Rm opcode S size
01x x1 UNALLOCATED-
10x 1x UNALLOCATED-
10x 1 01 UNALLOCATED-
0 11x UNALLOCATED-
0 0 11111 000 ST1 (single structure) — 8-bit, immediate offsetFEAT_AdvSIMD
0 0 11111 001 ST3 (single structure) — 8-bit, immediate offsetFEAT_AdvSIMD
0 0 11111 010 x0 ST1 (single structure) — 16-bit, immediate offsetFEAT_AdvSIMD
0 0 11111 011 x0 ST3 (single structure) — 16-bit, immediate offsetFEAT_AdvSIMD
0 0 11111 100 00 ST1 (single structure) — 32-bit, immediate offsetFEAT_AdvSIMD
0 0 11111 100 0 01 ST1 (single structure) — 64-bit, immediate offsetFEAT_AdvSIMD
0 0 11111 101 00 ST3 (single structure) — 32-bit, immediate offsetFEAT_AdvSIMD
0 0 11111 101 0 01 ST3 (single structure) — 64-bit, immediate offsetFEAT_AdvSIMD
0 0 != 11111 000 ST1 (single structure) — 8-bit, register offsetFEAT_AdvSIMD
0 0 != 11111 001 ST3 (single structure) — 8-bit, register offsetFEAT_AdvSIMD
0 0 != 11111 010 x0 ST1 (single structure) — 16-bit, register offsetFEAT_AdvSIMD
0 0 != 11111 011 x0 ST3 (single structure) — 16-bit, register offsetFEAT_AdvSIMD
0 0 != 11111 100 00 ST1 (single structure) — 32-bit, register offsetFEAT_AdvSIMD
0 0 != 11111 100 0 01 ST1 (single structure) — 64-bit, register offsetFEAT_AdvSIMD
0 0 != 11111 101 00 ST3 (single structure) — 32-bit, register offsetFEAT_AdvSIMD
0 0 != 11111 101 0 01 ST3 (single structure) — 64-bit, register offsetFEAT_AdvSIMD
0 1 11111 000 ST2 (single structure) — 8-bit, immediate offsetFEAT_AdvSIMD
0 1 11111 001 ST4 (single structure) — 8-bit, immediate offsetFEAT_AdvSIMD
0 1 11111 010 x0 ST2 (single structure) — 16-bit, immediate offsetFEAT_AdvSIMD
0 1 11111 011 x0 ST4 (single structure) — 16-bit, immediate offsetFEAT_AdvSIMD
0 1 11111 100 00 ST2 (single structure) — 32-bit, immediate offsetFEAT_AdvSIMD
0 1 11111 100 0 01 ST2 (single structure) — 64-bit, immediate offsetFEAT_AdvSIMD
0 1 11111 101 00 ST4 (single structure) — 32-bit, immediate offsetFEAT_AdvSIMD
0 1 11111 101 0 01 ST4 (single structure) — 64-bit, immediate offsetFEAT_AdvSIMD
0 1 != 11111 000 ST2 (single structure) — 8-bit, register offsetFEAT_AdvSIMD
0 1 != 11111 001 ST4 (single structure) — 8-bit, register offsetFEAT_AdvSIMD
0 1 != 11111 010 x0 ST2 (single structure) — 16-bit, register offsetFEAT_AdvSIMD
0 1 != 11111 011 x0 ST4 (single structure) — 16-bit, register offsetFEAT_AdvSIMD
0 1 != 11111 100 00 ST2 (single structure) — 32-bit, register offsetFEAT_AdvSIMD
0 1 != 11111 100 0 01 ST2 (single structure) — 64-bit, register offsetFEAT_AdvSIMD
0 1 != 11111 101 00 ST4 (single structure) — 32-bit, register offsetFEAT_AdvSIMD
0 1 != 11111 101 0 01 ST4 (single structure) — 64-bit, register offsetFEAT_AdvSIMD
1 11x 1 UNALLOCATED-
1 0 11111 000 LD1 (single structure) — 8-bit, immediate offsetFEAT_AdvSIMD
1 0 11111 001 LD3 (single structure) — 8-bit, immediate offsetFEAT_AdvSIMD
1 0 11111 010 x0 LD1 (single structure) — 16-bit, immediate offsetFEAT_AdvSIMD
1 0 11111 011 x0 LD3 (single structure) — 16-bit, immediate offsetFEAT_AdvSIMD
1 0 11111 100 00 LD1 (single structure) — 32-bit, immediate offsetFEAT_AdvSIMD
1 0 11111 100 0 01 LD1 (single structure) — 64-bit, immediate offsetFEAT_AdvSIMD
1 0 11111 101 00 LD3 (single structure) — 32-bit, immediate offsetFEAT_AdvSIMD
1 0 11111 101 0 01 LD3 (single structure) — 64-bit, immediate offsetFEAT_AdvSIMD
1 0 11111 110 0 LD1R — Immediate offsetFEAT_AdvSIMD
1 0 11111 111 0 LD3R — Immediate offsetFEAT_AdvSIMD
1 0 != 11111 000 LD1 (single structure) — 8-bit, register offsetFEAT_AdvSIMD
1 0 != 11111 001 LD3 (single structure) — 8-bit, register offsetFEAT_AdvSIMD
1 0 != 11111 010 x0 LD1 (single structure) — 16-bit, register offsetFEAT_AdvSIMD
1 0 != 11111 011 x0 LD3 (single structure) — 16-bit, register offsetFEAT_AdvSIMD
1 0 != 11111 100 00 LD1 (single structure) — 32-bit, register offsetFEAT_AdvSIMD
1 0 != 11111 100 0 01 LD1 (single structure) — 64-bit, register offsetFEAT_AdvSIMD
1 0 != 11111 101 00 LD3 (single structure) — 32-bit, register offsetFEAT_AdvSIMD
1 0 != 11111 101 0 01 LD3 (single structure) — 64-bit, register offsetFEAT_AdvSIMD
1 0 != 11111 110 0 LD1R — Register offsetFEAT_AdvSIMD
1 0 != 11111 111 0 LD3R — Register offsetFEAT_AdvSIMD
1 1 11111 000 LD2 (single structure) — 8-bit, immediate offsetFEAT_AdvSIMD
1 1 11111 001 LD4 (single structure) — 8-bit, immediate offsetFEAT_AdvSIMD
1 1 11111 010 x0 LD2 (single structure) — 16-bit, immediate offsetFEAT_AdvSIMD
1 1 11111 011 x0 LD4 (single structure) — 16-bit, immediate offsetFEAT_AdvSIMD
1 1 11111 100 00 LD2 (single structure) — 32-bit, immediate offsetFEAT_AdvSIMD
1 1 11111 100 0 01 LD2 (single structure) — 64-bit, immediate offsetFEAT_AdvSIMD
1 1 11111 101 00 LD4 (single structure) — 32-bit, immediate offsetFEAT_AdvSIMD
1 1 11111 101 0 01 LD4 (single structure) — 64-bit, immediate offsetFEAT_AdvSIMD
1 1 11111 110 0 LD2R — Immediate offsetFEAT_AdvSIMD
1 1 11111 111 0 LD4R — Immediate offsetFEAT_AdvSIMD
1 1 != 11111 000 LD2 (single structure) — 8-bit, register offsetFEAT_AdvSIMD
1 1 != 11111 001 LD4 (single structure) — 8-bit, register offsetFEAT_AdvSIMD
1 1 != 11111 010 x0 LD2 (single structure) — 16-bit, register offsetFEAT_AdvSIMD
1 1 != 11111 011 x0 LD4 (single structure) — 16-bit, register offsetFEAT_AdvSIMD
1 1 != 11111 100 00 LD2 (single structure) — 32-bit, register offsetFEAT_AdvSIMD
1 1 != 11111 100 0 01 LD2 (single structure) — 64-bit, register offsetFEAT_AdvSIMD
1 1 != 11111 101 00 LD4 (single structure) — 32-bit, register offsetFEAT_AdvSIMD
1 1 != 11111 101 0 01 LD4 (single structure) — 64-bit, register offsetFEAT_AdvSIMD
1 1 != 11111 110 0 LD2R — Register offsetFEAT_AdvSIMD
1 1 != 11111 111 0 LD4R — Register offsetFEAT_AdvSIMD

RCW compare and swap

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
0S011001AR1Rs000010RnRt
Decode fields Instruction Details Feature
S A R
0 0 0 RCWCAS, RCWCASA, RCWCASAL, RCWCASL — RCWCASFEAT_THE
0 0 1 RCWCAS, RCWCASA, RCWCASAL, RCWCASL — RCWCASLFEAT_THE
0 1 0 RCWCAS, RCWCASA, RCWCASAL, RCWCASL — RCWCASAFEAT_THE
0 1 1 RCWCAS, RCWCASA, RCWCASAL, RCWCASL — RCWCASALFEAT_THE
1 0 0 RCWSCAS, RCWSCASA, RCWSCASAL, RCWSCASL — RCWSCASFEAT_THE
1 0 1 RCWSCAS, RCWSCASA, RCWSCASAL, RCWSCASL — RCWSCASLFEAT_THE
1 1 0 RCWSCAS, RCWSCASA, RCWSCASAL, RCWSCASL — RCWSCASAFEAT_THE
1 1 1 RCWSCAS, RCWSCASA, RCWSCASAL, RCWSCASL — RCWSCASALFEAT_THE

RCW compare and swap pair

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
0S011001AR1Rs000011RnRt
Decode fields Instruction Details Feature
S A R
0 0 0 RCWCASP, RCWCASPA, RCWCASPAL, RCWCASPL — RCWCASPFEAT_D128 && FEAT_THE
0 0 1 RCWCASP, RCWCASPA, RCWCASPAL, RCWCASPL — RCWCASPLFEAT_D128 && FEAT_THE
0 1 0 RCWCASP, RCWCASPA, RCWCASPAL, RCWCASPL — RCWCASPAFEAT_D128 && FEAT_THE
0 1 1 RCWCASP, RCWCASPA, RCWCASPAL, RCWCASPL — RCWCASPALFEAT_D128 && FEAT_THE
1 0 0 RCWSCASP, RCWSCASPA, RCWSCASPAL, RCWSCASPL — RCWSCASPFEAT_D128 && FEAT_THE
1 0 1 RCWSCASP, RCWSCASPA, RCWSCASPAL, RCWSCASPL — RCWSCASPLFEAT_D128 && FEAT_THE
1 1 0 RCWSCASP, RCWSCASPA, RCWSCASPAL, RCWSCASPL — RCWSCASPAFEAT_D128 && FEAT_THE
1 1 1 RCWSCASP, RCWSCASPA, RCWSCASPAL, RCWSCASPL — RCWSCASPALFEAT_D128 && FEAT_THE

128-bit atomic memory operations

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
0S011001AR1Rt2o3opc00RnRt
Decode fields Instruction Details Feature
S A R o3 opc
1xx UNALLOCATED-
0 0 0x0 UNALLOCATED-
0 0 0 0 001 LDCLRP, LDCLRPA, LDCLRPAL, LDCLRPL — LDCLRPFEAT_LSE128
0 0 0 0 011 LDSETP, LDSETPA, LDSETPAL, LDSETPL — LDSETPFEAT_LSE128
0 0 0 1 000 SWPP, SWPPA, SWPPAL, SWPPL — SWPPFEAT_LSE128
0 0 0 1 001 RCWCLRP, RCWCLRPA, RCWCLRPAL, RCWCLRPL — RCWCLRPFEAT_D128 && FEAT_THE
0 0 0 1 010 RCWSWPP, RCWSWPPA, RCWSWPPAL, RCWSWPPL — RCWSWPPFEAT_D128 && FEAT_THE
0 0 0 1 011 RCWSETP, RCWSETPA, RCWSETPAL, RCWSETPL — RCWSETPFEAT_D128 && FEAT_THE
0 0 1 0 001 LDCLRP, LDCLRPA, LDCLRPAL, LDCLRPL — LDCLRPLFEAT_LSE128
0 0 1 0 011 LDSETP, LDSETPA, LDSETPAL, LDSETPL — LDSETPLFEAT_LSE128
0 0 1 1 000 SWPP, SWPPA, SWPPAL, SWPPL — SWPPLFEAT_LSE128
0 0 1 1 001 RCWCLRP, RCWCLRPA, RCWCLRPAL, RCWCLRPL — RCWCLRPLFEAT_D128 && FEAT_THE
0 0 1 1 010 RCWSWPP, RCWSWPPA, RCWSWPPAL, RCWSWPPL — RCWSWPPLFEAT_D128 && FEAT_THE
0 0 1 1 011 RCWSETP, RCWSETPA, RCWSETPAL, RCWSETPL — RCWSETPLFEAT_D128 && FEAT_THE
0 1 0 0 001 LDCLRP, LDCLRPA, LDCLRPAL, LDCLRPL — LDCLRPAFEAT_LSE128
0 1 0 0 011 LDSETP, LDSETPA, LDSETPAL, LDSETPL — LDSETPAFEAT_LSE128
0 1 0 1 000 SWPP, SWPPA, SWPPAL, SWPPL — SWPPAFEAT_LSE128
0 1 0 1 001 RCWCLRP, RCWCLRPA, RCWCLRPAL, RCWCLRPL — RCWCLRPAFEAT_D128 && FEAT_THE
0 1 0 1 010 RCWSWPP, RCWSWPPA, RCWSWPPAL, RCWSWPPL — RCWSWPPAFEAT_D128 && FEAT_THE
0 1 0 1 011 RCWSETP, RCWSETPA, RCWSETPAL, RCWSETPL — RCWSETPAFEAT_D128 && FEAT_THE
0 1 1 0 001 LDCLRP, LDCLRPA, LDCLRPAL, LDCLRPL — LDCLRPALFEAT_LSE128
0 1 1 0 011 LDSETP, LDSETPA, LDSETPAL, LDSETPL — LDSETPALFEAT_LSE128
0 1 1 1 000 SWPP, SWPPA, SWPPAL, SWPPL — SWPPALFEAT_LSE128
0 1 1 1 001 RCWCLRP, RCWCLRPA, RCWCLRPAL, RCWCLRPL — RCWCLRPALFEAT_D128 && FEAT_THE
0 1 1 1 010 RCWSWPP, RCWSWPPA, RCWSWPPAL, RCWSWPPL — RCWSWPPALFEAT_D128 && FEAT_THE
0 1 1 1 011 RCWSETP, RCWSETPA, RCWSETPAL, RCWSETPL — RCWSETPALFEAT_D128 && FEAT_THE
1 0 0xx UNALLOCATED-
1 1 000 UNALLOCATED-
1 0 0 1 001 RCWSCLRP, RCWSCLRPA, RCWSCLRPAL, RCWSCLRPL — RCWSCLRPFEAT_D128 && FEAT_THE
1 0 0 1 010 RCWSSWPP, RCWSSWPPA, RCWSSWPPAL, RCWSSWPPL — RCWSSWPPFEAT_D128 && FEAT_THE
1 0 0 1 011 RCWSSETP, RCWSSETPA, RCWSSETPAL, RCWSSETPL — RCWSSETPFEAT_D128 && FEAT_THE
1 0 1 1 001 RCWSCLRP, RCWSCLRPA, RCWSCLRPAL, RCWSCLRPL — RCWSCLRPLFEAT_D128 && FEAT_THE
1 0 1 1 010 RCWSSWPP, RCWSSWPPA, RCWSSWPPAL, RCWSSWPPL — RCWSSWPPLFEAT_D128 && FEAT_THE
1 0 1 1 011 RCWSSETP, RCWSSETPA, RCWSSETPAL, RCWSSETPL — RCWSSETPLFEAT_D128 && FEAT_THE
1 1 0 1 001 RCWSCLRP, RCWSCLRPA, RCWSCLRPAL, RCWSCLRPL — RCWSCLRPAFEAT_D128 && FEAT_THE
1 1 0 1 010 RCWSSWPP, RCWSSWPPA, RCWSSWPPAL, RCWSSWPPL — RCWSSWPPAFEAT_D128 && FEAT_THE
1 1 0 1 011 RCWSSETP, RCWSSETPA, RCWSSETPAL, RCWSSETPL — RCWSSETPAFEAT_D128 && FEAT_THE
1 1 1 1 001 RCWSCLRP, RCWSCLRPA, RCWSCLRPAL, RCWSCLRPL — RCWSCLRPALFEAT_D128 && FEAT_THE
1 1 1 1 010 RCWSSWPP, RCWSSWPPA, RCWSSWPPAL, RCWSSWPPL — RCWSSWPPALFEAT_D128 && FEAT_THE
1 1 1 1 011 RCWSSETP, RCWSSETPA, RCWSSETPAL, RCWSSETPL — RCWSSETPALFEAT_D128 && FEAT_THE

Atomic memory operations (unprivileged)

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
0sz011001AR1Rso3opc01RnRt
Decode fields Instruction Details Feature
sz A R o3 opc
010 UNALLOCATED-
1xx UNALLOCATED-
1 0x1 UNALLOCATED-
0 0 0 0 000 LDTADD, LDTADDA, LDTADDAL, LDTADDL — 32-bit no memory orderingFEAT_LSUI
0 0 0 0 001 LDTCLR, LDTCLRA, LDTCLRAL, LDTCLRL — 32-bit no memory orderingFEAT_LSUI
0 0 0 0 011 LDTSET, LDTSETA, LDTSETAL, LDTSETL — 32-bit no memory orderingFEAT_LSUI
0 0 0 1 000 SWPT, SWPTA, SWPTAL, SWPTL — 32-bit SWPTFEAT_LSUI
0 0 1 0 000 LDTADD, LDTADDA, LDTADDAL, LDTADDL — 32-bit releaseFEAT_LSUI
0 0 1 0 001 LDTCLR, LDTCLRA, LDTCLRAL, LDTCLRL — 32-bit releaseFEAT_LSUI
0 0 1 0 011 LDTSET, LDTSETA, LDTSETAL, LDTSETL — 32-bit releaseFEAT_LSUI
0 0 1 1 000 SWPT, SWPTA, SWPTAL, SWPTL — 32-bit SWPTLFEAT_LSUI
0 1 0 0 000 LDTADD, LDTADDA, LDTADDAL, LDTADDL — 32-bit acquireFEAT_LSUI
0 1 0 0 001 LDTCLR, LDTCLRA, LDTCLRAL, LDTCLRL — 32-bit acquireFEAT_LSUI
0 1 0 0 011 LDTSET, LDTSETA, LDTSETAL, LDTSETL — 32-bit acquireFEAT_LSUI
0 1 0 1 000 SWPT, SWPTA, SWPTAL, SWPTL — 32-bit SWPTAFEAT_LSUI
0 1 1 0 000 LDTADD, LDTADDA, LDTADDAL, LDTADDL — 32-bit acquire-releaseFEAT_LSUI
0 1 1 0 001 LDTCLR, LDTCLRA, LDTCLRAL, LDTCLRL — 32-bit acquire-releaseFEAT_LSUI
0 1 1 0 011 LDTSET, LDTSETA, LDTSETAL, LDTSETL — 32-bit acquire-releaseFEAT_LSUI
0 1 1 1 000 SWPT, SWPTA, SWPTAL, SWPTL — 32-bit SWPTALFEAT_LSUI
1 0 0 0 000 LDTADD, LDTADDA, LDTADDAL, LDTADDL — 64-bit no memory orderingFEAT_LSUI
1 0 0 0 001 LDTCLR, LDTCLRA, LDTCLRAL, LDTCLRL — 64-bit no memory orderingFEAT_LSUI
1 0 0 0 011 LDTSET, LDTSETA, LDTSETAL, LDTSETL — 64-bit no memory orderingFEAT_LSUI
1 0 0 1 000 SWPT, SWPTA, SWPTAL, SWPTL — 64-bit SWPTFEAT_LSUI
1 0 1 0 000 LDTADD, LDTADDA, LDTADDAL, LDTADDL — 64-bit releaseFEAT_LSUI
1 0 1 0 001 LDTCLR, LDTCLRA, LDTCLRAL, LDTCLRL — 64-bit releaseFEAT_LSUI
1 0 1 0 011 LDTSET, LDTSETA, LDTSETAL, LDTSETL — 64-bit releaseFEAT_LSUI
1 0 1 1 000 SWPT, SWPTA, SWPTAL, SWPTL — 64-bit SWPTLFEAT_LSUI
1 1 0 0 000 LDTADD, LDTADDA, LDTADDAL, LDTADDL — 64-bit acquireFEAT_LSUI
1 1 0 0 001 LDTCLR, LDTCLRA, LDTCLRAL, LDTCLRL — 64-bit acquireFEAT_LSUI
1 1 0 0 011 LDTSET, LDTSETA, LDTSETAL, LDTSETL — 64-bit acquireFEAT_LSUI
1 1 0 1 000 SWPT, SWPTA, SWPTAL, SWPTL — 64-bit SWPTAFEAT_LSUI
1 1 1 0 000 LDTADD, LDTADDA, LDTADDAL, LDTADDL — 64-bit acquire-releaseFEAT_LSUI
1 1 1 0 001 LDTCLR, LDTCLRA, LDTCLRAL, LDTCLRL — 64-bit acquire-releaseFEAT_LSUI
1 1 1 0 011 LDTSET, LDTSETA, LDTSETAL, LDTSETL — 64-bit acquire-releaseFEAT_LSUI
1 1 1 1 000 SWPT, SWPTA, SWPTAL, SWPTL — 64-bit SWPTALFEAT_LSUI

GCS load/store

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
11011001000111110opc11RnRt
Decode fields Instruction Details Feature
opc
000 GCSSTRFEAT_GCS
001 GCSSTTRFEAT_GCS
01x UNALLOCATED-
1xx UNALLOCATED-

Load/store memory tags

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
11011001opc1imm9op2RnRt
Decode fields Instruction Details Feature
opc imm9 op2
00 01 STG — Post-indexFEAT_MTE
00 10 STG — Signed offsetFEAT_MTE
00 11 STG — Pre-indexFEAT_MTE
00 000000000 00 STZGMFEAT_MTE2
01 00 LDGFEAT_MTE
01 01 STZG — Post-indexFEAT_MTE
01 10 STZG — Signed offsetFEAT_MTE
01 11 STZG — Pre-indexFEAT_MTE
10 01 ST2G — Post-indexFEAT_MTE
10 10 ST2G — Signed offsetFEAT_MTE
10 11 ST2G — Pre-indexFEAT_MTE
10 000000000 00 STGMFEAT_MTE2
11 01 STZ2G — Post-indexFEAT_MTE
11 10 STZ2G — Signed offsetFEAT_MTE
11 11 STZ2G — Pre-indexFEAT_MTE
11 000000000 00 LDGMFEAT_MTE2
!= 01 != 000000000 00 UNALLOCATED-

Load/store exclusive pair

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
1sz0010000L1Rso0Rt2RnRt
Decode fields Instruction Details
sz L o0
0 0 0 STXP — 32-bit
0 0 1 STLXP — 32-bit
0 1 0 LDXP — 32-bit
0 1 1 LDAXP — 32-bit
1 0 0 STXP — 64-bit
1 0 1 STLXP — 64-bit
1 1 0 LDXP — 64-bit
1 1 1 LDAXP — 64-bit

Load/store exclusive register (unprivileged)

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
1sz0010010L0Rso0Rt2RnRt
Decode fields Instruction Details Feature
sz L o0
0 0 0 STTXR — 32-bitFEAT_LSUI
0 0 1 STLTXR — 32-bitFEAT_LSUI
0 1 0 LDTXR — 32-bitFEAT_LSUI
0 1 1 LDATXR — 32-bitFEAT_LSUI
1 0 0 STTXR — 64-bitFEAT_LSUI
1 0 1 STLTXR — 64-bitFEAT_LSUI
1 1 0 LDTXR — 64-bitFEAT_LSUI
1 1 1 LDATXR — 64-bitFEAT_LSUI

Compare and swap (unprivileged)

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
1sz0010011L0Rso0Rt2RnRt
Decode fields Instruction Details Feature
sz L o0 Rt2
0 UNALLOCATED-
1 != 11111 UNALLOCATED-
1 0 0 11111 CAST, CASAT, CASALT, CASLT — CASTFEAT_LSUI
1 0 1 11111 CAST, CASAT, CASALT, CASLT — CASLTFEAT_LSUI
1 1 0 11111 CAST, CASAT, CASALT, CASLT — CASATFEAT_LSUI
1 1 1 11111 CAST, CASAT, CASALT, CASLT — CASALTFEAT_LSUI

Load/store exclusive register

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
size0010000L0Rso0Rt2RnRt
Decode fields Instruction Details
size L o0
00 0 0 STXRB
00 0 1 STLXRB
00 1 0 LDXRB
00 1 1 LDAXRB
01 0 0 STXRH
01 0 1 STLXRH
01 1 0 LDXRH
01 1 1 LDAXRH
10 0 0 STXR — 32-bit
10 0 1 STLXR — 32-bit
10 1 0 LDXR — 32-bit
10 1 1 LDAXR — 32-bit
11 0 0 STXR — 64-bit
11 0 1 STLXR — 64-bit
11 1 0 LDXR — 64-bit
11 1 1 LDAXR — 64-bit

Load/store ordered

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
size0010001L0Rso0Rt2RnRt
Decode fields Instruction Details Feature
size L o0
00 0 0 STLLRBFEAT_LOR
00 0 1 STLRB-
00 1 0 LDLARBFEAT_LOR
00 1 1 LDARB-
01 0 0 STLLRHFEAT_LOR
01 0 1 STLRH-
01 1 0 LDLARHFEAT_LOR
01 1 1 LDARH-
10 0 0 STLLR — 32-bitFEAT_LOR
10 0 1 STLR — 32-bit-
10 1 0 LDLAR — 32-bitFEAT_LOR
10 1 1 LDAR — 32-bit-
11 0 0 STLLR — 64-bitFEAT_LOR
11 0 1 STLR — 64-bit-
11 1 0 LDLAR — 64-bitFEAT_LOR
11 1 1 LDAR — 64-bit-

Compare and swap

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
size0010001L1Rso0Rt2RnRt
Decode fields Instruction Details Feature
size L o0 Rt2
!= 11111 UNALLOCATED-
00 0 0 11111 CASB, CASAB, CASALB, CASLB — CASBFEAT_LSE
00 0 1 11111 CASB, CASAB, CASALB, CASLB — CASLBFEAT_LSE
00 1 0 11111 CASB, CASAB, CASALB, CASLB — CASABFEAT_LSE
00 1 1 11111 CASB, CASAB, CASALB, CASLB — CASALBFEAT_LSE
01 0 0 11111 CASH, CASAH, CASALH, CASLH — CASHFEAT_LSE
01 0 1 11111 CASH, CASAH, CASALH, CASLH — CASLHFEAT_LSE
01 1 0 11111 CASH, CASAH, CASALH, CASLH — CASAHFEAT_LSE
01 1 1 11111 CASH, CASAH, CASALH, CASLH — CASALHFEAT_LSE
10 0 0 11111 CAS, CASA, CASAL, CASL — 32-bit CASFEAT_LSE
10 0 1 11111 CAS, CASA, CASAL, CASL — 32-bit CASLFEAT_LSE
10 1 0 11111 CAS, CASA, CASAL, CASL — 32-bit CASAFEAT_LSE
10 1 1 11111 CAS, CASA, CASAL, CASL — 32-bit CASALFEAT_LSE
11 0 0 11111 CAS, CASA, CASAL, CASL — 64-bit CASFEAT_LSE
11 0 1 11111 CAS, CASA, CASAL, CASL — 64-bit CASLFEAT_LSE
11 1 0 11111 CAS, CASA, CASAL, CASL — 64-bit CASAFEAT_LSE
11 1 1 11111 CAS, CASA, CASAL, CASL — 64-bit CASALFEAT_LSE

LDIAPP/STILP

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
size0110010L0Rt2opc210RnRt
Decode fields Instruction Details Feature
size L opc2
0x UNALLOCATED-
1x 001x UNALLOCATED-
1x 01xx UNALLOCATED-
1x 1xxx UNALLOCATED-
10 0 0000 STILP — 32-bit pre-indexFEAT_LRCPC3
10 0 0001 STILP — 32-bitFEAT_LRCPC3
10 1 0000 LDIAPP — 32-bit post-indexFEAT_LRCPC3
10 1 0001 LDIAPP — 32-bitFEAT_LRCPC3
11 0 0000 STILP — 64-bit pre-indexFEAT_LRCPC3
11 0 0001 STILP — 64-bitFEAT_LRCPC3
11 1 0000 LDIAPP — 64-bit post-indexFEAT_LRCPC3
11 1 0001 LDIAPP — 64-bitFEAT_LRCPC3

LDAPR/STLR (writeback)

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
size0110011L000000000010RnRt
Decode fields Instruction Details Feature
size L
0x UNALLOCATED-
10 0 STLR — 32-bitFEAT_LRCPC3
10 1 LDAPR — 32-bitFEAT_LRCPC3
11 0 STLR — 64-bitFEAT_LRCPC3
11 1 LDAPR — 64-bitFEAT_LRCPC3

LDAPR/STLR (unscaled immediate)

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
size011001opc0imm900RnRt
Decode fields Instruction Details Feature
size opc
00 00 STLURBFEAT_LRCPC2
00 01 LDAPURBFEAT_LRCPC2
00 10 LDAPURSB — 64-bitFEAT_LRCPC2
00 11 LDAPURSB — 32-bitFEAT_LRCPC2
01 00 STLURHFEAT_LRCPC2
01 01 LDAPURHFEAT_LRCPC2
01 10 LDAPURSH — 64-bitFEAT_LRCPC2
01 11 LDAPURSH — 32-bitFEAT_LRCPC2
10 00 STLUR — 32-bitFEAT_LRCPC2
10 01 LDAPUR — 32-bitFEAT_LRCPC2
10 10 LDAPURSWFEAT_LRCPC2
10 11 UNALLOCATED-
11 00 STLUR — 64-bitFEAT_LRCPC2
11 01 LDAPUR — 64-bitFEAT_LRCPC2
11 1x UNALLOCATED-

LDAPR/STLR (SIMD&FP)

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
size011101opc0imm910RnRt
Decode fields Instruction Details Feature
size opc
00 00 STLUR (SIMD&FP) — 8-bitFEAT_FP && FEAT_LRCPC3
00 01 LDAPUR (SIMD&FP) — 8-bitFEAT_FP && FEAT_LRCPC3
00 10 STLUR (SIMD&FP) — 128-bitFEAT_FP && FEAT_LRCPC3
00 11 LDAPUR (SIMD&FP) — 128-bitFEAT_FP && FEAT_LRCPC3
01 00 STLUR (SIMD&FP) — 16-bitFEAT_FP && FEAT_LRCPC3
01 01 LDAPUR (SIMD&FP) — 16-bitFEAT_FP && FEAT_LRCPC3
10 00 STLUR (SIMD&FP) — 32-bitFEAT_FP && FEAT_LRCPC3
10 01 LDAPUR (SIMD&FP) — 32-bitFEAT_FP && FEAT_LRCPC3
11 00 STLUR (SIMD&FP) — 64-bitFEAT_FP && FEAT_LRCPC3
11 01 LDAPUR (SIMD&FP) — 64-bitFEAT_FP && FEAT_LRCPC3
!= 00 1x UNALLOCATED-

Load register (literal)

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
opc011VR00imm19Rt
Decode fields Instruction Details Feature
opc VR
00 0 LDR (literal) — 32-bit-
00 1 LDR (literal, SIMD&FP) — 32-bitFEAT_FP
01 0 LDR (literal) — 64-bit-
01 1 LDR (literal, SIMD&FP) — 64-bitFEAT_FP
10 0 LDRSW (literal)-
10 1 LDR (literal, SIMD&FP) — 128-bitFEAT_FP
11 0 PRFM (literal)-
11 1 UNALLOCATED-

Memory Copy and Memory Set

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
size011o001op10Rsop201RnRd
Decode fields Instruction Details Feature
o0 op1 op2
11 11xx UNALLOCATED-
0 00 0000 CPYFP, CPYFM, CPYFE — PrologueFEAT_MOPS
0 00 0001 CPYFPWT, CPYFMWT, CPYFEWT — PrologueFEAT_MOPS
0 00 0010 CPYFPRT, CPYFMRT, CPYFERT — PrologueFEAT_MOPS
0 00 0011 CPYFPT, CPYFMT, CPYFET — PrologueFEAT_MOPS
0 00 0100 CPYFPWN, CPYFMWN, CPYFEWN — PrologueFEAT_MOPS
0 00 0101 CPYFPWTWN, CPYFMWTWN, CPYFEWTWN — PrologueFEAT_MOPS
0 00 0110 CPYFPRTWN, CPYFMRTWN, CPYFERTWN — PrologueFEAT_MOPS
0 00 0111 CPYFPTWN, CPYFMTWN, CPYFETWN — PrologueFEAT_MOPS
0 00 1000 CPYFPRN, CPYFMRN, CPYFERN — PrologueFEAT_MOPS
0 00 1001 CPYFPWTRN, CPYFMWTRN, CPYFEWTRN — PrologueFEAT_MOPS
0 00 1010 CPYFPRTRN, CPYFMRTRN, CPYFERTRN — PrologueFEAT_MOPS
0 00 1011 CPYFPTRN, CPYFMTRN, CPYFETRN — PrologueFEAT_MOPS
0 00 1100 CPYFPN, CPYFMN, CPYFEN — PrologueFEAT_MOPS
0 00 1101 CPYFPWTN, CPYFMWTN, CPYFEWTN — PrologueFEAT_MOPS
0 00 1110 CPYFPRTN, CPYFMRTN, CPYFERTN — PrologueFEAT_MOPS
0 00 1111 CPYFPTN, CPYFMTN, CPYFETN — PrologueFEAT_MOPS
0 01 0000 CPYFP, CPYFM, CPYFE — MainFEAT_MOPS
0 01 0001 CPYFPWT, CPYFMWT, CPYFEWT — MainFEAT_MOPS
0 01 0010 CPYFPRT, CPYFMRT, CPYFERT — MainFEAT_MOPS
0 01 0011 CPYFPT, CPYFMT, CPYFET — MainFEAT_MOPS
0 01 0100 CPYFPWN, CPYFMWN, CPYFEWN — MainFEAT_MOPS
0 01 0101 CPYFPWTWN, CPYFMWTWN, CPYFEWTWN — MainFEAT_MOPS
0 01 0110 CPYFPRTWN, CPYFMRTWN, CPYFERTWN — MainFEAT_MOPS
0 01 0111 CPYFPTWN, CPYFMTWN, CPYFETWN — MainFEAT_MOPS
0 01 1000 CPYFPRN, CPYFMRN, CPYFERN — MainFEAT_MOPS
0 01 1001 CPYFPWTRN, CPYFMWTRN, CPYFEWTRN — MainFEAT_MOPS
0 01 1010 CPYFPRTRN, CPYFMRTRN, CPYFERTRN — MainFEAT_MOPS
0 01 1011 CPYFPTRN, CPYFMTRN, CPYFETRN — MainFEAT_MOPS
0 01 1100 CPYFPN, CPYFMN, CPYFEN — MainFEAT_MOPS
0 01 1101 CPYFPWTN, CPYFMWTN, CPYFEWTN — MainFEAT_MOPS
0 01 1110 CPYFPRTN, CPYFMRTN, CPYFERTN — MainFEAT_MOPS
0 01 1111 CPYFPTN, CPYFMTN, CPYFETN — MainFEAT_MOPS
0 10 0000 CPYFP, CPYFM, CPYFE — EpilogueFEAT_MOPS
0 10 0001 CPYFPWT, CPYFMWT, CPYFEWT — EpilogueFEAT_MOPS
0 10 0010 CPYFPRT, CPYFMRT, CPYFERT — EpilogueFEAT_MOPS
0 10 0011 CPYFPT, CPYFMT, CPYFET — EpilogueFEAT_MOPS
0 10 0100 CPYFPWN, CPYFMWN, CPYFEWN — EpilogueFEAT_MOPS
0 10 0101 CPYFPWTWN, CPYFMWTWN, CPYFEWTWN — EpilogueFEAT_MOPS
0 10 0110 CPYFPRTWN, CPYFMRTWN, CPYFERTWN — EpilogueFEAT_MOPS
0 10 0111 CPYFPTWN, CPYFMTWN, CPYFETWN — EpilogueFEAT_MOPS
0 10 1000 CPYFPRN, CPYFMRN, CPYFERN — EpilogueFEAT_MOPS
0 10 1001 CPYFPWTRN, CPYFMWTRN, CPYFEWTRN — EpilogueFEAT_MOPS
0 10 1010 CPYFPRTRN, CPYFMRTRN, CPYFERTRN — EpilogueFEAT_MOPS
0 10 1011 CPYFPTRN, CPYFMTRN, CPYFETRN — EpilogueFEAT_MOPS
0 10 1100 CPYFPN, CPYFMN, CPYFEN — EpilogueFEAT_MOPS
0 10 1101 CPYFPWTN, CPYFMWTN, CPYFEWTN — EpilogueFEAT_MOPS
0 10 1110 CPYFPRTN, CPYFMRTN, CPYFERTN — EpilogueFEAT_MOPS
0 10 1111 CPYFPTN, CPYFMTN, CPYFETN — EpilogueFEAT_MOPS
0 11 0000 SETP, SETM, SETE — PrologueFEAT_MOPS
0 11 0001 SETPT, SETMT, SETET — PrologueFEAT_MOPS
0 11 0010 SETPN, SETMN, SETEN — PrologueFEAT_MOPS
0 11 0011 SETPTN, SETMTN, SETETN — PrologueFEAT_MOPS
0 11 0100 SETP, SETM, SETE — MainFEAT_MOPS
0 11 0101 SETPT, SETMT, SETET — MainFEAT_MOPS
0 11 0110 SETPN, SETMN, SETEN — MainFEAT_MOPS
0 11 0111 SETPTN, SETMTN, SETETN — MainFEAT_MOPS
0 11 1000 SETP, SETM, SETE — EpilogueFEAT_MOPS
0 11 1001 SETPT, SETMT, SETET — EpilogueFEAT_MOPS
0 11 1010 SETPN, SETMN, SETEN — EpilogueFEAT_MOPS
0 11 1011 SETPTN, SETMTN, SETETN — EpilogueFEAT_MOPS
1 00 0000 CPYP, CPYM, CPYE — PrologueFEAT_MOPS
1 00 0001 CPYPWT, CPYMWT, CPYEWT — PrologueFEAT_MOPS
1 00 0010 CPYPRT, CPYMRT, CPYERT — PrologueFEAT_MOPS
1 00 0011 CPYPT, CPYMT, CPYET — PrologueFEAT_MOPS
1 00 0100 CPYPWN, CPYMWN, CPYEWN — PrologueFEAT_MOPS
1 00 0101 CPYPWTWN, CPYMWTWN, CPYEWTWN — PrologueFEAT_MOPS
1 00 0110 CPYPRTWN, CPYMRTWN, CPYERTWN — PrologueFEAT_MOPS
1 00 0111 CPYPTWN, CPYMTWN, CPYETWN — PrologueFEAT_MOPS
1 00 1000 CPYPRN, CPYMRN, CPYERN — PrologueFEAT_MOPS
1 00 1001 CPYPWTRN, CPYMWTRN, CPYEWTRN — PrologueFEAT_MOPS
1 00 1010 CPYPRTRN, CPYMRTRN, CPYERTRN — PrologueFEAT_MOPS
1 00 1011 CPYPTRN, CPYMTRN, CPYETRN — PrologueFEAT_MOPS
1 00 1100 CPYPN, CPYMN, CPYEN — PrologueFEAT_MOPS
1 00 1101 CPYPWTN, CPYMWTN, CPYEWTN — PrologueFEAT_MOPS
1 00 1110 CPYPRTN, CPYMRTN, CPYERTN — PrologueFEAT_MOPS
1 00 1111 CPYPTN, CPYMTN, CPYETN — PrologueFEAT_MOPS
1 01 0000 CPYP, CPYM, CPYE — MainFEAT_MOPS
1 01 0001 CPYPWT, CPYMWT, CPYEWT — MainFEAT_MOPS
1 01 0010 CPYPRT, CPYMRT, CPYERT — MainFEAT_MOPS
1 01 0011 CPYPT, CPYMT, CPYET — MainFEAT_MOPS
1 01 0100 CPYPWN, CPYMWN, CPYEWN — MainFEAT_MOPS
1 01 0101 CPYPWTWN, CPYMWTWN, CPYEWTWN — MainFEAT_MOPS
1 01 0110 CPYPRTWN, CPYMRTWN, CPYERTWN — MainFEAT_MOPS
1 01 0111 CPYPTWN, CPYMTWN, CPYETWN — MainFEAT_MOPS
1 01 1000 CPYPRN, CPYMRN, CPYERN — MainFEAT_MOPS
1 01 1001 CPYPWTRN, CPYMWTRN, CPYEWTRN — MainFEAT_MOPS
1 01 1010 CPYPRTRN, CPYMRTRN, CPYERTRN — MainFEAT_MOPS
1 01 1011 CPYPTRN, CPYMTRN, CPYETRN — MainFEAT_MOPS
1 01 1100 CPYPN, CPYMN, CPYEN — MainFEAT_MOPS
1 01 1101 CPYPWTN, CPYMWTN, CPYEWTN — MainFEAT_MOPS
1 01 1110 CPYPRTN, CPYMRTN, CPYERTN — MainFEAT_MOPS
1 01 1111 CPYPTN, CPYMTN, CPYETN — MainFEAT_MOPS
1 10 0000 CPYP, CPYM, CPYE — EpilogueFEAT_MOPS
1 10 0001 CPYPWT, CPYMWT, CPYEWT — EpilogueFEAT_MOPS
1 10 0010 CPYPRT, CPYMRT, CPYERT — EpilogueFEAT_MOPS
1 10 0011 CPYPT, CPYMT, CPYET — EpilogueFEAT_MOPS
1 10 0100 CPYPWN, CPYMWN, CPYEWN — EpilogueFEAT_MOPS
1 10 0101 CPYPWTWN, CPYMWTWN, CPYEWTWN — EpilogueFEAT_MOPS
1 10 0110 CPYPRTWN, CPYMRTWN, CPYERTWN — EpilogueFEAT_MOPS
1 10 0111 CPYPTWN, CPYMTWN, CPYETWN — EpilogueFEAT_MOPS
1 10 1000 CPYPRN, CPYMRN, CPYERN — EpilogueFEAT_MOPS
1 10 1001 CPYPWTRN, CPYMWTRN, CPYEWTRN — EpilogueFEAT_MOPS
1 10 1010 CPYPRTRN, CPYMRTRN, CPYERTRN — EpilogueFEAT_MOPS
1 10 1011 CPYPTRN, CPYMTRN, CPYETRN — EpilogueFEAT_MOPS
1 10 1100 CPYPN, CPYMN, CPYEN — EpilogueFEAT_MOPS
1 10 1101 CPYPWTN, CPYMWTN, CPYEWTN — EpilogueFEAT_MOPS
1 10 1110 CPYPRTN, CPYMRTN, CPYERTN — EpilogueFEAT_MOPS
1 10 1111 CPYPTN, CPYMTN, CPYETN — EpilogueFEAT_MOPS
1 11 0000 SETGP, SETGM, SETGE — PrologueFEAT_MOPS
1 11 0001 SETGPT, SETGMT, SETGET — PrologueFEAT_MOPS
1 11 0010 SETGPN, SETGMN, SETGEN — PrologueFEAT_MOPS
1 11 0011 SETGPTN, SETGMTN, SETGETN — PrologueFEAT_MOPS
1 11 0100 SETGP, SETGM, SETGE — MainFEAT_MOPS
1 11 0101 SETGPT, SETGMT, SETGET — MainFEAT_MOPS
1 11 0110 SETGPN, SETGMN, SETGEN — MainFEAT_MOPS
1 11 0111 SETGPTN, SETGMTN, SETGETN — MainFEAT_MOPS
1 11 1000 SETGP, SETGM, SETGE — EpilogueFEAT_MOPS
1 11 1001 SETGPT, SETGMT, SETGET — EpilogueFEAT_MOPS
1 11 1010 SETGPN, SETGMN, SETGEN — EpilogueFEAT_MOPS
1 11 1011 SETGPTN, SETGMTN, SETGETN — EpilogueFEAT_MOPS

Load/store no-allocate pair (offset)

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
opc101VR000Limm7Rt2RnRt
Decode fields Instruction Details Feature
opc VR L
00 0 0 STNP — 32-bit-
00 0 1 LDNP — 32-bit-
00 1 0 STNP (SIMD&FP) — 32-bitFEAT_FP
00 1 1 LDNP (SIMD&FP) — 32-bitFEAT_FP
01 0 UNALLOCATED-
01 1 0 STNP (SIMD&FP) — 64-bitFEAT_FP
01 1 1 LDNP (SIMD&FP) — 64-bitFEAT_FP
10 0 0 STNP — 64-bit-
10 0 1 LDNP — 64-bit-
10 1 0 STNP (SIMD&FP) — 128-bitFEAT_FP
10 1 1 LDNP (SIMD&FP) — 128-bitFEAT_FP
11 0 0 STTNPFEAT_LSUI
11 0 1 LDTNPFEAT_LSUI
11 1 0 STTNP (SIMD&FP)FEAT_FP && FEAT_LSUI
11 1 1 LDTNP (SIMD&FP)FEAT_FP && FEAT_LSUI

Load/store register pair (post-indexed)

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
opc101VR001Limm7Rt2RnRt
Decode fields Instruction Details Feature
opc VR L
00 0 0 STP — 32-bit-
00 0 1 LDP — 32-bit-
00 1 0 STP (SIMD&FP) — 32-bitFEAT_FP
00 1 1 LDP (SIMD&FP) — 32-bitFEAT_FP
01 0 0 STGPFEAT_MTE
01 0 1 LDPSW-
01 1 0 STP (SIMD&FP) — 64-bitFEAT_FP
01 1 1 LDP (SIMD&FP) — 64-bitFEAT_FP
10 0 0 STP — 64-bit-
10 0 1 LDP — 64-bit-
10 1 0 STP (SIMD&FP) — 128-bitFEAT_FP
10 1 1 LDP (SIMD&FP) — 128-bitFEAT_FP
11 0 0 STTPFEAT_LSUI
11 0 1 LDTPFEAT_LSUI
11 1 0 STTP (SIMD&FP)FEAT_FP && FEAT_LSUI
11 1 1 LDTP (SIMD&FP)FEAT_FP && FEAT_LSUI

Load/store register pair (offset)

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
opc101VR010Limm7Rt2RnRt
Decode fields Instruction Details Feature
opc VR L
00 0 0 STP — 32-bit-
00 0 1 LDP — 32-bit-
00 1 0 STP (SIMD&FP) — 32-bitFEAT_FP
00 1 1 LDP (SIMD&FP) — 32-bitFEAT_FP
01 0 0 STGPFEAT_MTE
01 0 1 LDPSW-
01 1 0 STP (SIMD&FP) — 64-bitFEAT_FP
01 1 1 LDP (SIMD&FP) — 64-bitFEAT_FP
10 0 0 STP — 64-bit-
10 0 1 LDP — 64-bit-
10 1 0 STP (SIMD&FP) — 128-bitFEAT_FP
10 1 1 LDP (SIMD&FP) — 128-bitFEAT_FP
11 0 0 STTPFEAT_LSUI
11 0 1 LDTPFEAT_LSUI
11 1 0 STTP (SIMD&FP)FEAT_FP && FEAT_LSUI
11 1 1 LDTP (SIMD&FP)FEAT_FP && FEAT_LSUI

Load/store register pair (pre-indexed)

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
opc101VR011Limm7Rt2RnRt
Decode fields Instruction Details Feature
opc VR L
00 0 0 STP — 32-bit-
00 0 1 LDP — 32-bit-
00 1 0 STP (SIMD&FP) — 32-bitFEAT_FP
00 1 1 LDP (SIMD&FP) — 32-bitFEAT_FP
01 0 0 STGPFEAT_MTE
01 0 1 LDPSW-
01 1 0 STP (SIMD&FP) — 64-bitFEAT_FP
01 1 1 LDP (SIMD&FP) — 64-bitFEAT_FP
10 0 0 STP — 64-bit-
10 0 1 LDP — 64-bit-
10 1 0 STP (SIMD&FP) — 128-bitFEAT_FP
10 1 1 LDP (SIMD&FP) — 128-bitFEAT_FP
11 0 0 STTPFEAT_LSUI
11 0 1 LDTPFEAT_LSUI
11 1 0 STTP (SIMD&FP)FEAT_FP && FEAT_LSUI
11 1 1 LDTP (SIMD&FP)FEAT_FP && FEAT_LSUI

Load/store register (unscaled immediate)

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111VR00opc0imm900RnRt
Decode fields Instruction Details Feature
size VR opc
00 0 00 STURB-
00 0 01 LDURB-
00 0 10 LDURSB — 64-bit-
00 0 11 LDURSB — 32-bit-
00 1 00 STUR (SIMD&FP) — 8-bitFEAT_FP
00 1 01 LDUR (SIMD&FP) — 8-bitFEAT_FP
00 1 10 STUR (SIMD&FP) — 128-bitFEAT_FP
00 1 11 LDUR (SIMD&FP) — 128-bitFEAT_FP
01 0 00 STURH-
01 0 01 LDURH-
01 0 10 LDURSH — 64-bit-
01 0 11 LDURSH — 32-bit-
01 1 00 STUR (SIMD&FP) — 16-bitFEAT_FP
01 1 01 LDUR (SIMD&FP) — 16-bitFEAT_FP
1x 0 11 UNALLOCATED-
10 0 00 STUR — 32-bit-
10 0 01 LDUR — 32-bit-
10 0 10 LDURSW-
10 1 00 STUR (SIMD&FP) — 32-bitFEAT_FP
10 1 01 LDUR (SIMD&FP) — 32-bitFEAT_FP
11 0 00 STUR — 64-bit-
11 0 01 LDUR — 64-bit-
11 0 10 PRFUM-
11 1 00 STUR (SIMD&FP) — 64-bitFEAT_FP
11 1 01 LDUR (SIMD&FP) — 64-bitFEAT_FP
!= 00 1 1x UNALLOCATED-

Load/store register (immediate post-indexed)

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111VR00opc0imm901RnRt
Decode fields Instruction Details Feature
size VR opc
00 0 00 STRB (immediate)-
00 0 01 LDRB (immediate)-
00 0 10 LDRSB (immediate) — 64-bit-
00 0 11 LDRSB (immediate) — 32-bit-
00 1 00 STR (immediate, SIMD&FP) — 8-bitFEAT_FP
00 1 01 LDR (immediate, SIMD&FP) — 8-bitFEAT_FP
00 1 10 STR (immediate, SIMD&FP) — 128-bitFEAT_FP
00 1 11 LDR (immediate, SIMD&FP) — 128-bitFEAT_FP
01 0 00 STRH (immediate)-
01 0 01 LDRH (immediate)-
01 0 10 LDRSH (immediate) — 64-bit-
01 0 11 LDRSH (immediate) — 32-bit-
01 1 00 STR (immediate, SIMD&FP) — 16-bitFEAT_FP
01 1 01 LDR (immediate, SIMD&FP) — 16-bitFEAT_FP
01 1 1x UNALLOCATED-
10 0 00 STR (immediate) — 32-bit-
10 0 01 LDR (immediate) — 32-bit-
10 0 10 LDRSW (immediate)-
10 0 11 UNALLOCATED-
10 1 00 STR (immediate, SIMD&FP) — 32-bitFEAT_FP
10 1 01 LDR (immediate, SIMD&FP) — 32-bitFEAT_FP
10 1 1x UNALLOCATED-
11 1x UNALLOCATED-
11 0 00 STR (immediate) — 64-bit-
11 0 01 LDR (immediate) — 64-bit-
11 1 00 STR (immediate, SIMD&FP) — 64-bitFEAT_FP
11 1 01 LDR (immediate, SIMD&FP) — 64-bitFEAT_FP

Load/store register (unprivileged)

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111VR00opc0imm910RnRt
Decode fields Instruction Details
size VR opc
1 UNALLOCATED
00 0 00 STTRB
00 0 01 LDTRB
00 0 10 LDTRSB — 64-bit
00 0 11 LDTRSB — 32-bit
01 0 00 STTRH
01 0 01 LDTRH
01 0 10 LDTRSH — 64-bit
01 0 11 LDTRSH — 32-bit
10 0 00 STTR — 32-bit
10 0 01 LDTR — 32-bit
10 0 10 LDTRSW
10 0 11 UNALLOCATED
11 0 00 STTR — 64-bit
11 0 01 LDTR — 64-bit
11 0 1x UNALLOCATED

Load/store register (immediate pre-indexed)

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111VR00opc0imm911RnRt
Decode fields Instruction Details Feature
size VR opc
00 0 00 STRB (immediate)-
00 0 01 LDRB (immediate)-
00 0 10 LDRSB (immediate) — 64-bit-
00 0 11 LDRSB (immediate) — 32-bit-
00 1 00 STR (immediate, SIMD&FP) — 8-bitFEAT_FP
00 1 01 LDR (immediate, SIMD&FP) — 8-bitFEAT_FP
00 1 10 STR (immediate, SIMD&FP) — 128-bitFEAT_FP
00 1 11 LDR (immediate, SIMD&FP) — 128-bitFEAT_FP
01 0 00 STRH (immediate)-
01 0 01 LDRH (immediate)-
01 0 10 LDRSH (immediate) — 64-bit-
01 0 11 LDRSH (immediate) — 32-bit-
01 1 00 STR (immediate, SIMD&FP) — 16-bitFEAT_FP
01 1 01 LDR (immediate, SIMD&FP) — 16-bitFEAT_FP
01 1 1x UNALLOCATED-
10 0 00 STR (immediate) — 32-bit-
10 0 01 LDR (immediate) — 32-bit-
10 0 10 LDRSW (immediate)-
10 0 11 UNALLOCATED-
10 1 00 STR (immediate, SIMD&FP) — 32-bitFEAT_FP
10 1 01 LDR (immediate, SIMD&FP) — 32-bitFEAT_FP
10 1 1x UNALLOCATED-
11 1x UNALLOCATED-
11 0 00 STR (immediate) — 64-bit-
11 0 01 LDR (immediate) — 64-bit-
11 1 00 STR (immediate, SIMD&FP) — 64-bitFEAT_FP
11 1 01 LDR (immediate, SIMD&FP) — 64-bitFEAT_FP

Atomic memory operations

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111VR00AR1Rso3opc00RnRt
Decode fields Instruction Details Feature
size VR A R Rs o3 opc Rt
0 0 1 100 UNALLOCATED-
0 0 1 11x UNALLOCATED-
0 1 1 1 100 UNALLOCATED-
1 0 001 UNALLOCATED-
1 0 01x UNALLOCATED-
1 0 1 != 11111 UNALLOCATED-
1 0 1 001 11111 UNALLOCATED-
1 0 1 01x 11111 UNALLOCATED-
1 1 1 UNALLOCATED-
0x 0 0 1 101 UNALLOCATED-
0x 0 0 1 1 101 UNALLOCATED-
0x 0 1 1 11x UNALLOCATED-
0x 0 1 1 1 101 UNALLOCATED-
00 0 0 0 0 000 LDADDB, LDADDAB, LDADDALB, LDADDLB — No memory orderingFEAT_LSE
00 0 0 0 0 001 LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB — No memory orderingFEAT_LSE
00 0 0 0 0 010 LDEORB, LDEORAB, LDEORALB, LDEORLB — No memory orderingFEAT_LSE
00 0 0 0 0 011 LDSETB, LDSETAB, LDSETALB, LDSETLB — No memory orderingFEAT_LSE
00 0 0 0 0 100 LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB — No memory orderingFEAT_LSE
00 0 0 0 0 101 LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB — No memory orderingFEAT_LSE
00 0 0 0 0 110 LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB — No memory orderingFEAT_LSE
00 0 0 0 0 111 LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB — No memory orderingFEAT_LSE
00 0 0 0 1 000 SWPB, SWPAB, SWPALB, SWPLB — SWPBFEAT_LSE
00 0 0 0 1 001 RCWCLR, RCWCLRA, RCWCLRAL, RCWCLRL — RCWCLRFEAT_THE
00 0 0 0 1 010 RCWSWP, RCWSWPA, RCWSWPAL, RCWSWPL — RCWSWPFEAT_THE
00 0 0 0 1 011 RCWSET, RCWSETA, RCWSETAL, RCWSETL — RCWSETFEAT_THE
00 0 0 1 0 000 LDADDB, LDADDAB, LDADDALB, LDADDLB — ReleaseFEAT_LSE
00 0 0 1 0 001 LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB — ReleaseFEAT_LSE
00 0 0 1 0 010 LDEORB, LDEORAB, LDEORALB, LDEORLB — ReleaseFEAT_LSE
00 0 0 1 0 011 LDSETB, LDSETAB, LDSETALB, LDSETLB — ReleaseFEAT_LSE
00 0 0 1 0 100 LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB — ReleaseFEAT_LSE
00 0 0 1 0 101 LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB — ReleaseFEAT_LSE
00 0 0 1 0 110 LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB — ReleaseFEAT_LSE
00 0 0 1 0 111 LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB — ReleaseFEAT_LSE
00 0 0 1 1 000 SWPB, SWPAB, SWPALB, SWPLB — SWPLBFEAT_LSE
00 0 0 1 1 001 RCWCLR, RCWCLRA, RCWCLRAL, RCWCLRL — RCWCLRLFEAT_THE
00 0 0 1 1 010 RCWSWP, RCWSWPA, RCWSWPAL, RCWSWPL — RCWSWPLFEAT_THE
00 0 0 1 1 011 RCWSET, RCWSETA, RCWSETAL, RCWSETL — RCWSETLFEAT_THE
00 0 1 0 0 000 LDADDB, LDADDAB, LDADDALB, LDADDLB — AcquireFEAT_LSE
00 0 1 0 0 001 LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB — AcquireFEAT_LSE
00 0 1 0 0 010 LDEORB, LDEORAB, LDEORALB, LDEORLB — AcquireFEAT_LSE
00 0 1 0 0 011 LDSETB, LDSETAB, LDSETALB, LDSETLB — AcquireFEAT_LSE
00 0 1 0 0 100 LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB — AcquireFEAT_LSE
00 0 1 0 0 101 LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB — AcquireFEAT_LSE
00 0 1 0 0 110 LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB — AcquireFEAT_LSE
00 0 1 0 0 111 LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB — AcquireFEAT_LSE
00 0 1 0 1 000 SWPB, SWPAB, SWPALB, SWPLB — SWPABFEAT_LSE
00 0 1 0 1 001 RCWCLR, RCWCLRA, RCWCLRAL, RCWCLRL — RCWCLRAFEAT_THE
00 0 1 0 1 010 RCWSWP, RCWSWPA, RCWSWPAL, RCWSWPL — RCWSWPAFEAT_THE
00 0 1 0 1 011 RCWSET, RCWSETA, RCWSETAL, RCWSETL — RCWSETAFEAT_THE
00 0 1 0 1 100 LDAPRBFEAT_LRCPC
00 0 1 1 0 000 LDADDB, LDADDAB, LDADDALB, LDADDLB — Acquire-releaseFEAT_LSE
00 0 1 1 0 001 LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB — Acquire-releaseFEAT_LSE
00 0 1 1 0 010 LDEORB, LDEORAB, LDEORALB, LDEORLB — Acquire-releaseFEAT_LSE
00 0 1 1 0 011 LDSETB, LDSETAB, LDSETALB, LDSETLB — Acquire-releaseFEAT_LSE
00 0 1 1 0 100 LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB — Acquire-releaseFEAT_LSE
00 0 1 1 0 101 LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB — Acquire-releaseFEAT_LSE
00 0 1 1 0 110 LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB — Acquire-releaseFEAT_LSE
00 0 1 1 0 111 LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB — Acquire-releaseFEAT_LSE
00 0 1 1 1 000 SWPB, SWPAB, SWPALB, SWPLB — SWPALBFEAT_LSE
00 0 1 1 1 001 RCWCLR, RCWCLRA, RCWCLRAL, RCWCLRL — RCWCLRALFEAT_THE
00 0 1 1 1 010 RCWSWP, RCWSWPA, RCWSWPAL, RCWSWPL — RCWSWPALFEAT_THE
00 0 1 1 1 011 RCWSET, RCWSETA, RCWSETAL, RCWSETL — RCWSETALFEAT_THE
00 1 0 0 0 000 LDBFADD, LDBFADDA, LDBFADDAL, LDBFADDL — No memory orderingFEAT_LSFE
00 1 0 0 0 100 LDBFMAX, LDBFMAXA, LDBFMAXAL, LDBFMAXL — No memory orderingFEAT_LSFE
00 1 0 0 0 101 LDBFMIN, LDBFMINA, LDBFMINAL, LDBFMINL — No memory orderingFEAT_LSFE
00 1 0 0 0 110 LDBFMAXNM, LDBFMAXNMA, LDBFMAXNMAL, LDBFMAXNML — No memory orderingFEAT_LSFE
00 1 0 0 0 111 LDBFMINNM, LDBFMINNMA, LDBFMINNMAL, LDBFMINNML — No memory orderingFEAT_LSFE
00 1 0 0 1 000 11111 STBFADD, STBFADDL — No memory orderingFEAT_LSFE
00 1 0 0 1 100 11111 STBFMAX, STBFMAXL — No memory orderingFEAT_LSFE
00 1 0 0 1 101 11111 STBFMIN, STBFMINL — No memory orderingFEAT_LSFE
00 1 0 0 1 110 11111 STBFMAXNM, STBFMAXNML — No memory orderingFEAT_LSFE
00 1 0 0 1 111 11111 STBFMINNM, STBFMINNML — No memory orderingFEAT_LSFE
00 1 0 1 0 000 LDBFADD, LDBFADDA, LDBFADDAL, LDBFADDL — ReleaseFEAT_LSFE
00 1 0 1 0 100 LDBFMAX, LDBFMAXA, LDBFMAXAL, LDBFMAXL — ReleaseFEAT_LSFE
00 1 0 1 0 101 LDBFMIN, LDBFMINA, LDBFMINAL, LDBFMINL — ReleaseFEAT_LSFE
00 1 0 1 0 110 LDBFMAXNM, LDBFMAXNMA, LDBFMAXNMAL, LDBFMAXNML — ReleaseFEAT_LSFE
00 1 0 1 0 111 LDBFMINNM, LDBFMINNMA, LDBFMINNMAL, LDBFMINNML — ReleaseFEAT_LSFE
00 1 0 1 1 000 11111 STBFADD, STBFADDL — ReleaseFEAT_LSFE
00 1 0 1 1 100 11111 STBFMAX, STBFMAXL — ReleaseFEAT_LSFE
00 1 0 1 1 101 11111 STBFMIN, STBFMINL — ReleaseFEAT_LSFE
00 1 0 1 1 110 11111 STBFMAXNM, STBFMAXNML — ReleaseFEAT_LSFE
00 1 0 1 1 111 11111 STBFMINNM, STBFMINNML — ReleaseFEAT_LSFE
00 1 1 0 0 000 LDBFADD, LDBFADDA, LDBFADDAL, LDBFADDL — AcquireFEAT_LSFE
00 1 1 0 0 100 LDBFMAX, LDBFMAXA, LDBFMAXAL, LDBFMAXL — AcquireFEAT_LSFE
00 1 1 0 0 101 LDBFMIN, LDBFMINA, LDBFMINAL, LDBFMINL — AcquireFEAT_LSFE
00 1 1 0 0 110 LDBFMAXNM, LDBFMAXNMA, LDBFMAXNMAL, LDBFMAXNML — AcquireFEAT_LSFE
00 1 1 0 0 111 LDBFMINNM, LDBFMINNMA, LDBFMINNMAL, LDBFMINNML — AcquireFEAT_LSFE
00 1 1 1 0 000 LDBFADD, LDBFADDA, LDBFADDAL, LDBFADDL — Acquire-releaseFEAT_LSFE
00 1 1 1 0 100 LDBFMAX, LDBFMAXA, LDBFMAXAL, LDBFMAXL — Acquire-releaseFEAT_LSFE
00 1 1 1 0 101 LDBFMIN, LDBFMINA, LDBFMINAL, LDBFMINL — Acquire-releaseFEAT_LSFE
00 1 1 1 0 110 LDBFMAXNM, LDBFMAXNMA, LDBFMAXNMAL, LDBFMAXNML — Acquire-releaseFEAT_LSFE
00 1 1 1 0 111 LDBFMINNM, LDBFMINNMA, LDBFMINNMAL, LDBFMINNML — Acquire-releaseFEAT_LSFE
01 0 0 0 0 000 LDADDH, LDADDAH, LDADDALH, LDADDLH — No memory orderingFEAT_LSE
01 0 0 0 0 001 LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH — No memory orderingFEAT_LSE
01 0 0 0 0 010 LDEORH, LDEORAH, LDEORALH, LDEORLH — No memory orderingFEAT_LSE
01 0 0 0 0 011 LDSETH, LDSETAH, LDSETALH, LDSETLH — No memory orderingFEAT_LSE
01 0 0 0 0 100 LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH — No memory orderingFEAT_LSE
01 0 0 0 0 101 LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH — No memory orderingFEAT_LSE
01 0 0 0 0 110 LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH — No memory orderingFEAT_LSE
01 0 0 0 0 111 LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH — No memory orderingFEAT_LSE
01 0 0 0 1 000 SWPH, SWPAH, SWPALH, SWPLH — SWPHFEAT_LSE
01 0 0 0 1 001 RCWSCLR, RCWSCLRA, RCWSCLRAL, RCWSCLRL — RCWSCLRFEAT_THE
01 0 0 0 1 010 RCWSSWP, RCWSSWPA, RCWSSWPAL, RCWSSWPL — RCWSSWPFEAT_THE
01 0 0 0 1 011 RCWSSET, RCWSSETA, RCWSSETAL, RCWSSETL — RCWSSETFEAT_THE
01 0 0 1 0 000 LDADDH, LDADDAH, LDADDALH, LDADDLH — ReleaseFEAT_LSE
01 0 0 1 0 001 LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH — ReleaseFEAT_LSE
01 0 0 1 0 010 LDEORH, LDEORAH, LDEORALH, LDEORLH — ReleaseFEAT_LSE
01 0 0 1 0 011 LDSETH, LDSETAH, LDSETALH, LDSETLH — ReleaseFEAT_LSE
01 0 0 1 0 100 LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH — ReleaseFEAT_LSE
01 0 0 1 0 101 LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH — ReleaseFEAT_LSE
01 0 0 1 0 110 LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH — ReleaseFEAT_LSE
01 0 0 1 0 111 LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH — ReleaseFEAT_LSE
01 0 0 1 1 000 SWPH, SWPAH, SWPALH, SWPLH — SWPLHFEAT_LSE
01 0 0 1 1 001 RCWSCLR, RCWSCLRA, RCWSCLRAL, RCWSCLRL — RCWSCLRLFEAT_THE
01 0 0 1 1 010 RCWSSWP, RCWSSWPA, RCWSSWPAL, RCWSSWPL — RCWSSWPLFEAT_THE
01 0 0 1 1 011 RCWSSET, RCWSSETA, RCWSSETAL, RCWSSETL — RCWSSETLFEAT_THE
01 0 1 0 0 000 LDADDH, LDADDAH, LDADDALH, LDADDLH — AcquireFEAT_LSE
01 0 1 0 0 001 LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH — AcquireFEAT_LSE
01 0 1 0 0 010 LDEORH, LDEORAH, LDEORALH, LDEORLH — AcquireFEAT_LSE
01 0 1 0 0 011 LDSETH, LDSETAH, LDSETALH, LDSETLH — AcquireFEAT_LSE
01 0 1 0 0 100 LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH — AcquireFEAT_LSE
01 0 1 0 0 101 LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH — AcquireFEAT_LSE
01 0 1 0 0 110 LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH — AcquireFEAT_LSE
01 0 1 0 0 111 LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH — AcquireFEAT_LSE
01 0 1 0 1 000 SWPH, SWPAH, SWPALH, SWPLH — SWPAHFEAT_LSE
01 0 1 0 1 001 RCWSCLR, RCWSCLRA, RCWSCLRAL, RCWSCLRL — RCWSCLRAFEAT_THE
01 0 1 0 1 010 RCWSSWP, RCWSSWPA, RCWSSWPAL, RCWSSWPL — RCWSSWPAFEAT_THE
01 0 1 0 1 011 RCWSSET, RCWSSETA, RCWSSETAL, RCWSSETL — RCWSSETAFEAT_THE
01 0 1 0 1 100 LDAPRHFEAT_LRCPC
01 0 1 1 0 000 LDADDH, LDADDAH, LDADDALH, LDADDLH — Acquire-releaseFEAT_LSE
01 0 1 1 0 001 LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH — Acquire-releaseFEAT_LSE
01 0 1 1 0 010 LDEORH, LDEORAH, LDEORALH, LDEORLH — Acquire-releaseFEAT_LSE
01 0 1 1 0 011 LDSETH, LDSETAH, LDSETALH, LDSETLH — Acquire-releaseFEAT_LSE
01 0 1 1 0 100 LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH — Acquire-releaseFEAT_LSE
01 0 1 1 0 101 LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH — Acquire-releaseFEAT_LSE
01 0 1 1 0 110 LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH — Acquire-releaseFEAT_LSE
01 0 1 1 0 111 LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH — Acquire-releaseFEAT_LSE
01 0 1 1 1 000 SWPH, SWPAH, SWPALH, SWPLH — SWPALHFEAT_LSE
01 0 1 1 1 001 RCWSCLR, RCWSCLRA, RCWSCLRAL, RCWSCLRL — RCWSCLRALFEAT_THE
01 0 1 1 1 010 RCWSSWP, RCWSSWPA, RCWSSWPAL, RCWSSWPL — RCWSSWPALFEAT_THE
01 0 1 1 1 011 RCWSSET, RCWSSETA, RCWSSETAL, RCWSSETL — RCWSSETALFEAT_THE
01 1 0 0 0 000 LDFADD, LDFADDA, LDFADDAL, LDFADDL — Half-precision no memory orderingFEAT_LSFE
01 1 0 0 0 100 LDFMAX, LDFMAXA, LDFMAXAL, LDFMAXL — Half-precision no memory orderingFEAT_LSFE
01 1 0 0 0 101 LDFMIN, LDFMINA, LDFMINAL, LDFMINL — Half-precision no memory orderingFEAT_LSFE
01 1 0 0 0 110 LDFMAXNM, LDFMAXNMA, LDFMAXNMAL, LDFMAXNML — Half-precision no memory orderingFEAT_LSFE
01 1 0 0 0 111 LDFMINNM, LDFMINNMA, LDFMINNMAL, LDFMINNML — Half-precision no memory orderingFEAT_LSFE
01 1 0 0 1 000 11111 STFADD, STFADDL — Half-precision no memory orderingFEAT_LSFE
01 1 0 0 1 100 11111 STFMAX, STFMAXL — Half-precision no memory orderingFEAT_LSFE
01 1 0 0 1 101 11111 STFMIN, STFMINL — Half-precision no memory orderingFEAT_LSFE
01 1 0 0 1 110 11111 STFMAXNM, STFMAXNML — Half-precision no memory orderingFEAT_LSFE
01 1 0 0 1 111 11111 STFMINNM, STFMINNML — Half-precision no memory orderingFEAT_LSFE
01 1 0 1 0 000 LDFADD, LDFADDA, LDFADDAL, LDFADDL — Half-precision releaseFEAT_LSFE
01 1 0 1 0 100 LDFMAX, LDFMAXA, LDFMAXAL, LDFMAXL — Half-precision releaseFEAT_LSFE
01 1 0 1 0 101 LDFMIN, LDFMINA, LDFMINAL, LDFMINL — Half-precision releaseFEAT_LSFE
01 1 0 1 0 110 LDFMAXNM, LDFMAXNMA, LDFMAXNMAL, LDFMAXNML — Half-precision releaseFEAT_LSFE
01 1 0 1 0 111 LDFMINNM, LDFMINNMA, LDFMINNMAL, LDFMINNML — Half-precision releaseFEAT_LSFE
01 1 0 1 1 000 11111 STFADD, STFADDL — Half-precision releaseFEAT_LSFE
01 1 0 1 1 100 11111 STFMAX, STFMAXL — Half-precision releaseFEAT_LSFE
01 1 0 1 1 101 11111 STFMIN, STFMINL — Half-precision releaseFEAT_LSFE
01 1 0 1 1 110 11111 STFMAXNM, STFMAXNML — Half-precision releaseFEAT_LSFE
01 1 0 1 1 111 11111 STFMINNM, STFMINNML — Half-precision releaseFEAT_LSFE
01 1 1 0 0 000 LDFADD, LDFADDA, LDFADDAL, LDFADDL — Half-precision acquireFEAT_LSFE
01 1 1 0 0 100 LDFMAX, LDFMAXA, LDFMAXAL, LDFMAXL — Half-precision acquireFEAT_LSFE
01 1 1 0 0 101 LDFMIN, LDFMINA, LDFMINAL, LDFMINL — Half-precision acquireFEAT_LSFE
01 1 1 0 0 110 LDFMAXNM, LDFMAXNMA, LDFMAXNMAL, LDFMAXNML — Half-precision acquireFEAT_LSFE
01 1 1 0 0 111 LDFMINNM, LDFMINNMA, LDFMINNMAL, LDFMINNML — Half-precision acquireFEAT_LSFE
01 1 1 1 0 000 LDFADD, LDFADDA, LDFADDAL, LDFADDL — Half-precision acquire-releaseFEAT_LSFE
01 1 1 1 0 100 LDFMAX, LDFMAXA, LDFMAXAL, LDFMAXL — Half-precision acquire-releaseFEAT_LSFE
01 1 1 1 0 101 LDFMIN, LDFMINA, LDFMINAL, LDFMINL — Half-precision acquire-releaseFEAT_LSFE
01 1 1 1 0 110 LDFMAXNM, LDFMAXNMA, LDFMAXNMAL, LDFMAXNML — Half-precision acquire-releaseFEAT_LSFE
01 1 1 1 0 111 LDFMINNM, LDFMINNMA, LDFMINNMAL, LDFMINNML — Half-precision acquire-releaseFEAT_LSFE
1x 0 1 1 x01 UNALLOCATED-
1x 0 1 1 x1x UNALLOCATED-
10 0 0 1 x01 UNALLOCATED-
10 0 0 1 010 UNALLOCATED-
10 0 0 1 011 UNALLOCATED-
10 0 0 0 0 000 LDADD, LDADDA, LDADDAL, LDADDL — 32-bit no memory orderingFEAT_LSE
10 0 0 0 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL — 32-bit no memory orderingFEAT_LSE
10 0 0 0 0 010 LDEOR, LDEORA, LDEORAL, LDEORL — 32-bit no memory orderingFEAT_LSE
10 0 0 0 0 011 LDSET, LDSETA, LDSETAL, LDSETL — 32-bit no memory orderingFEAT_LSE
10 0 0 0 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL — 32-bit no memory orderingFEAT_LSE
10 0 0 0 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL — 32-bit no memory orderingFEAT_LSE
10 0 0 0 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL — 32-bit no memory orderingFEAT_LSE
10 0 0 0 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL — 32-bit no memory orderingFEAT_LSE
10 0 0 0 1 000 SWP, SWPA, SWPAL, SWPL — 32-bit SWPFEAT_LSE
10 0 0 1 0 000 LDADD, LDADDA, LDADDAL, LDADDL — 32-bit releaseFEAT_LSE
10 0 0 1 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL — 32-bit releaseFEAT_LSE
10 0 0 1 0 010 LDEOR, LDEORA, LDEORAL, LDEORL — 32-bit releaseFEAT_LSE
10 0 0 1 0 011 LDSET, LDSETA, LDSETAL, LDSETL — 32-bit releaseFEAT_LSE
10 0 0 1 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL — 32-bit releaseFEAT_LSE
10 0 0 1 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL — 32-bit releaseFEAT_LSE
10 0 0 1 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL — 32-bit releaseFEAT_LSE
10 0 0 1 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL — 32-bit releaseFEAT_LSE
10 0 0 1 1 000 SWP, SWPA, SWPAL, SWPL — 32-bit SWPLFEAT_LSE
10 0 1 0 0 000 LDADD, LDADDA, LDADDAL, LDADDL — 32-bit acquireFEAT_LSE
10 0 1 0 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL — 32-bit acquireFEAT_LSE
10 0 1 0 0 010 LDEOR, LDEORA, LDEORAL, LDEORL — 32-bit acquireFEAT_LSE
10 0 1 0 0 011 LDSET, LDSETA, LDSETAL, LDSETL — 32-bit acquireFEAT_LSE
10 0 1 0 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL — 32-bit acquireFEAT_LSE
10 0 1 0 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL — 32-bit acquireFEAT_LSE
10 0 1 0 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL — 32-bit acquireFEAT_LSE
10 0 1 0 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL — 32-bit acquireFEAT_LSE
10 0 1 0 1 000 SWP, SWPA, SWPAL, SWPL — 32-bit SWPAFEAT_LSE
10 0 1 0 1 100 LDAPR — 32-bitFEAT_LRCPC
10 0 1 1 0 000 LDADD, LDADDA, LDADDAL, LDADDL — 32-bit acquire-releaseFEAT_LSE
10 0 1 1 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL — 32-bit acquire-releaseFEAT_LSE
10 0 1 1 0 010 LDEOR, LDEORA, LDEORAL, LDEORL — 32-bit acquire-releaseFEAT_LSE
10 0 1 1 0 011 LDSET, LDSETA, LDSETAL, LDSETL — 32-bit acquire-releaseFEAT_LSE
10 0 1 1 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL — 32-bit acquire-releaseFEAT_LSE
10 0 1 1 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL — 32-bit acquire-releaseFEAT_LSE
10 0 1 1 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL — 32-bit acquire-releaseFEAT_LSE
10 0 1 1 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL — 32-bit acquire-releaseFEAT_LSE
10 0 1 1 1 000 SWP, SWPA, SWPAL, SWPL — 32-bit SWPALFEAT_LSE
10 1 0 0 0 000 LDFADD, LDFADDA, LDFADDAL, LDFADDL — Single-precision no memory orderingFEAT_LSFE
10 1 0 0 0 100 LDFMAX, LDFMAXA, LDFMAXAL, LDFMAXL — Single-precision no memory orderingFEAT_LSFE
10 1 0 0 0 101 LDFMIN, LDFMINA, LDFMINAL, LDFMINL — Single-precision no memory orderingFEAT_LSFE
10 1 0 0 0 110 LDFMAXNM, LDFMAXNMA, LDFMAXNMAL, LDFMAXNML — Single-precision no memory orderingFEAT_LSFE
10 1 0 0 0 111 LDFMINNM, LDFMINNMA, LDFMINNMAL, LDFMINNML — Single-precision no memory orderingFEAT_LSFE
10 1 0 0 1 000 11111 STFADD, STFADDL — Single-precision no memory orderingFEAT_LSFE
10 1 0 0 1 100 11111 STFMAX, STFMAXL — Single-precision no memory orderingFEAT_LSFE
10 1 0 0 1 101 11111 STFMIN, STFMINL — Single-precision no memory orderingFEAT_LSFE
10 1 0 0 1 110 11111 STFMAXNM, STFMAXNML — Single-precision no memory orderingFEAT_LSFE
10 1 0 0 1 111 11111 STFMINNM, STFMINNML — Single-precision no memory orderingFEAT_LSFE
10 1 0 1 0 000 LDFADD, LDFADDA, LDFADDAL, LDFADDL — Single-precision releaseFEAT_LSFE
10 1 0 1 0 100 LDFMAX, LDFMAXA, LDFMAXAL, LDFMAXL — Single-precision releaseFEAT_LSFE
10 1 0 1 0 101 LDFMIN, LDFMINA, LDFMINAL, LDFMINL — Single-precision releaseFEAT_LSFE
10 1 0 1 0 110 LDFMAXNM, LDFMAXNMA, LDFMAXNMAL, LDFMAXNML — Single-precision releaseFEAT_LSFE
10 1 0 1 0 111 LDFMINNM, LDFMINNMA, LDFMINNMAL, LDFMINNML — Single-precision releaseFEAT_LSFE
10 1 0 1 1 000 11111 STFADD, STFADDL — Single-precision releaseFEAT_LSFE
10 1 0 1 1 100 11111 STFMAX, STFMAXL — Single-precision releaseFEAT_LSFE
10 1 0 1 1 101 11111 STFMIN, STFMINL — Single-precision releaseFEAT_LSFE
10 1 0 1 1 110 11111 STFMAXNM, STFMAXNML — Single-precision releaseFEAT_LSFE
10 1 0 1 1 111 11111 STFMINNM, STFMINNML — Single-precision releaseFEAT_LSFE
10 1 1 0 0 000 LDFADD, LDFADDA, LDFADDAL, LDFADDL — Single-precision acquireFEAT_LSFE
10 1 1 0 0 100 LDFMAX, LDFMAXA, LDFMAXAL, LDFMAXL — Single-precision acquireFEAT_LSFE
10 1 1 0 0 101 LDFMIN, LDFMINA, LDFMINAL, LDFMINL — Single-precision acquireFEAT_LSFE
10 1 1 0 0 110 LDFMAXNM, LDFMAXNMA, LDFMAXNMAL, LDFMAXNML — Single-precision acquireFEAT_LSFE
10 1 1 0 0 111 LDFMINNM, LDFMINNMA, LDFMINNMAL, LDFMINNML — Single-precision acquireFEAT_LSFE
10 1 1 1 0 000 LDFADD, LDFADDA, LDFADDAL, LDFADDL — Single-precision acquire-releaseFEAT_LSFE
10 1 1 1 0 100 LDFMAX, LDFMAXA, LDFMAXAL, LDFMAXL — Single-precision acquire-releaseFEAT_LSFE
10 1 1 1 0 101 LDFMIN, LDFMINA, LDFMINAL, LDFMINL — Single-precision acquire-releaseFEAT_LSFE
10 1 1 1 0 110 LDFMAXNM, LDFMAXNMA, LDFMAXNMAL, LDFMAXNML — Single-precision acquire-releaseFEAT_LSFE
10 1 1 1 0 111 LDFMINNM, LDFMINNMA, LDFMINNMAL, LDFMINNML — Single-precision acquire-releaseFEAT_LSFE
11 0 0 0 0 000 LDADD, LDADDA, LDADDAL, LDADDL — 64-bit no memory orderingFEAT_LSE
11 0 0 0 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL — 64-bit no memory orderingFEAT_LSE
11 0 0 0 0 010 LDEOR, LDEORA, LDEORAL, LDEORL — 64-bit no memory orderingFEAT_LSE
11 0 0 0 0 011 LDSET, LDSETA, LDSETAL, LDSETL — 64-bit no memory orderingFEAT_LSE
11 0 0 0 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL — 64-bit no memory orderingFEAT_LSE
11 0 0 0 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL — 64-bit no memory orderingFEAT_LSE
11 0 0 0 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL — 64-bit no memory orderingFEAT_LSE
11 0 0 0 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL — 64-bit no memory orderingFEAT_LSE
11 0 0 0 1 000 SWP, SWPA, SWPAL, SWPL — 64-bit SWPFEAT_LSE
11 0 0 0 1 010 ST64BV0FEAT_LS64_ACCDATA
11 0 0 0 1 011 ST64BVFEAT_LS64_V
11 0 0 0 11111 1 001 ST64BFEAT_LS64
11 0 0 0 11111 1 101 LD64BFEAT_LS64
11 0 0 0 != 11111 1 x01 UNALLOCATED-
11 0 0 1 0 000 LDADD, LDADDA, LDADDAL, LDADDL — 64-bit releaseFEAT_LSE
11 0 0 1 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL — 64-bit releaseFEAT_LSE
11 0 0 1 0 010 LDEOR, LDEORA, LDEORAL, LDEORL — 64-bit releaseFEAT_LSE
11 0 0 1 0 011 LDSET, LDSETA, LDSETAL, LDSETL — 64-bit releaseFEAT_LSE
11 0 0 1 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL — 64-bit releaseFEAT_LSE
11 0 0 1 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL — 64-bit releaseFEAT_LSE
11 0 0 1 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL — 64-bit releaseFEAT_LSE
11 0 0 1 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL — 64-bit releaseFEAT_LSE
11 0 0 1 1 x01 UNALLOCATED-
11 0 0 1 1 000 SWP, SWPA, SWPAL, SWPL — 64-bit SWPLFEAT_LSE
11 0 0 1 1 010 UNALLOCATED-
11 0 0 1 1 011 UNALLOCATED-
11 0 1 0 0 000 LDADD, LDADDA, LDADDAL, LDADDL — 64-bit acquireFEAT_LSE
11 0 1 0 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL — 64-bit acquireFEAT_LSE
11 0 1 0 0 010 LDEOR, LDEORA, LDEORAL, LDEORL — 64-bit acquireFEAT_LSE
11 0 1 0 0 011 LDSET, LDSETA, LDSETAL, LDSETL — 64-bit acquireFEAT_LSE
11 0 1 0 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL — 64-bit acquireFEAT_LSE
11 0 1 0 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL — 64-bit acquireFEAT_LSE
11 0 1 0 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL — 64-bit acquireFEAT_LSE
11 0 1 0 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL — 64-bit acquireFEAT_LSE
11 0 1 0 1 000 SWP, SWPA, SWPAL, SWPL — 64-bit SWPAFEAT_LSE
11 0 1 0 1 100 LDAPR — 64-bitFEAT_LRCPC
11 0 1 1 0 000 LDADD, LDADDA, LDADDAL, LDADDL — 64-bit acquire-releaseFEAT_LSE
11 0 1 1 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL — 64-bit acquire-releaseFEAT_LSE
11 0 1 1 0 010 LDEOR, LDEORA, LDEORAL, LDEORL — 64-bit acquire-releaseFEAT_LSE
11 0 1 1 0 011 LDSET, LDSETA, LDSETAL, LDSETL — 64-bit acquire-releaseFEAT_LSE
11 0 1 1 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL — 64-bit acquire-releaseFEAT_LSE
11 0 1 1 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL — 64-bit acquire-releaseFEAT_LSE
11 0 1 1 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL — 64-bit acquire-releaseFEAT_LSE
11 0 1 1 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL — 64-bit acquire-releaseFEAT_LSE
11 0 1 1 1 000 SWP, SWPA, SWPAL, SWPL — 64-bit SWPALFEAT_LSE
11 1 0 0 0 000 LDFADD, LDFADDA, LDFADDAL, LDFADDL — Double-precision no memory orderingFEAT_LSFE
11 1 0 0 0 100 LDFMAX, LDFMAXA, LDFMAXAL, LDFMAXL — Double-precision no memory orderingFEAT_LSFE
11 1 0 0 0 101 LDFMIN, LDFMINA, LDFMINAL, LDFMINL — Double-precision no memory orderingFEAT_LSFE
11 1 0 0 0 110 LDFMAXNM, LDFMAXNMA, LDFMAXNMAL, LDFMAXNML — Double-precision no memory orderingFEAT_LSFE
11 1 0 0 0 111 LDFMINNM, LDFMINNMA, LDFMINNMAL, LDFMINNML — Double-precision no memory orderingFEAT_LSFE
11 1 0 0 1 000 11111 STFADD, STFADDL — Double-precision no memory orderingFEAT_LSFE
11 1 0 0 1 100 11111 STFMAX, STFMAXL — Double-precision no memory orderingFEAT_LSFE
11 1 0 0 1 101 11111 STFMIN, STFMINL — Double-precision no memory orderingFEAT_LSFE
11 1 0 0 1 110 11111 STFMAXNM, STFMAXNML — Double-precision no memory orderingFEAT_LSFE
11 1 0 0 1 111 11111 STFMINNM, STFMINNML — Double-precision no memory orderingFEAT_LSFE
11 1 0 1 0 000 LDFADD, LDFADDA, LDFADDAL, LDFADDL — Double-precision releaseFEAT_LSFE
11 1 0 1 0 100 LDFMAX, LDFMAXA, LDFMAXAL, LDFMAXL — Double-precision releaseFEAT_LSFE
11 1 0 1 0 101 LDFMIN, LDFMINA, LDFMINAL, LDFMINL — Double-precision releaseFEAT_LSFE
11 1 0 1 0 110 LDFMAXNM, LDFMAXNMA, LDFMAXNMAL, LDFMAXNML — Double-precision releaseFEAT_LSFE
11 1 0 1 0 111 LDFMINNM, LDFMINNMA, LDFMINNMAL, LDFMINNML — Double-precision releaseFEAT_LSFE
11 1 0 1 1 000 11111 STFADD, STFADDL — Double-precision releaseFEAT_LSFE
11 1 0 1 1 100 11111 STFMAX, STFMAXL — Double-precision releaseFEAT_LSFE
11 1 0 1 1 101 11111 STFMIN, STFMINL — Double-precision releaseFEAT_LSFE
11 1 0 1 1 110 11111 STFMAXNM, STFMAXNML — Double-precision releaseFEAT_LSFE
11 1 0 1 1 111 11111 STFMINNM, STFMINNML — Double-precision releaseFEAT_LSFE
11 1 1 0 0 000 LDFADD, LDFADDA, LDFADDAL, LDFADDL — Double-precision acquireFEAT_LSFE
11 1 1 0 0 100 LDFMAX, LDFMAXA, LDFMAXAL, LDFMAXL — Double-precision acquireFEAT_LSFE
11 1 1 0 0 101 LDFMIN, LDFMINA, LDFMINAL, LDFMINL — Double-precision acquireFEAT_LSFE
11 1 1 0 0 110 LDFMAXNM, LDFMAXNMA, LDFMAXNMAL, LDFMAXNML — Double-precision acquireFEAT_LSFE
11 1 1 0 0 111 LDFMINNM, LDFMINNMA, LDFMINNMAL, LDFMINNML — Double-precision acquireFEAT_LSFE
11 1 1 1 0 000 LDFADD, LDFADDA, LDFADDAL, LDFADDL — Double-precision acquire-releaseFEAT_LSFE
11 1 1 1 0 100 LDFMAX, LDFMAXA, LDFMAXAL, LDFMAXL — Double-precision acquire-releaseFEAT_LSFE
11 1 1 1 0 101 LDFMIN, LDFMINA, LDFMINAL, LDFMINL — Double-precision acquire-releaseFEAT_LSFE
11 1 1 1 0 110 LDFMAXNM, LDFMAXNMA, LDFMAXNMAL, LDFMAXNML — Double-precision acquire-releaseFEAT_LSFE
11 1 1 1 0 111 LDFMINNM, LDFMINNMA, LDFMINNMAL, LDFMINNML — Double-precision acquire-releaseFEAT_LSFE

Load/store register (register offset)

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111VR00opc1RmoptionS10RnRt
Decode fields Instruction Details Feature
size VR opc option Rt
00 0 00 011 STRB (register) — Shifted register-
00 0 00 != 011 STRB (register) — Extended register-
00 0 01 011 LDRB (register) — Shifted register-
00 0 01 != 011 LDRB (register) — Extended register-
00 0 10 011 LDRSB (register) — 64-bit with shifted register offset-
00 0 10 != 011 LDRSB (register) — 64-bit with extended register offset-
00 0 11 011 LDRSB (register) — 32-bit with shifted register offset-
00 0 11 != 011 LDRSB (register) — 32-bit with extended register offset-
00 1 00 011 STR (register, SIMD&FP) — 8-bitFEAT_FP
00 1 00 != 011 STR (register, SIMD&FP) — 8-bitFEAT_FP
00 1 01 011 LDR (register, SIMD&FP) — 8-bitFEAT_FP
00 1 01 != 011 LDR (register, SIMD&FP) — 8-bitFEAT_FP
00 1 10 STR (register, SIMD&FP) — 128-bitFEAT_FP
00 1 11 LDR (register, SIMD&FP) — 128-bitFEAT_FP
01 0 00 STRH (register)-
01 0 01 LDRH (register)-
01 0 10 LDRSH (register) — 64-bit-
01 0 11 LDRSH (register) — 32-bit-
01 1 00 STR (register, SIMD&FP) — 16-bitFEAT_FP
01 1 01 LDR (register, SIMD&FP) — 16-bitFEAT_FP
1x 0 11 UNALLOCATED-
10 0 00 STR (register) — 32-bit-
10 0 01 LDR (register) — 32-bit-
10 0 10 LDRSW (register)-
10 1 00 STR (register, SIMD&FP) — 32-bitFEAT_FP
10 1 01 LDR (register, SIMD&FP) — 32-bitFEAT_FP
11 0 00 STR (register) — 64-bit-
11 0 01 LDR (register) — 64-bit-
11 0 10 x0x UNALLOCATED-
11 0 10 x1x 11xxx RPRFMFEAT_RPRFM
11 0 10 x1x != 11xxx PRFM (register)-
11 1 00 STR (register, SIMD&FP) — 64-bitFEAT_FP
11 1 01 LDR (register, SIMD&FP) — 64-bitFEAT_FP
!= 00 1 1x UNALLOCATED-

Load/store register (pac)

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111VR00MS1imm9W1RnRt
Decode fields Instruction Details Feature
size VR M W
11 0 0 0 LDRAA, LDRAB — Key A, offsetFEAT_PAuth
11 0 0 1 LDRAA, LDRAB — Key A, pre-indexedFEAT_PAuth
11 0 1 0 LDRAA, LDRAB — Key B, offsetFEAT_PAuth
11 0 1 1 LDRAA, LDRAB — Key B, pre-indexedFEAT_PAuth
11 1 UNALLOCATED-
!= 11 UNALLOCATED-

Load/store register (unsigned immediate)

The encodings in this section are decoded from Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111VR01opcimm12RnRt
Decode fields Instruction Details Feature
size VR opc
00 0 00 STRB (immediate)-
00 0 01 LDRB (immediate)-
00 0 10 LDRSB (immediate) — 64-bit-
00 0 11 LDRSB (immediate) — 32-bit-
00 1 00 STR (immediate, SIMD&FP) — 8-bitFEAT_FP
00 1 01 LDR (immediate, SIMD&FP) — 8-bitFEAT_FP
00 1 10 STR (immediate, SIMD&FP) — 128-bitFEAT_FP
00 1 11 LDR (immediate, SIMD&FP) — 128-bitFEAT_FP
01 0 00 STRH (immediate)-
01 0 01 LDRH (immediate)-
01 0 10 LDRSH (immediate) — 64-bit-
01 0 11 LDRSH (immediate) — 32-bit-
01 1 00 STR (immediate, SIMD&FP) — 16-bitFEAT_FP
01 1 01 LDR (immediate, SIMD&FP) — 16-bitFEAT_FP
1x 0 11 UNALLOCATED-
10 0 00 STR (immediate) — 32-bit-
10 0 01 LDR (immediate) — 32-bit-
10 0 10 LDRSW (immediate)-
10 1 00 STR (immediate, SIMD&FP) — 32-bitFEAT_FP
10 1 01 LDR (immediate, SIMD&FP) — 32-bitFEAT_FP
11 0 00 STR (immediate) — 64-bit-
11 0 01 LDR (immediate) — 64-bit-
11 0 10 PRFM (immediate)-
11 1 00 STR (immediate, SIMD&FP) — 64-bitFEAT_FP
11 1 01 LDR (immediate, SIMD&FP) — 64-bitFEAT_FP
!= 00 1 1x UNALLOCATED-
Base Instructions
SIMD&FP Instructions
SVE Instructions
SME Instructions
Index by Encoding
Shared Pseudocode
Proprietary Notice

Internal version only: aarchmrs v2024-12_rel, pseudocode v2024-12_rel ; Build timestamp: 2024-12-15T22:18

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