SMOP4A (4-way) -- A64

This instruction generates four independent quarter-tile signed integer sums of outer products from the sub-matrices in the half-vectors of the one or two first and second source vectors and accumulates the results to the corresponding elements of a 32-bit or 64-bit element ZA tile.

In case of the 8-bit integer variant, each of the quarter-tile sums of outer products is generated by multiplying the SVL_S÷2 × 4 sub-matrix of 8-bit signed values held in the half-vectors of the first source vectors by the 4 × SVL_S÷2 sub-matrix of 8-bit signed values held in the half-vectors of the second source vectors. Each 32-bit container of the half-vectors in the first source vectors holds 4 elements of each row of a SVL_S÷2 × 4 sub-matrix. Similarly, each 32-bit container of the half-vectors in the second source vector holds 4 elements of each column of a 4 × SVL_S÷2 sub-matrix.

In case of the 16-bit integer variant, each of the quarter-tile sums of outer products is generated by multiplying the SVL_D÷2 × 4 sub-matrix of 16-bit signed values held in the half-vectors of the first source vectors by the 4 × SVL_D÷2 sub-matrix of 16-bit signed values held in the half-vectors of the second source vectors. Each 64-bit container of the half-vectors in the first source vectors holds 4 elements of each row of a SVL_D÷2 × 4 sub-matrix. Similarly, each 64-bit container of the half-vectors in the second source vector holds 4 elements of each column of a 4 × SVL_D÷2 sub-matrix.

The resulting quarter-tile SVL_S÷2 × SVL_S÷2 widened 32-bit integer sums of outer products in case of the 8-bit integer variant or SVL_D÷2 × SVL_D÷2 widened 64-bit integer sums of outer products in case of the 16-bit integer variant are then destructively added to the 32-bit or 64-bit integer destination tile respectively.

This is equivalent to performing a 4-way dot product and accumulate to each of the destination tile elements.

32-bit, single and multiple vectors
(FEAT_SME_MOP4)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME_MOP4) then EndOfDecode(Decode_UNDEF); constant integer esize = 32; constant integer n = UInt('0':Zn:'0'); constant integer m = UInt('1':Zm:'0'); constant integer nreg = 1; constant integer mreg = 2; constant integer da = UInt(ZAda); constant boolean sub_op = FALSE; constant boolean op1_unsigned = FALSE; constant boolean op2_unsigned = FALSE;

32-bit, single vectors
(FEAT_SME_MOP4)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME_MOP4) then EndOfDecode(Decode_UNDEF); constant integer esize = 32; constant integer n = UInt('0':Zn:'0'); constant integer m = UInt('1':Zm:'0'); constant integer nreg = 1; constant integer mreg = 1; constant integer da = UInt(ZAda); constant boolean sub_op = FALSE; constant boolean op1_unsigned = FALSE; constant boolean op2_unsigned = FALSE;

32-bit, multiple and single vectors
(FEAT_SME_MOP4)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME_MOP4) then EndOfDecode(Decode_UNDEF); constant integer esize = 32; constant integer n = UInt('0':Zn:'0'); constant integer m = UInt('1':Zm:'0'); constant integer nreg = 2; constant integer mreg = 1; constant integer da = UInt(ZAda); constant boolean sub_op = FALSE; constant boolean op1_unsigned = FALSE; constant boolean op2_unsigned = FALSE;

32-bit, multiple vectors
(FEAT_SME_MOP4)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME_MOP4) then EndOfDecode(Decode_UNDEF); constant integer esize = 32; constant integer n = UInt('0':Zn:'0'); constant integer m = UInt('1':Zm:'0'); constant integer nreg = 2; constant integer mreg = 2; constant integer da = UInt(ZAda); constant boolean sub_op = FALSE; constant boolean op1_unsigned = FALSE; constant boolean op2_unsigned = FALSE;

64-bit, single and multiple vectors
(FEAT_SME_MOP4 && FEAT_SME_I16I64)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME_MOP4) || !IsFeatureImplemented(FEAT_SME_I16I64) then EndOfDecode(Decode_UNDEF); constant integer esize = 64; constant integer n = UInt('0':Zn:'0'); constant integer m = UInt('1':Zm:'0'); constant integer nreg = 1; constant integer mreg = 2; constant integer da = UInt(ZAda); constant boolean sub_op = FALSE; constant boolean op1_unsigned = FALSE; constant boolean op2_unsigned = FALSE;

64-bit, single vectors
(FEAT_SME_MOP4 && FEAT_SME_I16I64)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME_MOP4) || !IsFeatureImplemented(FEAT_SME_I16I64) then EndOfDecode(Decode_UNDEF); constant integer esize = 64; constant integer n = UInt('0':Zn:'0'); constant integer m = UInt('1':Zm:'0'); constant integer nreg = 1; constant integer mreg = 1; constant integer da = UInt(ZAda); constant boolean sub_op = FALSE; constant boolean op1_unsigned = FALSE; constant boolean op2_unsigned = FALSE;

64-bit, multiple and single vectors
(FEAT_SME_MOP4 && FEAT_SME_I16I64)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME_MOP4) || !IsFeatureImplemented(FEAT_SME_I16I64) then EndOfDecode(Decode_UNDEF); constant integer esize = 64; constant integer n = UInt('0':Zn:'0'); constant integer m = UInt('1':Zm:'0'); constant integer nreg = 2; constant integer mreg = 1; constant integer da = UInt(ZAda); constant boolean sub_op = FALSE; constant boolean op1_unsigned = FALSE; constant boolean op2_unsigned = FALSE;

64-bit, multiple vectors
(FEAT_SME_MOP4 && FEAT_SME_I16I64)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME_MOP4) || !IsFeatureImplemented(FEAT_SME_I16I64) then EndOfDecode(Decode_UNDEF); constant integer esize = 64; constant integer n = UInt('0':Zn:'0'); constant integer m = UInt('1':Zm:'0'); constant integer nreg = 2; constant integer mreg = 2; constant integer da = UInt(ZAda); constant boolean sub_op = FALSE; constant boolean op1_unsigned = FALSE; constant boolean op2_unsigned = FALSE;

Assembler Symbols

<ZAda>	For the "32-bit, multiple and single vectors", "32-bit, multiple vectors", "32-bit, single and multiple vectors", and "32-bit, single vectors" variants: is the name of the ZA tile ZA0-ZA3, encoded in the "ZAda" field.
	For the "64-bit, multiple and single vectors", "64-bit, multiple vectors", "64-bit, single and multiple vectors", and "64-bit, single vectors" variants: is the name of the ZA tile ZA0-ZA7, encoded in the "ZAda" field.

<Zn>	Is the name of the first source scalable vector register, registers in the range Z0-Z15, encoded as "Zn" times 2.

<Zm1>

Is the name of the first scalable vector register of the second source multi-vector group, in the range Z16-Z31, encoded as "Zm" times 2 plus 16.

<Zm2>

Is the name of the second scalable vector register of the second source multi-vector group, in the range Z16-Z31, encoded as "Zm" times 2 plus 17.

<Zm>	Is the name of the second source scalable vector register, registers in the range Z16-Z31, encoded as "Zm" times 2 plus 16.

<Zn1>

Is the name of the first scalable vector register of the first source multi-vector group, in the range Z0-Z15, encoded as "Zn" times 2.

<Zn2>

Is the name of the second scalable vector register of the first source multi-vector group, in the range Z0-Z15, encoded as "Zn" times 2 plus 1.

Operation

CheckStreamingSVEAndZAEnabled(); constant integer VL = CurrentVL; constant integer hvsize = VL DIV 2; constant integer dim = hvsize DIV esize; constant integer tilesize = 4*dim*dim*esize; constant bits(tilesize) op3 = ZAtile[da, esize, tilesize]; bits(tilesize) result; integer prod; for outprod = 0 to 3 constant integer row_hv = outprod DIV 2; constant integer col_hv = outprod MOD 2; constant integer row_base = row_hv * dim; constant integer col_base = col_hv * dim; constant bits(VL) op1 = Z[n + (nreg-1)*col_hv, VL]; constant bits(VL) op2 = Z[m + (mreg-1)*row_hv, VL]; for row = 0 to dim-1 for col = 0 to dim-1 constant integer row_idx = row_base + row; constant integer col_idx = col_base + col; constant integer tile_idx = row_idx * dim * 2 + col_idx; bits(esize) sum = Elem[op3, tile_idx, esize]; for k = 0 to 3 prod = (Int(Elem[op1, 4*row_idx + k, esize DIV 4], op1_unsigned) * Int(Elem[op2, 4*col_idx + k, esize DIV 4], op2_unsigned)); if sub_op then prod = -prod; sum = sum + prod; Elem[result, tile_idx, esize] = sum; ZAtile[da, esize, tilesize] = result;

Operational information

If PSTATE.DIT is 1:

The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.

Internal version only: aarchmrs v2024-12_rel, pseudocode v2024-12_rel ; Build timestamp: 2024-12-15T22:18

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	0	0	0	0	0	0	0	0	0	0	1	Zm			0	1	0	0	0	0	0	0	Zn			0	0	0	0	ZAda
							u0			u1	M											N					S

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	0	0	0	0	0	0	0	0	0	0	0	Zm			0	1	0	0	0	0	0	0	Zn			0	0	0	0	ZAda
							u0			u1	M											N					S

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	0	0	0	0	0	0	0	0	0	0	0	Zm			0	1	0	0	0	0	0	1	Zn			0	0	0	0	ZAda
							u0			u1	M											N					S

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	0	0	0	0	0	0	0	0	0	0	1	Zm			0	1	0	0	0	0	0	1	Zn			0	0	0	0	ZAda
							u0			u1	M											N					S

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	0	1	0	0	0	0	0	1	1	0	1	Zm			0	0	0	0	0	0	0	0	Zn			0	0	1	ZAda
							u0			u1	M											N					S

SMOP4A (4-way)

32-bit, single and multiple vectors
(FEAT_SME_MOP4)

Encoding

Decode for this encoding

32-bit, single vectors
(FEAT_SME_MOP4)

Encoding

Decode for this encoding

32-bit, multiple and single vectors
(FEAT_SME_MOP4)

Encoding

Decode for this encoding

32-bit, multiple vectors
(FEAT_SME_MOP4)

Encoding

Decode for this encoding

64-bit, single and multiple vectors
(FEAT_SME_MOP4 && FEAT_SME_I16I64)

Encoding

Decode for this encoding

64-bit, single vectors
(FEAT_SME_MOP4 && FEAT_SME_I16I64)

Encoding

Decode for this encoding

64-bit, multiple and single vectors
(FEAT_SME_MOP4 && FEAT_SME_I16I64)

Encoding

Decode for this encoding

64-bit, multiple vectors
(FEAT_SME_MOP4 && FEAT_SME_I16I64)

Encoding

Decode for this encoding

Assembler Symbols

Operation

Operational information