AESEMC

Multi-vector AES single round encryption and mix columns

The AESEMC instruction reads a 16-byte state array from each 128-bit segment of the two or four first source vectors, together with a round key from the indexed 128-bit segment of the corresponding 512-bit portion of the second source vector. Each state array undergoes a single round of the AddRoundKey(), ShiftRows(), SubBytes(), and MixColumns() transformations in accordance with the AES standard. Each updated state array is destructively placed in the corresponding segment of the two or four first source vectors.

When the vector length is less than 512 bits, the most significant bits of the index are ignored to select the indexed 128-bit segment of the second source vector. This instruction is unpredicated.

This instruction is legal in Streaming SVE mode if both FEAT_SSVE_AES and FEAT_SVE_AES2 are implemented.

It has encodings from 2 classes: Two registers and Four registers

Two registers
(FEAT_SVE_AES2)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE_AES2) then EndOfDecode(Decode_UNDEF); constant integer m = UInt(Zm); constant integer dn = UInt(Zdn:'0'); integer index = UInt(i2); constant integer nreg = 2;

Four registers
(FEAT_SVE_AES2)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE_AES2) then EndOfDecode(Decode_UNDEF); constant integer m = UInt(Zm); constant integer dn = UInt(Zdn:'00'); integer index = UInt(i2); constant integer nreg = 4;