FEXPA -- A64

The FEXPA instruction computes an exponentiation acceleration operation on each floating-point element in the source vector, where the result sign is zero, the result exponent field is copied from a set of significant bits of the input fraction, and the result fraction is inserted from a lookup table indexed by the least-significant input fraction bits, and returns each result in the corresponding element of the destination vector.

This instruction is fully defined by its bit-manipulation semantics, does not generate floating-point exceptions, and does not guarantee NaN propagation.

For double-precision variants, the result element exponent is copied from the source element bits<16:6>, and the result fraction is set based on the source element to the rounded value of 2⁵² × (2^bits<5:0>/64 - 1).

For single-precision variants, the result element exponent is copied from the source element bits<13:6>, and the result fraction is set based on the source element to the rounded value of 2²³ × (2^bits<5:0>/64 - 1).

For half-precision variants, the result element exponent is copied from the source element bits<9:5>, and the result fraction is set based on the source element to the rounded value of 2¹⁰ × (2^bits<4:0>/32 - 1).

This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled, or FEAT_SME2p2 is implemented.

Note

For a double-precision floating-point input value x in the range 70,368,744,177,655 <= x < 70,368,744,179,711, the operation performed by this instruction is equivalent to computing 2^{x-70,368,744,178,687}.

For a single-precision floating-point input value x in the range 131,073 <= x < 131,327, the operation performed by this instruction is equivalent to computing 2^x-131,199.

For a half-precision floating-point input value x in the range 33 <= x < 63, the operation performed by this instruction is equivalent to computing 2^x-47.

SVE
(FEAT_SVE || FEAT_SME2p2)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME2p2) then EndOfDecode(Decode_UNDEF); if size == '00' then EndOfDecode(Decode_UNDEF); constant integer esize = 8 << UInt(size); constant integer n = UInt(Zn); constant integer d = UInt(Zd);

Assembler Symbols

<Zd>	Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

Is the size specifier, encoded in size:

size	<T>
00	RESERVED
01	H
10	S
11	D

<Zn>	Is the name of the source scalable vector register, encoded in the "Zn" field.

Operation

if IsFeatureImplemented(FEAT_SME2p2) then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(VL) operand = Z[n, VL]; bits(VL) result; for e = 0 to elements-1 constant bits(esize) element = Elem[operand, e, esize]; Elem[result, e, esize] = FPExpA(element); Z[d, VL] = result;

Internal version only: aarchmrs v2024-12_rel, pseudocode v2024-12_rel ; Build timestamp: 2024-12-15T22:18

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	1	0	0	size		1	0	0	0	0	0	1	0	1	1	1	0	Zn					Zd
											opc

FEXPA

Note

SVE(FEAT_SVE || FEAT_SME2p2)

Encoding

Decode for this encoding

Assembler Symbols

Operation

SVE
(FEAT_SVE || FEAT_SME2p2)