LDR (literal, SIMD&FP) -- A64

This instruction loads a SIMD&FP register from memory. The address that is used for the load is calculated from the PC value and an immediate offset.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Literal
(FEAT_FP)

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); constant integer t = UInt(Rt); if opc == '11' then EndOfDecode(Decode_UNDEF); constant integer size = 4 << (UInt(opc)); constant boolean nontemporal = FALSE; constant boolean tagchecked = FALSE; constant bits(64) offset = SignExtend(imm19:'00', 64);

Assembler Symbols

<St>	Is the 32-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.

<label>

Is the program label from which the data is to be loaded. Its offset from the address of this instruction, in the range +/-1MB, is encoded as "imm19" times 4.

<Dt>	Is the 64-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.

<Qt>	Is the 128-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.

Operation

constant bits(64) address = PC64 + offset; CheckFPEnabled64(); constant boolean privileged = PSTATE.EL != EL0; constant AccessDescriptor accdesc = CreateAccDescASIMD(MemOp_LOAD, nontemporal, tagchecked, privileged); constant bits(size*8) data = Mem[address, size, accdesc]; V[t, size*8] = data;

Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.

Internal version only: aarchmrs v2024-12_rel, pseudocode v2024-12_rel ; Build timestamp: 2024-12-15T22:18

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opc		0	1	1	1	0	0	imm19																			Rt
					VR