Base Instructions
SIMD&FP Instructions
SVE Instructions
SME Instructions
Index by Encoding
Shared Pseudocode
Proprietary Notice

SUBS (shifted register)

Subtract optionally-shifted register, setting flags

This instruction subtracts an optionally-shifted register value from a register value, and writes the result to the destination register. It updates the condition flags based on the result.

This instruction is used by the aliases CMP (shifted register), and NEGS.

313029282726252423222120191817161514131211109876543210
sf1101011shift0Rmimm6RnRd
opS

Encoding for the 32-bit variant

Applies when (sf == 0)

SUBS <Wd>, <Wn>, <Wm>{, <shift> #<amount>}

Encoding for the 64-bit variant

Applies when (sf == 1)

SUBS <Xd>, <Xn>, <Xm>{, <shift> #<amount>}

Decode for all variants of this encoding

if shift == '11' then EndOfDecode(Decode_UNDEF); if sf == '0' && imm6<5> == '1' then EndOfDecode(Decode_UNDEF); constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer m = UInt(Rm); constant integer datasize = 32 << UInt(sf); constant ShiftType shift_type = DecodeShift(shift); constant integer shift_amount = UInt(imm6);

Assembler Symbols

<Wd>

Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Wn>

Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field.

<Wm>

Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field.

<shift>

Is the optional shift type to be applied to the second source operand, defaulting to LSL and encoded in shift:

shift <shift>
00 LSL
01 LSR
10 ASR
11 RESERVED
<amount>

For the "32-bit" variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.

For the "64-bit" variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field.

<Xd>

Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Xn>

Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field.

<Xm>

Is the 64-bit name of the second general-purpose source register, encoded in the "Rm" field.

Alias Conditions

AliasIs preferred when
CMP (shifted register)Rd == '11111'
NEGSRn == '11111' && Rd != '11111'

Operation

constant bits(datasize) operand1 = X[n, datasize]; constant bits(datasize) operand2 = NOT(ShiftReg(m, shift_type, shift_amount, datasize)); bits(datasize) result; bits(4) nzcv; (result, nzcv) = AddWithCarry(operand1, operand2, '1'); X[d, datasize] = result; PSTATE.<N,Z,C,V> = nzcv;

Operational information

If PSTATE.DIT is 1:

Base Instructions
SIMD&FP Instructions
SVE Instructions
SME Instructions
Index by Encoding
Shared Pseudocode
Proprietary Notice

Internal version only: aarchmrs v2024-12_rel, pseudocode v2024-12_rel ; Build timestamp: 2024-12-15T22:18

Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.