BIC (vector, immediate) -- A64

This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Shifted immediate
(FEAT_AdvSIMD)

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); constant integer rd = UInt(Rd); constant integer datasize = 64 << UInt(Q); constant bits(64) imm64 = AdvSIMDExpandImm(op, cmode, a:b:c:d:e:f:g:h); constant bits(datasize) imm = Replicate(imm64, datasize DIV 64);

Assembler Symbols

<Vd>	Is the name of the SIMD&FP register, encoded in the "Rd" field.

<T>

For the "16-bit" variant: is an arrangement specifier, encoded in Q:

Q	<T>
0	4H
1	8H

For the "32-bit" variant: is an arrangement specifier, encoded in Q:

Q	<T>
0	2S
1	4S

<imm8>

Is an 8-bit immediate encoded in "a:b:c:d:e:f:g:h".

For the "16-bit" variant: is the shift amount encoded in cmode<1>:

cmode<1>	<amount>
0	0
1	8

defaulting to 0 if LSL is omitted.

For the "32-bit" variant: is the shift amount encoded in cmode<2:1>:

cmode<2:1>	<amount>
00	0
01	8
10	16
11	24

defaulting to 0 if LSL is omitted.

Operation

CheckFPAdvSIMDEnabled64(); constant bits(datasize) operand = V[rd, datasize]; V[rd, datasize] = operand AND NOT(imm);

Operational information

If PSTATE.DIT is 1:

The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.

Internal version only: aarchmrs v2024-12_rel, pseudocode v2024-12_rel ; Build timestamp: 2024-12-15T22:18

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	Q	1	0	1	1	1	1	0	0	0	0	0	a	b	c	x	x	x	1	0	1	d	e	f	g	h	Rd
		op														cmode				o2