Signed move vector element to general-purpose register
This instruction reads the signed integer from the source SIMD&FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | imm5 | 0 | 0 | 1 | 0 | 1 | 1 | Rn | Rd | ||||||||||||
| op | imm4 | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); if imm5 IN 'xx000' then EndOfDecode(Decode_UNDEF); constant integer size = LowestSetBitNZ(imm5<2:0>); constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer esize = 8 << size; constant integer datasize = 32 << UInt(Q); if datasize <= esize then EndOfDecode(Decode_UNDEF); constant integer index = UInt(imm5<4:size+1>); constant integer idxdsize = 64 << UInt(imm5<4>);
| <Wd> |
Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. |
| <Vn> |
Is the name of the SIMD&FP source register, encoded in the "Rn" field. |
| <index> |
For the "32-bit" variant: is the element index
encoded in
| ||||||||||
|
For the "64-bit" variant: is the element index
encoded in
|
| <Xd> |
Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. |
if index == 0 then CheckFPEnabled64(); else CheckFPAdvSIMDEnabled64(); constant bits(idxdsize) operand = V[n, idxdsize]; X[d, datasize] = SignExtend(Elem[operand, index, esize], datasize);
If PSTATE.DIT is 1:
Internal version only: aarchmrs v2024-12_rel, pseudocode v2024-12_rel ; Build timestamp: 2024-12-15T22:18
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