STLR

Store-release register

This instruction stores a 32-bit word or a 64-bit doubleword to a memory location, from a register. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.

It has encodings from 2 classes: No offset and Pre-index

No offset

Decode for all variants of this encoding

constant integer t = UInt(Rt); constant integer n = UInt(Rn); constant boolean wback = FALSE; constant integer offset = 0; constant boolean rt_unknown = FALSE; constant integer elsize = 8 << UInt(size); constant integer datasize = elsize; constant boolean tagchecked = n != 31;

Pre-index
(FEAT_LRCPC3)

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_LRCPC3) then EndOfDecode(Decode_UNDEF); constant boolean wback = TRUE; constant integer t = UInt(Rt); constant integer n = UInt(Rn); constant integer datasize = 8 << UInt(size); constant integer offset = -1 * (1 << UInt(size)); constant boolean tagchecked = TRUE; boolean rt_unknown = FALSE; if n == t && n != 31 then constant Constraint c = ConstrainUnpredictable(Unpredictable_WBOVERLAPST); assert c IN {Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_NONE rt_unknown = FALSE; // value stored is original value when Constraint_UNKNOWN rt_unknown = TRUE; // value stored is UNKNOWN when Constraint_UNDEF EndOfDecode(Decode_UNDEF); when Constraint_NOP EndOfDecode(Decode_NOP);