UQSHL (immediate)

Unsigned saturating shift left (immediate)

This instruction takes each vector element in the source SIMD&FP register, shifts it by an immediate value, places the results in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.

If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: Scalar and Vector

Scalar
(FEAT_AdvSIMD)

313029282726252423222120191817161514131211109876543210
011111110!= 0000immb011101RnRd
Uimmhop

Encoding

UQSHL <V><d>, <V><n>, #<shift>

Decode for this encoding

if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); if immh == '0000' then EndOfDecode(Decode_UNDEF); constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer esize = 8 << HighestSetBitNZ(immh); constant integer datasize = esize; constant integer elements = 1; constant integer shift = UInt(immh:immb) - esize; constant boolean src_unsigned = TRUE; constant boolean dst_unsigned = TRUE;

Vector
(FEAT_AdvSIMD)

313029282726252423222120191817161514131211109876543210
0Q1011110!= 0000immb011101RnRd
Uimmhop

Encoding

UQSHL <Vd>.<T>, <Vn>.<T>, #<shift>

Decode for this encoding

if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); if immh == '0000' then SEE(asimdimm); if immh<3>:Q == '10' then EndOfDecode(Decode_UNDEF); constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer esize = 8 << HighestSetBitNZ(immh); constant integer datasize = 64 << UInt(Q); constant integer elements = datasize DIV esize; constant integer shift = UInt(immh:immb) - esize; constant boolean src_unsigned = TRUE; constant boolean dst_unsigned = TRUE;

Assembler Symbols

<V>

Is a width specifier, encoded in immh:

immh <V>
0001 B
001x H
01xx S
1xxx D
<d>

Is the number of the SIMD&FP destination register, encoded in the "Rd" field.

<n>

Is the number of the SIMD&FP source register, encoded in the "Rn" field.

<shift>

For the "Scalar" variant: is the left shift amount, in the range 0 to the operand width in bits minus 1, encoded in immh:immb:

immh <shift>
0001 UInt(immh:immb) - 8
001x UInt(immh:immb) - 16
01xx UInt(immh:immb) - 32
1xxx UInt(immh:immb) - 64

For the "Vector" variant: is the left shift amount, in the range 0 to the element width in bits minus 1, encoded in immh:immb:

immh <shift>
0001 UInt(immh:immb) - 8
001x UInt(immh:immb) - 16
01xx UInt(immh:immb) - 32
1xxx UInt(immh:immb) - 64
<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>

Is an arrangement specifier, encoded in immh:Q:

immh Q <T>
0001 0 8B
0001 1 16B
001x 0 4H
001x 1 8H
01xx 0 2S
01xx 1 4S
1xxx 0 RESERVED
1xxx 1 2D
<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

Operation

CheckFPAdvSIMDEnabled64(); constant bits(datasize) operand = V[n, datasize]; bits(datasize) result; integer element; boolean sat; for e = 0 to elements-1 element = Int(Elem[operand, e, esize], src_unsigned) << shift; (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned); if sat then FPSR.QC = '1'; V[d, datasize] = result;


Internal version only: aarchmrs v2024-12_rel, pseudocode v2024-12_rel ; Build timestamp: 2024-12-15T22:18

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