Store pair of SIMD&FP registers
This instruction stores a pair of SIMD&FP registers to memory. The address used for the store is calculated from a base register value and an immediate offset.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 3 classes: Post-index , Pre-index and Signed offset
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| opc | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | imm7 | Rt2 | Rn | Rt | |||||||||||||||||||
| VR | L | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); constant boolean wback = TRUE; constant boolean postindex = TRUE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| opc | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | imm7 | Rt2 | Rn | Rt | |||||||||||||||||||
| VR | L | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); constant boolean wback = TRUE; constant boolean postindex = FALSE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| opc | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | imm7 | Rt2 | Rn | Rt | |||||||||||||||||||
| VR | L | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); constant boolean wback = FALSE; constant boolean postindex = FALSE;
| <St1> |
Is the 32-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field. |
| <St2> |
Is the 32-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Dt1> |
Is the 64-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field. |
| <Dt2> |
Is the 64-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field. |
| <Qt1> |
Is the 128-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field. |
| <Qt2> |
Is the 128-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field. |
constant integer t = UInt(Rt); constant integer t2 = UInt(Rt2); constant integer n = UInt(Rn); constant boolean nontemporal = FALSE; constant integer scale = 2 + (UInt(opc)); constant integer datasize = 8 << scale; constant bits(64) offset = LSL(SignExtend(imm7, 64), scale); constant boolean tagchecked = wback || n != 31;
CheckFPEnabled64(); bits(64) address; constant integer dbytes = datasize DIV 8; constant boolean privileged = PSTATE.EL != EL0; constant boolean ispair = IsFeatureImplemented(FEAT_LS64WB) && datasize == 128; constant AccessDescriptor accdesc = CreateAccDescASIMD(MemOp_STORE, nontemporal, tagchecked, privileged, ispair); if n == 31 then CheckSPAlignment(); address = SP[64]; else address = X[n, 64]; if !postindex then address = AddressAdd(address, offset, accdesc); if accdesc.ispair then bits(2*datasize) full_data; if BigEndian(accdesc.acctype) then full_data = V[t, datasize] : V[t2, datasize]; else full_data = V[t2, datasize] : V[t, datasize]; Mem[address, 2*dbytes, accdesc] = full_data; else constant bits(64) address2 = AddressIncrement(address, dbytes, accdesc); Mem[address , dbytes, accdesc] = V[t , datasize]; Mem[address2, dbytes, accdesc] = V[t2, datasize]; if wback then if postindex then address = AddressAdd(address, offset, accdesc); if n == 31 then SP[64] = address; else X[n, 64] = address;
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: aarchmrs v2024-12_rel, pseudocode v2024-12_rel ; Build timestamp: 2024-12-15T22:18
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