Profiling synchronization barrier
This instruction is a barrier that ensures that all existing profiling data for the current PE has been formatted, and profiling buffer addresses have been translated such that all writes to the profiling buffer have been initiated. A following DSB instruction completes when the writes to the profiling buffer have completed.
If FEAT_SPE is not implemented, this instruction executes as a NOP.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 |
| CRm | op2 | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SPE) then EndOfDecode(Decode_NOP);
if IsFeatureImplemented(FEAT_FGT) && IsFeatureImplemented(FEAT_SPEv1p5) then constant boolean trap_to_el2 = (PSTATE.EL IN {EL0, EL1} && EL2Enabled() && !IsInHost() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.PSBCSYNC == '1'); if trap_to_el2 then ExceptionRecord except = ExceptionSyndrome(Exception_LDST64BTrap); // to be renamed except.syndrome.iss = 0x3<24:0>; constant bits(64) preferred_exception_return = ThisInstrAddr(64); constant integer vect_offset = 0x0; AArch64.TakeException(EL2, except, preferred_exception_return, vect_offset); ProfilingSynchronizationBarrier();
Internal version only: aarchmrs v2024-12_rel, pseudocode v2024-12_rel ; Build timestamp: 2024-12-15T22:18
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