SHA1SU0

SHA1 schedule update 0

SHA1 schedule update 0.

Advanced SIMD
(FEAT_SHA1)

313029282726252423222120191817161514131211109876543210
01011110000Rm001100RnRd
sizeopcode

Encoding

SHA1SU0 <Vd>.4S, <Vn>.4S, <Vm>.4S

Decode for this encoding

if !IsFeatureImplemented(FEAT_SHA1) then EndOfDecode(Decode_UNDEF); constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer m = UInt(Rm);

Assembler Symbols

<Vd>

Is the name of the SIMD&FP source and destination register, encoded in the "Rd" field.

<Vn>

Is the name of the second SIMD&FP source register, encoded in the "Rn" field.

<Vm>

Is the name of the third SIMD&FP source register, encoded in the "Rm" field.

Operation

AArch64.CheckFPAdvSIMDEnabled(); constant bits(128) operand1 = V[d, 128]; constant bits(128) operand2 = V[n, 128]; constant bits(128) operand3 = V[m, 128]; bits(128) result = operand2<63:0> : operand1<127:64>; result = result EOR operand1 EOR operand3; V[d, 128] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: aarchmrs v2024-12_rel, pseudocode v2024-12_rel ; Build timestamp: 2024-12-15T22:18

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