Signed unpack and extend half of vector
Unpack elements from the lowest or highest half of the source vector and then sign-extend them to place in elements of twice their size within the destination vector. This instruction is unpredicated.
It has encodings from 2 classes: High half and Low half
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | size | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | Zn | Zd | |||||||||
| U | H | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); if size == '00' then EndOfDecode(Decode_UNDEF); constant integer esize = 8 << UInt(size); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant boolean unsigned = FALSE; constant boolean hi = TRUE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | size | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | Zn | Zd | |||||||||
| U | H | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); if size == '00' then EndOfDecode(Decode_UNDEF); constant integer esize = 8 << UInt(size); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant boolean unsigned = FALSE; constant boolean hi = FALSE;
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Zn> |
Is the name of the source scalable vector register, encoded in the "Zn" field. |
| <Tb> |
Is the size specifier,
encoded in
|
CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; constant integer hsize = esize DIV 2; constant integer offset = if hi then elements else 0; constant bits(VL) operand = Z[n, VL]; bits(VL) result; for e = 0 to elements-1 constant bits(hsize) element = Elem[operand, e + offset, hsize]; Elem[result, e, esize] = Extend(element, esize, unsigned); Z[d, VL] = result;
If PSTATE.DIT is 1:
Internal version only: aarchmrs v2024-12_rel, pseudocode v2024-12_rel ; Build timestamp: 2024-12-15T22:18
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.